{"id":291362,"date":"2018-10-25T16:40:02","date_gmt":"2018-10-25T12:40:02","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=291362"},"modified":"-0001-11-30T00:00:00","modified_gmt":"2018-10-25T12:40:02","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=291362","title":{"rendered":"STM32H7 \u2014 \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u0431\u0435\u0437 HAL"},"content":{"rendered":"\n
\u041d\u0435 \u0442\u0430\u043a \u0434\u0430\u0432\u043d\u043e \u043a\u043e\u043c\u043f\u0430\u043d\u0438\u044f STM \u0432\u044b\u043f\u0443\u0441\u0442\u0438\u043b\u0430 \u043d\u0430 \u0440\u044b\u043d\u043e\u043a \u043e\u0447\u0435\u043d\u044c \u043c\u043e\u0449\u043d\u0443\u044e, \u043f\u043e \u043c\u0435\u0440\u043a\u0430\u043c \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u043e\u0432, \u043b\u0438\u043d\u0435\u0439\u043a\u0443 \u043a\u0440\u0438\u0441\u0442\u0430\u043b\u043b\u043e\u0432 STM32H7. \u0427\u0442\u043e \u043c\u0435\u043d\u044f \u0432 \u043d\u0435\u0439 \u043f\u0440\u0438\u0432\u043b\u0435\u043a\u043b\u043e:
\u2014 \u043f\u043e\u0432\u044b\u0448\u0435\u043d\u043d\u0430\u044f \u0447\u0430\u0441\u0442\u043e\u0442\u0430 \u044f\u0434\u0440\u0430 \u0434\u043e 400 \u041c\u0413\u0446
\u2014 \u0443\u0432\u0435\u043b\u0438\u0447\u0435\u043d\u043d\u044b\u0439 \u043e\u0431\u044a\u0435\u043c \u041e\u0417\u0423, \u0434\u043e 1 \u041c\u0411
\u2014 16 \u0440\u0430\u0437\u0440\u044f\u0434\u043d\u044b\u0439 \u0410\u0426\u041f
\u2014 pin-to-pin \u0441\u043e\u0432\u043c\u0435\u0441\u0442\u0438\u043c\u043e\u0441\u0442\u044c \u0441 \u0441\u0435\u0440\u0438\u0439 F7<\/p>\n

\u041e\u0442\u043b\u0438\u0447\u043d\u043e \u043f\u043e\u0434\u0443\u043c\u0430\u043b \u044f, \u0437\u0430\u043f\u0430\u044f\u043b \u043d\u0430 \u043f\u043b\u0430\u0442\u0443 \u043a\u0440\u0438\u0441\u0442\u0430\u043b\u043b STM32H743IIT6 \u0432\u043c\u0435\u0441\u0442\u043e STM32F746IGT6 \u0438 \u043d\u0430\u0447\u0430\u043b \u043d\u043e\u0432\u044b\u0439 \u043f\u0440\u043e\u0435\u043a\u0442 \u0432 SW4STM32. <\/p>\n

<\/a><\/p>\n

\u0414\u043b\u044f \u0440\u0430\u0441\u0447\u0435\u0442\u0430 \u043a\u043e\u044d\u0444\u0444\u0438\u0446\u0438\u0435\u043d\u0442\u043e\u0432 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0435\u0439 \u0438 \u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u0435\u0439 \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430 \u0443\u0434\u043e\u0431\u043d\u043e \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0432\u043a\u043b\u0430\u0434\u043a\u043e\u0439 Clock Configuration \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b STM32CubeMX.<\/p>\n

\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0438 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f:
\u2014 \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u043a\u0432\u0430\u0440\u0446 \u2014 8 \u041c\u0413\u0446
\u2014 \u0438\u0441\u0442\u043e\u0447\u043d\u0438\u043a \u0447\u0430\u0441\u0442\u043e\u0442\u044b \u0434\u043b\u044f PLL1 \u2014 \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u043a\u0432\u0430\u0440\u0446 (HSE)
\u2014 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u0434\u043b\u044f PLL1 \u2014 4 (DIVM1)
\u2014 \u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044c PLL1 \u2014 400 (DIVN1)
\u2014 \u0432\u044b\u0445\u043e\u0434\u043d\u044b\u0435 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0438 \u2014 2 (DIVP1, DIVQ1, DIVR1)<\/p>\n

\u0421\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0435\u043d\u043d\u043e, \u0447\u0430\u0441\u0442\u043e\u0442\u0430 \u044f\u0434\u0440\u0430 (SYSCLK)- 400 \u041c\u0413\u0446.
<\/p>\n

\u041a\u0440\u043e\u043c\u0435 STM32CubeMX \u0435\u0441\u0442\u044c \u0435\u0449\u0435 \u043d\u0430\u0431\u043e\u0440 \u00abSTM32CubeH7 firmware package\u00bb, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0431\u043e\u043b\u044c\u0448\u043e\u0435 \u043a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u043f\u0440\u0438\u043c\u0435\u0440\u043e\u0432 \u0434\u043b\u044f \u0440\u0430\u0431\u043e\u0442\u044b \u0441 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0435\u0439 \u0434\u043b\u044f STM32H7. \u0418\u043c\u0435\u043d\u043d\u043e \u0438\u0437 \u043d\u0435\u0433\u043e \u0431\u044b\u043b\u0430 \u0432\u0437\u044f\u0442\u0430 \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u044c \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430.<\/p>\n

\u0418\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f \u0438 \u043a\u043e\u043c\u043c\u0435\u043d\u0442\u0430\u0440\u0438\u0438 \u0432\u0437\u044f\u0442\u044b \u0438\u0437 \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u0445 \u0438\u0441\u0442\u043e\u0447\u043d\u0438\u043a\u043e\u0432:
\u2014 SystemClock_Config \u0438\u0437 STM32CubeH7 firmware package
\u2014 Reference manual STM32H743\/753 and STM32H750 advanced ARM-based 32-bit
MCUs
\u2014 Datasheet STM32H743xI<\/p>\n

\u0418\u0442\u0430\u043a, \u043d\u0430\u0447\u043d\u0435\u043c.
1. \u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u0432\u043d\u0435\u0448\u043d\u0435\u0433\u043e \u043a\u0432\u0430\u0440\u0446\u0430 \u0438 \u043e\u0436\u0438\u0434\u0430\u043d\u0438\u0435 \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438.
\/\/ Enable HSE
RCC->CR |= RCC_CR_HSEON;
\/\/ Wait till HSE is ready
while((RCC->CR & RCC_CR_HSERDY) == 0);<\/code><\/p>\n

2. \u0423\u043a\u0430\u0437\u0430\u043d\u0438\u0435 \u0438\u0441\u0442\u043e\u0447\u043d\u0438\u043a\u0430 \u0447\u0430\u0441\u0442\u043e\u0442\u044b \u0434\u043b\u044f PLL1 \u2014 \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u043a\u0432\u0430\u0440\u0446.
\/\/RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE;
RCC -> PLLCKSELR |= RCC_PLLCKSELR_PLLSRC_HSE;<\/code><\/p>\n

3. \u0417\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044f \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u0440\u0430\u0432\u043d\u044b\u043c 4.
\/\/PLLM = 4
RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_5; \/\/0
RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_4; \/\/0
RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_3; \/\/0
RCC -> PLLCKSELR |= RCC_PLLCKSELR_DIVM1_2; \/\/1
RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_1; \/\/0
RCC -> PLLCKSELR &= ~RCC_PLLCKSELR_DIVM1_0; \/\/0<\/code><\/p>\n

4. \u041c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044c N \u0438 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0438 P, Q, R
\/\/PLL1DIVR bits
\/\/DIVN1[8:0] 0 - 8 PLLN = 400
\/\/DIVP1[6:0] 9 - 15 PLLP = 2
\/\/DIVQ1[6:0] 16 - 22 PLLQ = 2
\/\/DIVR1[6:0] 24 - 30 PLLR = 2
RCC -> PLL1DIVR |= 0x0101038F;<\/code><\/p>\n

5. \u0414\u0440\u043e\u0431\u043d\u044b\u0439 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u0447\u0430\u0441\u0442\u043e\u0442\u044b PLL (\u0435\u0441\u043b\u0438 \u043d\u0443\u0436\u0435\u043d)
\/\/ \/* Configure PLL PLL1FRACN *\/
\/\/__HAL_RCC_PLLFRACN_CONFIG(RCC_OscInitStruct->PLL.PLLFRACN);
RCC -> PLL1FRACR = 0;<\/code><\/p>\n

6. \u0423\u043a\u0430\u0437\u0430\u043d\u0438\u0435 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d\u0430 \u0432\u0445\u043e\u0434\u043d\u043e\u0439 \u0447\u0430\u0441\u0442\u043e\u0442\u044b PLL1
\/* Select PLL1 input reference frequency range: VCI *\/
\/\/__HAL_RCC_PLL_VCIRANGE(RCC_OscInitStruct->PLL.PLLRGE) ;
RCC->PLLCFGR |= RCC_PLLCFGR_PLL1RGE_3;<\/code><\/p>\n

7. \u0423\u043a\u0430\u0437\u0430\u043d\u0438\u0435 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d\u0430 \u0432\u044b\u0445\u043e\u0434\u043d\u043e\u0439 \u0447\u0430\u0441\u0442\u043e\u0442\u044b PLL1
\/* Select PLL1 output frequency range : VCO *\/
\/\/__HAL_RCC_PLL_VCORANGE(RCC_OscInitStruct->PLL.PLLVCOSEL) ;
RCC->PLLCFGR &= ~RCC_PLLCFGR_PLL1VCOSEL;<\/code><\/p>\n

8. \u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u0432\u044b\u0445\u043e\u0434\u043d\u044b\u0445 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0435\u0439 PLL1: P, Q, R
\/* Enable PLL System Clock output. *\/
\/\/ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVP);
\/\/Bit 16 DIVP1EN: PLL1 DIVP divider output enable
RCC->PLLCFGR |= RCC_PLLCFGR_DIVP1EN;<\/p>\n

\/* Enable PLL1Q Clock output. *\/
\/\/__HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVQ);
RCC->PLLCFGR |= RCC_PLLCFGR_DIVQ1EN;<\/p>\n

\/* Enable PLL1R Clock output. *\/
\/\/ __HAL_RCC_PLLCLKOUT_ENABLE(RCC_PLL1_DIVR);
RCC->PLLCFGR |= RCC_PLLCFGR_DIVR1EN;<\/code><\/p>\n

9. \u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u0434\u0440\u043e\u0431\u043d\u043e\u0433\u043e \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044f.
\/* Enable PLL1FRACN . *\/
\/\/__HAL_RCC_PLLFRACN_ENABLE();
RCC->PLLCFGR |= RCC_PLLCFGR_PLL1FRACEN;<\/code><\/p>\n

10. \u041f\u0443\u0441\u043a PLL1 \u0438 \u043e\u0436\u0438\u0434\u0430\u043d\u0438\u0435 \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438
\/* Enable the main PLL. *\/
\/\/__HAL_RCC_PLL_ENABLE();
RCC->CR |= RCC_CR_PLLON;
while((RCC->CR & RCC_CR_PLL1RDY) == 0);<\/code><\/p>\n

PLL1 \u043d\u0430\u0441\u0442\u0440\u043e\u0435\u043d \u0438 \u0437\u0430\u043f\u0443\u0449\u0435\u043d. \u0422\u0435\u043f\u0435\u0440\u044c \u0432\u044b\u0431\u043e\u0440 \u0438\u0441\u0442\u043e\u0447\u043d\u0438\u043a\u0430 \u0447\u0430\u0441\u0442\u043e\u0442\u044b SYSCLK \u0438 \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0435\u0439 \u0448\u0438\u043d.<\/p>\n

11. \u0414\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u043d\u0430 2 HPRE
\/\/RCC_ClkInitStruct.AHBCLKDivider = RCC_HCLK_DIV2;
\/\/ MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, RCC_ClkInitStruct->AHBCLKDivider);
\/\/HPRE[3:0]: D1 domain AHB prescaler
\/\/1000: rcc_hclk3 = sys_d1cpre_ck \/ 2
RCC -> D1CFGR |= RCC_D1CFGR_HPRE_3; \/\/1
RCC -> D1CFGR &= ~RCC_D1CFGR_HPRE_2; \/\/0
RCC -> D1CFGR &= ~RCC_D1CFGR_HPRE_1; \/\/0
RCC -> D1CFGR &= ~RCC_D1CFGR_HPRE_0; \/\/0<\/code><\/p>\n

12. \u0411\u0435\u0437 \u0434\u0435\u043b\u0435\u043d\u0438\u044f D1CPRE
\/\/RCC_ClkInitStruct.SYSCLKDivider = RCC_SYSCLK_DIV1;
\/\/MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, RCC_ClkInitStruct->SYSCLKDivider);
\/\/D1CPRE[3:0]: D1 domain Core prescaler
\/\/0xxx: sys_ck not divided (default after reset)
RCC -> D1CFGR &= ~RCC_D1CFGR_D1CPRE_3; \/\/0
RCC -> D1CFGR &= ~RCC_D1CFGR_D1CPRE_2; \/\/0
RCC -> D1CFGR &= ~RCC_D1CFGR_D1CPRE_1; \/\/0
RCC -> D1CFGR &= ~RCC_D1CFGR_D1CPRE_0; \/\/0<\/code> <\/p>\n

13. \u0417\u0430\u0434\u0430\u0435\u043c PLL1 \u043a\u0430\u043a \u0438\u0441\u0442\u043e\u0447\u043d\u0438\u043a SYSCLK \u0438 \u043e\u0436\u0438\u0434\u0430\u0435\u043c \u0433\u043e\u0442\u043e\u0432\u043d\u043e\u0441\u0442\u0438
\/\/RCC_ClkInitStruct.SYSCLKSource = RCC_SYSCLKSOURCE_PLLCLK;
\/\/MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, RCC_ClkInitStruct->SYSCLKSource);
\/\/SW[2:0]: System clock switch
\/\/011: PLL1 selected as system clock (pll1_p_ck)<\/p>\n

RCC->CFGR &= ~RCC_CFGR_SW_2; \/\/0
RCC->CFGR |= RCC_CFGR_SW_1; \/\/1
RCC->CFGR |= RCC_CFGR_SW_0; \/\/1<\/p>\n

while((RCC->CFGR & RCC_CFGR_SWS) != RCC_CFGR_SWS_PLL1);<\/code> <\/p>\n

14. \u0414\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u043d\u0430 2 D1PPRE
\/\/D1PCLK1 Configuration
\/\/RCC_ClkInitStruct.APB3CLKDivider = RCC_APB3_DIV2;
\/\/MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, RCC_ClkInitStruct->APB3CLKDivider);
\/\/Bits 6:4 D1PPRE[2:0]: D1 domain APB3 prescaler
\/\/100: rcc_pclk3 = rcc_hclk3 \/ 2
RCC -> D1CFGR |= RCC_D1CFGR_D1PPRE_2;
RCC -> D1CFGR &= ~RCC_D1CFGR_D1PPRE_1;
RCC -> D1CFGR &= ~RCC_D1CFGR_D1PPRE_0;<\/code> <\/p>\n

15. \u0414\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u043d\u0430 2 D2PPRE1
\/\/PCLK1 Configuration
\/\/RCC_ClkInitStruct.APB1CLKDivider = RCC_APB1_DIV2;
\/\/MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, (RCC_ClkInitStruct->APB1CLKDivider));
\/\/Bits 6:4 D2PPRE1[2:0]: D2 domain APB1 prescaler
\/\/100: rcc_pclk1 = rcc_hclk1 \/ 2
RCC -> D2CFGR |= RCC_D2CFGR_D2PPRE1_2;
RCC -> D2CFGR &= ~RCC_D2CFGR_D2PPRE1_1;
RCC -> D2CFGR &= ~RCC_D2CFGR_D2PPRE1_0;<\/code> <\/p>\n

16. \u0414\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u043d\u0430 2 D2PPRE2
\/\/PCLK2 Configuration
\/\/RCC_ClkInitStruct.APB2CLKDivider = RCC_APB2_DIV2;
\/\/MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, (RCC_ClkInitStruct->APB2CLKDivider));
\/\/Bits 10:8 D2PPRE2[2:0]: D2 domain APB2 prescaler
\/\/100: rcc_pclk2 = rcc_hclk1 \/ 2
RCC -> D2CFGR |= RCC_D2CFGR_D2PPRE2_2;
RCC -> D2CFGR &= ~RCC_D2CFGR_D2PPRE2_1;
RCC -> D2CFGR &= ~RCC_D2CFGR_D2PPRE2_0;<\/code> <\/p>\n

17. \u0414\u0435\u043b\u0438\u0442\u0435\u043b\u044c \u043d\u0430 2 D3PPRE
\/\/D3PCLK1 Configuration
\/\/RCC_ClkInitStruct.APB4CLKDivider = RCC_APB4_DIV2;
\/\/MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, (RCC_ClkInitStruct->APB4CLKDivider) );
\/\/Bits 6:4 D3PPRE[2:0]: D3 domain APB4 prescaler
\/\/100: rcc_pclk4 = rcc_hclk4 \/ 2
RCC -> D3CFGR |= RCC_D3CFGR_D3PPRE_2;
RCC -> D3CFGR &= ~RCC_D3CFGR_D3PPRE_1;
RCC -> D3CFGR &= ~RCC_D3CFGR_D3PPRE_0;<\/code> <\/p>\n

\u0414\u043b\u044f \u0442\u043e\u0433\u043e \u0447\u0442\u043e\u0431\u044b \u0443\u0431\u0435\u0434\u0438\u0442\u044c\u0441\u044f, \u0447\u0442\u043e \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u0438 \u0437\u0430\u043f\u0443\u0441\u043a \u043f\u0440\u043e\u0448\u043b\u0438 \u0443\u0441\u043f\u0435\u0448\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c \u0432\u044b\u0445\u043e\u0434 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430 MCO2. \u041d\u0430 \u044d\u0442\u043e\u043c \u0432\u044b\u0445\u043e\u0434\u0435 \u0434\u043e\u043b\u0436\u043d\u0430 \u0431\u044b\u0442\u044c \u0447\u0430\u0441\u0442\u043e\u0442\u0430 26.666 \u041c\u0413\u0446 \u043f\u0440\u0438 \u0434\u0435\u043b\u0438\u0442\u0435\u043b\u0435 \u0432\u044b\u0445\u043e\u0434\u0430 15.<\/p>\n

<\/p>\n

\u041e\u0442\u043b\u0438\u0447\u043d\u043e. \u0427\u0430\u0441\u0442\u043e\u0442\u0430 \u043f\u0440\u0438\u0441\u0443\u0442\u0441\u0442\u0432\u0443\u0435\u0442, \u0437\u043d\u0430\u0447\u0438\u0442 \u0432\u0441\u0435 \u0441\u0434\u0435\u043b\u0430\u043d\u043e \u043f\u0440\u0430\u0432\u0438\u043b\u044c\u043d\u043e.<\/p><\/div>\n