{"id":308240,"date":"2020-08-10T09:00:56","date_gmt":"2020-08-10T09:00:56","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=308240"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=308240","title":{"rendered":"\u0410\u043d\u0430\u043b\u0438\u0437 \u0434\u0430\u043d\u043d\u044b\u0445 \u0438\u0437 \u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0435\u0433\u043e \u0441\u043b\u0438\u0432\u0430 Intel"},"content":{"rendered":"\n<div class=\"post__text post__text-html post__text_v1\" id=\"post-content-body\" data-io-article-url=\"https:\/\/habr.com\/ru\/post\/514458\/\">\u042f \u043f\u043e\u0440\u044b\u043b\u0441\u044f \u0432 20 \u0433\u0438\u0433\u0430\u0431\u0430\u0439\u0442\u0430\u0445 <a href=\"https:\/\/t.me\/exconfidential\/590\" rel=\"nofollow\">\u0441\u043b\u0438\u0442\u044b\u0445 \u0434\u0430\u043d\u043d\u044b\u0445<\/a> \u0441 \u043d\u0435\u0437\u0430\u0449\u0438\u0449\u0451\u043d\u043d\u043e\u0433\u043e CDN \u0438\u043d\u0442\u0435\u043b\u0430 \u0432 \u043f\u043e\u0438\u0441\u043a\u0430\u0445 \u0438\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u043e\u0433\u043e \u0438 \u043e\u0446\u0435\u043d\u043a\u0438 \u0441\u0435\u0440\u044c\u0451\u0437\u043d\u043e\u0441\u0442\u0438 \u044d\u0442\u043e\u0439 \u0443\u0442\u0435\u0447\u043a\u0438.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/x6\/qt\/q3\/x6qtq3dkqjerex4fpveywhf6dlq.png\"><br \/>  <i>\u041a\u0414\u041f\u0412. \u041f\u0440\u043e\u0442\u043e\u0442\u0438\u043f \u043d\u043e\u0443\u0442\u0431\u0443\u043a\u0430 \u043d\u0430 Tiger Lake.<\/i><\/p>\n<h4>\u041a\u0440\u0430\u0442\u043a\u043e\u0435 \u0440\u0435\u0437\u044e\u043c\u0435<\/h4>\n<p>  \u0411\u043e\u043b\u044c\u0448\u0430\u044f \u0447\u0430\u0441\u0442\u044c \u0441\u043b\u0438\u0442\u043e\u0439 \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u0438 \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0430 \u0434\u043b\u044f OEM\/ODM \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432 \u0438 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u0439, \u043d\u043e \u0437\u0430\u0438\u043d\u0442\u0435\u0440\u0435\u0441\u0443\u0435\u0442 \u044d\u043d\u0442\u0443\u0437\u0438\u0430\u0441\u0442\u043e\u0432, \u0438\u0441\u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u0445 BIOS \u0438 \u043d\u0435\u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0435 \u0440\u0435\u0436\u0438\u043c\u044b \u0440\u0430\u0431\u043e\u0442\u044b \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Intel. \u0412 \u043d\u0438\u0445 \u043d\u0435\u0442 \u0432\u043d\u0443\u0442\u0440\u0435\u043d\u043d\u0435\u0439 \u0438\u043d\u0442\u0435\u043b\u043e\u0432\u0441\u043a\u043e\u0439 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u0438, \u043a\u0440\u0438\u0442\u0438\u0447\u043d\u043e\u0439 \u043a \u043e\u0431\u043d\u0430\u0440\u043e\u0434\u043e\u0432\u0430\u043d\u0438\u044e, \u0438\u043b\u0438 \u0441\u043f\u043e\u0441\u043e\u0431\u043d\u043e\u0439 \u0440\u0430\u0441\u043a\u0440\u044b\u0442\u044c \u0441\u0435\u043a\u0440\u0435\u0442\u043d\u044b\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438. \u0422\u0430\u043a\u0436\u0435 \u0437\u0434\u0435\u0441\u044c \u043d\u0435 \u043d\u0430\u0439\u0442\u0438 \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u0438 \u043e \u043d\u0435\u0438\u0437\u0432\u0435\u0441\u0442\u043d\u044b\u0445 \u0440\u0430\u043d\u0435\u0435 \u0443\u044f\u0437\u0432\u0438\u043c\u043e\u0441\u0442\u044f\u0445.<br \/>  <a name=\"habracut\"><\/a>  <\/p>\n<h4>\u0424\u0430\u0439\u043b\u044b<\/h4>\n<p>  \u041d\u0435 \u0443\u043a\u0430\u0437\u0430\u043d\u043d\u044b\u0435 \u0437\u0434\u0435\u0441\u044c \u0444\u0430\u0439\u043b\u044b \u043b\u0438\u0431\u043e \u044f\u0432\u043b\u044f\u044e\u0442\u0441\u044f \u043f\u0440\u043e\u0441\u0442\u043e \u043d\u043e\u0432\u043e\u0441\u0442\u043d\u044b\u043c\u0438 \u043e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u044f\u043c\u0438 Intel, \u043b\u0438\u0431\u043e \u0431\u0438\u043d\u0430\u0440\u043d\u0438\u043a\u0430\u043c\u0438 \u0431\u0435\u0437 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u0438\u043b\u0438 \u043d\u0435 \u0437\u0430\u0441\u043b\u0443\u0436\u0438\u0432\u0430\u044e\u0442 \u0432\u043d\u0438\u043c\u0430\u043d\u0438\u044f.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 576931-potter-city-576931-v1-0-schem.pdf<\/b><\/p>\n<p>  \u0414\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u044b, \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u044b, \u0440\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0430\u0446\u0438\u0438 \u043f\u043e \u0440\u0430\u0437\u0432\u043e\u0434\u043a\u0435 \u043c\u0430\u0442\u0435\u0440\u0438\u043d\u0441\u043a\u0438\u0445 \u043f\u043b\u0430\u0442 \u0441 \u0447\u0435\u0442\u044b\u0440\u044c\u043c\u044f \u0441\u043e\u043a\u0435\u0442\u0430\u043c\u0438 \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 \u043d\u0430 \u044f\u0434\u0440\u0435 SandyBridge \u043e\u0442 2010 \u0433\u043e\u0434\u0430.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/lt\/50\/hj\/lt50hjrv5rkmwkliehoefsmuyee.png\"><br \/>  <i>\u0418\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u043e, \u0447\u0442\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e\u0442\u0441\u044f \u0442\u043e\u043b\u044c\u043a\u043e \u043f\u0435\u0440\u0435\u043d\u0430\u0437\u043d\u0430\u0447\u0430\u0435\u043c\u044b\u0435 \u043b\u0438\u043d\u0438\u0438 PCIe \u043e\u0434\u043d\u043e\u0433\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430<\/i><\/p>\n<p>  \u041d\u0430 \u043e\u0441\u0442\u0430\u043b\u044c\u043d\u044b\u0445 \u0441\u0442\u0440\u0430\u043d\u0438\u0446\u0430\u0445 \u0434\u0430\u043d\u043d\u044b\u0435 \u043f\u043e \u0432\u0441\u0435\u043c \u0443\u043a\u0430\u0437\u0430\u043d\u043d\u044b\u043c \u043d\u0430 \u0434\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u0435 \u0431\u043b\u043e\u043a\u0430\u043c. \u041c\u043e\u0436\u0435\u0442 \u0431\u044b\u0442\u044c \u043f\u043e\u043b\u0435\u0437\u043d\u043e \u0434\u043b\u044f \u0430\u043a\u0430\u0434\u0435\u043c\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u0437\u043d\u0430\u043d\u0438\u0439, \u043d\u0430 \u0440\u0435\u0430\u043b\u044c\u043d\u044b\u0435 \u043c\u0430\u0442\u0435\u0440\u0438\u043d\u0441\u043a\u0438\u0435 \u043f\u043b\u0430\u0442\u044b \u043f\u0435\u0440\u0435\u043b\u043e\u0436\u0438\u0442\u044c \u043d\u0435 \u043f\u043e\u043b\u0443\u0447\u0438\u0442\u0441\u044f.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/ki\/ch\/td\/kichtdxfbcxxjesdwlqo_-jxnau.png\"><br \/>  <i>\u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440 \u0431\u043b\u043e\u043a\u0438\u0440\u043e\u0432\u043e\u0447\u043d\u044b\u0435 \u043a\u043e\u043d\u0434\u0435\u043d\u0441\u0430\u0442\u043e\u0440\u044b \u0434\u043b\u044f \u0440\u0430\u0437\u043d\u044b\u0445 \u0446\u0435\u043f\u0435\u0439 \u0441 \u0443\u043a\u0430\u0437\u0430\u043d\u0438\u0435\u043c \u0442\u043e\u0447\u043d\u043e\u0439 \u043c\u0430\u0440\u043a\u0438\u0440\u043e\u0432\u043a\u0438 \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u0430 \u0438 \u0440\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0430\u0446\u0438\u0438 \u043f\u043e \u0440\u0430\u0437\u043c\u0435\u0449\u0435\u043d\u0438\u044e<\/i><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 367228-367228-rev-1-5.pdf<\/b><\/p>\n<p>  \u0414\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f \u0441 \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u0430\u043c\u0438 \u0434\u043b\u044f \u0447\u0435\u0433\u043e-\u0442\u043e \u0432\u0440\u043e\u0434\u0435 \u043e\u0442\u043b\u0430\u0434\u043e\u0447\u043d\u043e\u0439\/\u0434\u0435\u043c\u043e\u043d\u0441\u0442\u0440\u0430\u0446\u0438\u043e\u043d\u043d\u043e\u0439 \u043f\u043b\u0430\u0442\u044b \u0434\u043b\u044f \u043f\u0435\u0440\u0432\u043e\u0433\u043e \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u044f \u00ab\u0430\u0442\u043e\u043c\u043e\u0432\u00bb.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/0i\/fq\/uz\/0ifquzpme8tr5mbwsr2fjmxwhmy.png\"><br \/>  <i>\u0421\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u043d\u0430\u044f \u0441\u0445\u0435\u043c\u0430 \u0441 \u043f\u043e\u044f\u0441\u043d\u0435\u043d\u0438\u044f\u043c\u0438 \u043f\u043e \u0440\u0430\u0431\u043e\u0442\u0435 \u0446\u0435\u043f\u0438 \u043f\u0438\u0442\u0430\u043d\u0438\u044f \u043f\u0440\u0438 \u0432\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0438<\/i><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 544767-intel-ethernet-connection-i219-reference-schematic-rev1-0.pdf<\/b> <\/p>\n<p>  \u0422\u0438\u043f\u043e\u0432\u0430\u044f \u0441\u0445\u0435\u043c\u0430 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u044f \u0433\u0438\u0433\u0430\u0431\u0438\u0442\u043d\u043e\u0433\u043e \u0441\u0435\u0442\u0435\u0432\u043e\u0433\u043e \u0430\u0434\u0430\u043f\u0442\u0435\u0440\u0430 <a href=\"https:\/\/ark.intel.com\/content\/www\/ru\/ru\/ark\/products\/82186\/intel-ethernet-connection-i219-v.html\" rel=\"nofollow\">i219<\/a>, 2015 \u0433\u043e\u0434.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/de\/sz\/ec\/deszecpxybzdbxoib60cha57s7k.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 555388-purley-platform-power-delivery-schematic-layout-checklist-rev1-1.xlsx<\/b><\/p>\n<p>  \u0422\u0430\u0431\u043b\u0438\u0446\u0430 \u0434\u043b\u044f \u0437\u0430\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u044f \u0438\u043d\u0436\u0435\u043d\u0435\u0440\u0430\u043c\u0438 \u0438\u043b\u0438 \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0449\u0438\u043a\u0430\u043c\u0438 \u043f\u043b\u0430\u0442 \u0441\u0442\u043e\u0440\u043e\u043d\u043d\u0438\u0445 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u0439. \u041d\u0443\u0436\u043d\u043e \u043f\u0440\u043e\u0432\u0435\u0440\u0438\u0442\u044c \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u0443 \u0438 \u0442\u043e\u043f\u043e\u043b\u043e\u0433\u0438\u044e (\u0430 \u043a\u043e\u043d\u043a\u0440\u0435\u0442\u043d\u043e \u0441\u0438\u043b\u043e\u0432\u0443\u044e \u0447\u0430\u0441\u0442\u044c) \u043d\u0430 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u0435 \u0440\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0443\u0435\u043c\u044b\u043c \u0442\u0440\u0435\u0431\u043e\u0432\u0430\u043d\u0438\u044f\u043c. \u0412 \u043a\u043e\u043d\u0446\u0435 excel \u043f\u043e\u0441\u0447\u0438\u0442\u0430\u0435\u0442 \u00ab\u043e\u0447\u043a\u0438\u00bb \u0438 \u0432\u044b\u0434\u0430\u0441\u0442 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442 \u0432 \u043f\u0440\u043e\u0446\u0435\u043d\u0442\u0430\u0445:<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/e9\/4r\/qf\/e94rqfkykjvjgu0u6t9ry79mqe4.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 621487-cml-itbmt3-ta-ww14-2020.pdf<\/b> <\/p>\n<p>  \u041e\u0431\u0449\u0435\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u0435 \u043f\u0440\u0438\u043d\u0446\u0438\u043f\u043e\u0432 \u0440\u0430\u0431\u043e\u0442\u044b \u0442\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u0438 Turbo Boost 3.0 \u0432 Kaby Lake (\u044d\u0442\u043e \u0441\u0435\u0434\u044c\u043c\u043e\u0435 \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u0435 Core \u043e\u0442 2017 \u0433\u043e\u0434\u0430). \u0412 \u0447\u0430\u0441\u0442\u043d\u043e\u0441\u0442\u0438 \u043e\u043f\u0438\u0441\u0430\u043d\u043e, \u0438\u0437 \u043a\u0430\u043a\u0438\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u043f\u043e\u0434\u0441\u0438\u0441\u0442\u0435\u043c\u0435 BIOS \u0441\u0447\u0438\u0442\u044b\u0432\u0430\u0442\u044c \u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u044b\u0435 \u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u0438 \u0431\u0443\u0441\u0442\u0430 \u043e\u0442\u0434\u0435\u043b\u044c\u043d\u044b\u0445 \u044f\u0434\u0435\u0440.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/kb\/_s\/v_\/kb_sv_elwl7sv4zeh3xvhpicgsk.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 20170823_HDCP_EB-1.0_MEDIA_Eng_release.tar.gz<\/b> <\/p>\n<p>  \u0414\u0435\u043c\u043e\u043d \u0438 \u0442\u0435\u0441\u0442\u043e\u0432\u0430\u044f \u0443\u0442\u0438\u043b\u0438\u0442\u0430 \u0434\u043b\u044f \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0438 \u0440\u0430\u0431\u043e\u0442\u044b <a href=\"https:\/\/ru.wikipedia.org\/wiki\/HDCP\" rel=\"nofollow\">HDCP<\/a> \u043f\u043e\u0434 Arch Linux. \u0412 \u0430\u0440\u0445\u0438\u0432\u0435 \u0442\u043e\u043b\u044c\u043a\u043e \u0431\u0438\u043d\u0430\u0440\u043d\u0438\u043a\u0438 \u0438 readme.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b BVT_Package_10.0.0.1086.exe<\/b><\/p>\n<p>  \u0423\u0442\u0438\u043b\u0438\u0442\u0430 \u0438 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0438 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u044f \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0442\u0440\u0435\u0431\u043e\u0432\u0430\u043d\u0438\u044f\u043c Intel \u0434\u043b\u044f \u043c\u0430\u0440\u043a\u0438\u0440\u043e\u0432\u043a\u0438 \u043a\u043e\u043c\u043f\u044c\u044e\u0442\u0435\u0440\u0430 \u043b\u043e\u0433\u043e\u0442\u0438\u043f\u043e\u043c <a href=\"https:\/\/www.intel.ru\/content\/www\/ru\/ru\/architecture-and-technology\/vpro\/vpro-platform-general.html\" rel=\"nofollow\">Intel vPro<\/a>. \u0423\u0442\u0438\u043b\u0438\u0442\u0430 \u043f\u0440\u043e\u0432\u043e\u0434\u0438\u0442 \u043d\u0435\u0441\u043a\u043e\u043b\u044c\u043a\u043e \u0442\u0435\u0441\u0442\u043e\u0432, \u0438 \u0437\u0430\u0442\u0435\u043c \u043e\u0442\u0447\u0451\u0442 \u043c\u043e\u0436\u043d\u043e \u043e\u0442\u043f\u0440\u0430\u0432\u0438\u0442\u044c \u0432 Intel, \u0435\u0441\u043b\u0438 \u0432\u0441\u0435 \u0442\u0435\u0441\u0442\u044b \u043f\u0440\u043e\u0439\u0434\u0435\u043d\u044b \u0443\u0441\u043f\u0435\u0448\u043d\u043e.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b cmls102-prq-report-rev0.pdf<\/b> <\/p>\n<p>  \u041e\u0442\u0447\u0451\u0442 \u043e \u043c\u0435\u0442\u043e\u0434\u0438\u043a\u0430\u0445 \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c \u0438 \u043f\u0440\u043e\u0433\u043d\u043e\u0437\u0438\u0440\u0443\u0435\u043c\u044b\u0445 \u043f\u0440\u043e\u0446\u0435\u043d\u0442\u0430\u0445 \u043e\u0442\u043a\u0430\u0437\u0430 \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Core \u0438 Xeon \u043e\u0442 \u0430\u043f\u0440\u0435\u043b\u044f 2020 \u0433\u043e\u0434\u0430. \u0418\u0437 \u044d\u0442\u043e\u0433\u043e \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430 \u043c\u043e\u0436\u043d\u043e \u0443\u0437\u043d\u0430\u0442\u044c, \u0447\u0435\u0440\u0435\u0437 \u0447\u0442\u043e \u043f\u0440\u043e\u0445\u043e\u0434\u044f\u0442 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u044b \u043f\u0435\u0440\u0435\u0434 \u043f\u043e\u043f\u0430\u0434\u0430\u043d\u0438\u0435\u043c \u0432 \u043d\u0430\u0448\u0438 \u043a\u043e\u043c\u043f\u044c\u044e\u0442\u0435\u0440\u044b:<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/3b\/fe\/fc\/3bfefcsfz_cmh823qtklcicsqyy.png\"><br \/>  <i>Infant Mortality Test \u2014 \u044d\u0442\u043e \u043f\u0435\u0440\u0432\u043e\u0435 \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u043c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c \u043f\u043e\u0441\u043b\u0435 \u043a\u043e\u0440\u043f\u0443\u0441\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u0432 \u0440\u0430\u0431\u043e\u0442\u0435 \u043f\u0440\u0438 \u043f\u043e\u0432\u044b\u0448\u0435\u043d\u043d\u043e\u0439 \u0442\u0435\u043c\u043f\u0435\u0440\u0430\u0442\u0443\u0440\u0435. \u041d\u0430\u0437\u0432\u0430\u043d\u0438\u0435 <a href=\"https:\/\/ru.wikipedia.org\/wiki\/%D0%9C%D0%BB%D0%B0%D0%B4%D0%B5%D0%BD%D1%87%D0%B5%D1%81%D0%BA%D0%B0%D1%8F_%D1%81%D0%BC%D0%B5%D1%80%D1%82%D0%BD%D0%BE%D1%81%D1%82%D1%8C\" rel=\"nofollow\">\u043d\u0435 \u0441\u0430\u043c\u043e\u0435 \u043c\u043e\u0440\u0430\u043b\u044c\u043d\u043e \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0435<\/a>, \u043d\u043e \u0447\u0435\u0433\u043e \u0436\u0434\u0430\u0442\u044c \u043e\u0442 \u0430\u0432\u0442\u043e\u0440\u043e\u0432 master\/slave?<\/i><\/p>\n<p>  \u041f\u043e\u0434\u0440\u043e\u0431\u043d\u0435\u0435 \u043e \u043f\u0440\u043e\u0446\u0435\u0434\u0443\u0440\u0435 \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c \u043c\u043e\u0436\u043d\u043e \u0431\u0443\u0434\u0435\u0442 \u0443\u0437\u043d\u0430\u0442\u044c \u0438\u0437 \u0444\u0438\u043b\u044c\u043c\u0430, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u044f \u0441\u043a\u043e\u0440\u043e \u043e\u043f\u0443\u0431\u043b\u0438\u043a\u0443\u044e.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b prq-prq-customer-report-skl-2-2-lga-dt-rev0.pdf<\/b> <\/p>\n<p>  \u0422\u0430\u043a\u043e\u0439 \u0436\u0435 \u043e\u0442\u0447\u0451\u0442 \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Pentium \u0438 i3 \u043e\u0442 2015 \u0433\u043e\u0434\u0430.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b c-state-test-case-intel-soc-watch-bkc-626226-rev0-5.pdf<\/b><\/p>\n<p>  \u0412\u0430\u0440\u0438\u0430\u043d\u0442\u044b \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u0440\u0435\u0436\u0438\u043c\u043e\u0432 c-state \u0438 p-state \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 (\u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u043e \u043f\u043e\u0442\u0440\u0435\u0431\u043b\u044f\u0435\u043c\u043e\u0439 \u043c\u043e\u0449\u043d\u043e\u0441\u0442\u0438 \u0438 \u043f\u043e \u0447\u0430\u0441\u0442\u043e\u0442\u0435 \u0441 \u043d\u0430\u043f\u0440\u044f\u0436\u0435\u043d\u0438\u0435\u043c). \u041f\u043e\u0448\u0430\u0433\u043e\u0432\u0430\u044f \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043f\u043e \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430\u043c BIOS \u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u044e \u0441\u043f\u0435\u0446\u0438\u0430\u043b\u044c\u043d\u043e\u0439 \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u0434\u043b\u044f \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b FMX.Data.Flows.Training.v1.0_2020-02-11_AVM.pdf<\/b><\/p>\n<p>  \u041a\u0430\u043a\u0430\u044f-\u0442\u043e \u043f\u043b\u043e\u0445\u043e \u0441\u0432\u0451\u0440\u0441\u0442\u0430\u043d\u043d\u0430\u044f \u043f\u0440\u0435\u0437\u0435\u043d\u0442\u0430\u0446\u0438\u044f \u043d\u0430 \u0442\u0435\u043c\u0443 \u0441\u0435\u0442\u0435\u0432\u043e\u0439 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438. \u041d\u0430\u043f\u043e\u043b\u043e\u0432\u0438\u043d\u0443 \u0441\u043e\u0441\u0442\u043e\u0438\u0442 \u0438\u0437 \u0430\u0431\u0431\u0440\u0435\u0432\u0438\u0430\u0442\u0443\u0440, \u0442\u0430\u043a \u0447\u0442\u043e \u044f \u043d\u0435 \u043f\u043e\u043d\u044f\u043b, \u043e \u0447\u0451\u043c \u043e\u043d\u0430 \u043a\u043e\u043d\u043a\u0440\u0435\u0442\u043d\u043e. 2020 \u0433\u043e\u0434.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b glk_platform_intel&reg;_txe_4.0.25.1324_mr.pdf<\/b> <\/p>\n<p>  \u041d\u0435\u043a\u043e\u0442\u043e\u0440\u043e\u0435 (\u043d\u0435\u043f\u043e\u043b\u043d\u043e\u0435) \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u0435 \u043d\u0430\u0431\u043e\u0440\u0430 \u0443\u0442\u0438\u043b\u0438\u0442 \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438 \u0438 \u043f\u043e\u0434\u043f\u0438\u0441\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u0440\u043e\u0448\u0438\u0432\u043e\u043a \u043c\u043e\u0434\u0443\u043b\u044f <a href=\"https:\/\/www.intel.ru\/content\/www\/ru\/ru\/support\/articles\/000025873\/technologies.html\" rel=\"nofollow\">Intel TXE<\/a>. \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440 \u0435\u0441\u0442\u044c \u0442\u0430\u0431\u043b\u0438\u0446\u0430 \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u043e\u0432 TXE \u0441 \u0438\u0445 \u0440\u0430\u0437\u043c\u0435\u0440\u0430\u043c\u0438 \u0438 \u0440\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0430\u0446\u0438\u0438 \u043f\u043e \u0432\u044b\u0431\u043e\u0440\u0443 \u0451\u043c\u043a\u043e\u0441\u0442\u0438 \u043c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c\u044b flash \u0434\u043b\u044f BIOS. 2020 \u0433\u043e\u0434.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b how to obtain intel system debugger nda.pdf <\/b><\/p>\n<p>  \u0421\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0440\u0443\u043a\u043e\u0432\u043e\u0434\u0441\u0442\u0432\u043e \u043f\u043e \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044e \u043e\u0442\u043b\u0430\u0434\u043e\u0447\u043d\u043e\u0433\u043e \u043a\u043e\u043c\u043f\u043b\u0435\u043a\u0442\u0430 \u0434\u043b\u044f \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432 \u0441\u0438\u0441\u0442\u0435\u043c \u0441 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430\u043c\u0438 Intel. \u0411\u0443\u043a\u0432\u0430\u043b\u044c\u043d\u043e \u043a\u0430\u043a \u0438 \u043a\u0430\u043a\u0438\u0435 \u043f\u043e\u043b\u044f \u0437\u0430\u043f\u043e\u043b\u043d\u044f\u0442\u044c \u0432 \u0444\u043e\u0440\u043c\u0435 \u043d\u0430 \u0441\u0430\u0439\u0442\u0435. 2020 \u0433\u043e\u0434.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b qts-qpp-5v1-17-1.pdf<\/b><\/p>\n<p>  \u0418\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043f\u043e Quartus Pro \u2014 \u0441\u043e\u0444\u0442\u0443 \u0434\u043b\u044f \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u043e\u0434 FPGA (\u0434\u043e \u043f\u043e\u043a\u0443\u043f\u043a\u0438 \u0438\u043d\u0442\u0435\u043b\u043e\u043c \u0431\u044b\u043b \u0438\u0437\u0432\u0435\u0441\u0442\u0435\u043d, \u043a\u0430\u043a Altera Quartus).<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b SeamlessUpdate_CapsuleGeneration_UserGuide_v0.5.2.pdf<\/b><\/p>\n<p>  \u0418\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u0434\u043b\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u0439 \u043e\u0431\u043e\u0440\u0443\u0434\u043e\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0441\u0431\u043e\u0440\u043a\u0435 \u043f\u0430\u0442\u0447\u0435\u0439 \u0434\u043b\u044f \u043e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u044f \u0431\u0438\u043e\u0441\u0430, Intel ME, \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u0434\u0430 \u0438 \u0442\u043e\u043c\u0443 \u043f\u043e\u0434\u043e\u0431\u043d\u043e\u0433\u043e.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b SeamlessUpdate_CapsuleGenerationEnv_v0.5.2.zip<\/b><\/p>\n<p>  \u0421\u0430\u043c \u043d\u0430\u0431\u043e\u0440 \u0443\u0442\u0438\u043b\u0438\u0442 \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b simicsmodellibrary_eaglestream_rn_v0_6_00.pdf<\/b><\/p>\n<p>  \u041a\u0440\u0430\u0442\u043a\u0430\u044f \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043f\u043e \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043a\u0435 \u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u044e \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u0434\u043b\u044f \u044d\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u0441\u0438\u0441\u0442\u0435\u043c\u044b. \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442\u0441\u044f \u0432 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438 BIOS \u0434\u043b\u044f \u0435\u0449\u0451 \u043d\u0435 \u0432\u044b\u0448\u0435\u0434\u0448\u0438\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432.<\/p>\n<p>  \u041f\u0430\u043f\u043a\u0430 <b>Intel ME<\/b> c\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0443\u0442\u0438\u043b\u0438\u0442\u044b, \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044e \u0438 \u0431\u0438\u043d\u0430\u0440\u043d\u0438\u043a\u0438 \u0434\u043b\u044f <a href=\"https:\/\/www.intel.ru\/content\/www\/ru\/ru\/support\/articles\/000008927\/software\/chipset-software.html\" rel=\"nofollow\">Intel ME<\/a>. \u0410\u0431\u0441\u043e\u043b\u044e\u0442\u043d\u043e \u043d\u0438\u0447\u0435\u0433\u043e \u043f\u043e\u043b\u0435\u0437\u043d\u043e\u0433\u043e \u043d\u0435 \u043e\u0431\u043d\u0430\u0440\u0443\u0436\u0435\u043d\u043e. \u0415\u0441\u0442\u044c \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a \u043f\u0440\u0438\u043c\u0435\u0440\u0430 \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u0434\u043b\u044f \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438, \u043d\u043e \u043e\u043d \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442 \u0441\u0438\u0448\u043d\u0443\u044e \u0431\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a\u0443 FWUpdateLib.lib, \u043a\u043e\u0442\u043e\u0440\u0430\u044f \u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442 \u0432\u0441\u044e \u0438\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u0443\u044e \u0440\u0430\u0431\u043e\u0442\u0443. \u0412 \u043a\u043e\u0434\u0435 \u0432\u043e \u0432\u0441\u0435\u0445 \u0444\u0443\u043d\u043a\u0446\u0438\u044f\u0445 \u0441\u0432\u043e\u0435\u043e\u0431\u0440\u0430\u0437\u043d\u044b\u0439 \u0432\u044b\u0445\u043e\u0434 \u0438\u0437 \u0444\u0443\u043d\u043a\u0446\u0438\u0439 \u043f\u043e goto (\u043c\u0435\u0442\u043a\u0430 End \u0432\u043e \u0432\u0441\u0435\u0445 \u0444\u0443\u043d\u043a\u0446\u0438\u044f\u0445 \u043e\u0434\u0438\u043d\u0430\u043a\u043e\u0432\u0430\u044f), \u0431\u043e\u043b\u044c\u0448\u0435 \u043d\u0438\u0447\u0435\u0433\u043e \u043f\u0440\u0438\u043c\u0435\u0447\u0430\u0442\u0435\u043b\u044c\u043d\u043e\u0433\u043e.<\/p>\n<div class=\"spoiler\" role=\"button\" tabindex=\"0\">                         <b class=\"spoiler_title\">\u041f\u043e\u0441\u043c\u043e\u0442\u0440\u0435\u0442\u044c \u043b\u0438\u0441\u0442\u0438\u043d\u0433<\/b>                         <\/p>\n<div class=\"spoiler_text\">\n<pre><code class=\"cpp\">static UINT32 checkUpdateType(IN  const char *fileName, IN  UINT32 *updateType) {     UINT32 status;     UINT16 flashMajor = 0;     UINT16 flashMinor = 0;     UINT16 flashHotfix = 0;     UINT16 flashBuild = 0;     UINT16 fileMajor = 0;     UINT16 fileMinor = 0;     UINT16 fileHotfix = 0;     UINT16 fileBuild = 0;     INT32  comparedVersion = 0;      if (fileName == NULL || updateType == NULL)     {         status = INTERNAL_ERROR;         goto End;     }      status = FwuPartitionVersionFromFlash(FPT_PARTITION_NAME_FTPR, &amp;flashMajor, &amp;flashMinor, &amp;flashHotfix, &amp;flashBuild);     if (status != SUCCESS)     {         goto End;     }      status = FwuPartitionVersionFromFile(fileName, FPT_PARTITION_NAME_FTPR, &amp;fileMajor, &amp;fileMinor, &amp;fileHotfix, &amp;fileBuild);     if (status != SUCCESS)     {         goto End;     }      comparedVersion = versionCompare(fileMajor, fileMinor, fileHotfix, fileBuild,                                      flashMajor, flashMinor, flashHotfix, flashBuild);      if (comparedVersion &lt; 0)     {         *updateType = DOWNGRADE;     }     else if (comparedVersion &gt; 0)     {         *updateType = UPGRADE;     }     else     {         *updateType = SAME_VERSION;     }  End:     return status; }<\/code><\/pre>\n<p>  <\/div>\n<\/p><\/div>\n<p>  <b>\u041f\u0430\u043f\u043a\u0430 Intel Restricted Secret<\/b><\/p>\n<p>  \u0410 \u0432\u043e\u0442 \u0442\u0443\u0442 \u0443\u0436\u0435 \u0435\u0441\u0442\u044c \u043a\u043e\u0435-\u0447\u0442\u043e \u0438\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u043e\u0435. \u0412 \u043f\u0430\u043f\u043a\u0435 KabylakePlatform_3_7_9\\KabylakePlatSamplePkg \u043b\u0435\u0436\u0438\u0442 \u043f\u0440\u0438\u043c\u0435\u0440 BIOS \u0434\u043b\u044f \u043f\u043b\u0430\u0442\u0444\u043e\u0440\u043c\u044b Kaby Lake (\u044d\u0442\u043e 7-\u043e\u0435 \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u0435 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Core, \u0432\u044b\u0448\u043b\u0438 \u0432 2017 \u0433\u043e\u0434\u0443). \u0421\u043e\u0431\u0438\u0440\u0430\u0442\u044c \u044f \u0435\u0433\u043e \u043d\u0435 \u043f\u0440\u043e\u0431\u043e\u0432\u0430\u043b, \u043d\u043e \u043f\u043e \u0432\u0438\u0434\u0443 \u0442\u0443\u0442 \u0435\u0441\u0442\u044c \u0432\u0441\u0451 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e\u0435.<\/p>\n<div style=\"text-align:center;\"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/nm\/se\/j0\/nmsej0yrglq-zrczzwx4j0fv2xq.png\"><\/div>\n<p>  \u0412 \u043f\u0430\u043f\u043a\u0435 Features \u043b\u0435\u0436\u0430\u0442 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u0434\u0440\u0430\u0439\u0432\u0435\u0440\u043e\u0432 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432. \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440 \u0434\u043b\u044f SATA, \u0441 \u0432\u0438\u0434\u0443, \u0432\u043f\u043e\u043b\u043d\u0435 \u0440\u0430\u0431\u043e\u0447\u0438\u0439 \u043a\u043e\u0434 \u043f\u043e\u0438\u0441\u043a\u0430 \u0438 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430 \u043d\u0430 PCIe.<\/p>\n<div style=\"text-align:center;\"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/__\/pu\/v8\/__puv89vy35vcf9gxs3q2hfsbio.png\"><\/div>\n<p>  <\/p>\n<div class=\"spoiler\" role=\"button\" tabindex=\"0\">                         <b class=\"spoiler_title\">\u041b\u0438\u0441\u0442\u0438\u043d\u0433<\/b>                         <\/p>\n<div class=\"spoiler_text\">\n<pre><code class=\"cpp\">\/**   This routine is called right after the .Supported() is called and returns   EFI_SUCCESS. Notes: The supported protocols are checked but the Protocols   are closed.    @param[in] This                 A pointer points to the Binding Protocol instance   @param[in] Controller           The handle of controller to be tested. Parameter                                   passed by the caller   @param[in] RemainingDevicePath  A pointer to the device path. Should be ignored by                                   device driver    @retval EFI_SUCCESS             The device is started   @retval Other values            Something error happened **\/ EFI_STATUS EFIAPI SataControllerStart (   IN EFI_DRIVER_BINDING_PROTOCOL    *This,   IN EFI_HANDLE                     Controller,   IN EFI_DEVICE_PATH_PROTOCOL       *RemainingDevicePath   ) {   EFI_STATUS                        Status;   EFI_IDE_CONTROLLER_INIT_PROTOCOL  *IdeInit;   EFI_PCI_IO_PROTOCOL               *PciIo;   UINT8                             NumberOfPort;   UINT64                            CommandVal;    DEBUG ((DEBUG_INFO, &quot;SataControllerStart() Start\\n&quot;));    \/\/\/   \/\/\/ Now test and open the EfiPciIoProtocol   \/\/\/   Status = gBS-&gt;OpenProtocol (                   Controller,                   &amp;gEfiPciIoProtocolGuid,                   (VOID **) &amp;PciIo,                   This-&gt;DriverBindingHandle,                   Controller,                   EFI_OPEN_PROTOCOL_BY_DRIVER                   );   \/\/\/   \/\/\/ Status == 0 - A normal execution flow, SUCCESS and the program proceeds.   \/\/\/ Status == ALREADY_STARTED - A non-zero Status code returned. It indicates   \/\/\/           that the protocol has been opened and should be treated as a   \/\/\/           normal condition and the program proceeds. The Protocol will not   \/\/\/           opened 'again' by this call.   \/\/\/ Status != ALREADY_STARTED - Error status, terminate program execution   \/\/\/   if (EFI_ERROR (Status)) {     \/\/\/     \/\/\/ EFI_ALREADY_STARTED is also an error     \/\/\/     return Status;   }    \/\/\/   \/\/\/ Get device capabilities   \/\/\/   Status = PciIo-&gt;Attributes (                     PciIo,                     EfiPciIoAttributeOperationSupported,                     0,                     &amp;CommandVal                     );   ASSERT_EFI_ERROR (Status);    \/\/\/   \/\/\/ Enable Command Register   \/\/\/   Status = PciIo-&gt;Attributes (                     PciIo,                     EfiPciIoAttributeOperationEnable,                     CommandVal &amp; EFI_PCI_DEVICE_ENABLE,                     NULL                     );   ASSERT_EFI_ERROR (Status);    \/\/\/   \/\/\/ Get Number of Ports   \/\/\/   PciIo-&gt;Mem.Read (                PciIo,                EfiPciIoWidthUint8,                EFI_AHCI_BAR_INDEX,                (UINT64) R_AHCI_CAPABILITY,                1,                &amp; NumberOfPort                );   NumberOfPort = (NumberOfPort &amp; 0x1F) + 1;    IdeInit = AllocatePool (sizeof (EFI_IDE_CONTROLLER_INIT_PROTOCOL));   if (IdeInit == NULL) {     return EFI_OUT_OF_RESOURCES;   }   IdeInit-&gt;GetChannelInfo = IdeInitGetChannelInfo;   IdeInit-&gt;NotifyPhase    = IdeInitNotifyPhase;   IdeInit-&gt;SubmitData     = IdeInitSubmitData;   IdeInit-&gt;DisqualifyMode = IdeInitDisqualifyMode;   IdeInit-&gt;CalculateMode  = IdeInitCalculateMode;   IdeInit-&gt;SetTiming      = IdeInitSetTiming;   IdeInit-&gt;EnumAll        = SATA_ENUMER_ALL;   IdeInit-&gt;ChannelCount   = NumberOfPort;    \/\/\/   \/\/\/ Install IDE_CONTROLLER_INIT protocol &amp; private data to this instance   \/\/\/   Status = gBS-&gt;InstallMultipleProtocolInterfaces (                   &amp;Controller,                   &amp;gEfiIdeControllerInitProtocolGuid,                   IdeInit,                   NULL                   );    \/\/\/   \/\/\/ Close protocols opened by SATA controller driver   \/\/\/   gBS-&gt;CloseProtocol (         Controller,         &amp;gEfiPciIoProtocolGuid,         This-&gt;DriverBindingHandle,         Controller         );    DEBUG ((DEBUG_INFO, &quot;SataControllerStart() End\\n&quot;));    return Status; }<\/code><\/pre>\n<p>  <\/div>\n<\/p><\/div>\n<p>  \u0422\u0430\u043a\u0436\u0435 \u0432 \u043f\u0430\u043f\u043a\u0435 Intel Restricted Secret \u043b\u0435\u0436\u0430\u0442 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438:<\/p>\n<ul>\n<li>\u041a\u043e\u0434\u043e\u0432 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Kaby Lake \u0441 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u0435\u0439;<\/li>\n<li>\u0427\u0442\u043e-\u0442\u043e \u043f\u043e\u0434 \u043d\u0430\u0437\u0432\u0430\u043d\u0438\u0435\u043c Client Silicon API package;<\/li>\n<li>\u0418\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043f\u043e \u0438\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u0438 \u044d\u0442\u043e\u0433\u043e \u0432\u0441\u0435\u0433\u043e \u0432 \u0441\u0432\u043e\u0439 BIOS (\u0434\u043b\u044f \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432 \u043e\u0431\u043e\u0440\u0443\u0434\u043e\u0432\u0430\u043d\u0438\u044f).<\/li>\n<\/ul>\n<p>  <b>\u0424\u0430\u0439\u043b 482486-crystal-forest-gladden-stargo-schematic-design-files-rev2-1.zip<\/b><\/p>\n<p>  \u0411\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a\u0438 <a href=\"https:\/\/www.cadence.com\/en_US\/home.html\" rel=\"nofollow\">Cadence<\/a> \u0434\u043b\u044f \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u043e\u0434 \u0438\u043d\u0442\u0435\u043b\u043e\u0432\u0441\u043a\u0443\u044e \u043f\u043b\u0430\u0442\u0444\u043e\u0440\u043c\u0443 \u0441 \u043a\u043e\u0434\u043e\u0432\u044b\u043c \u043d\u0430\u0437\u0432\u0430\u043d\u0438\u0435\u043c <a href=\"https:\/\/www.intel.com\/content\/www\/us\/en\/design\/products-and-solutions\/processors-and-chipsets\/crystal-forest\/technical-library.html\" rel=\"nofollow\">Crystal Forest<\/a>. \u0421\u0430\u043c\u0438\u0445 \u043f\u0440\u043e\u0435\u043a\u0442\u043e\u0432 \u0441 \u0442\u0440\u0430\u0441\u0441\u0438\u0440\u043e\u0432\u043a\u043e\u0439 \u043f\u043b\u0430\u0442 \u043d\u0435\u0442.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/cl\/qr\/zc\/clqrzc95xbdcdggttmpilec25j8.png\"><br \/>  <i>\u041b\u043e\u0433\u0438\u043a\u0430<\/i><\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/mr\/29\/kj\/mr29kj2djsobeupwkbcejip6xta.png\"><br \/>  <i>EEPROM<\/i><\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/ra\/cl\/gl\/raclglmictj4r5ixhspz-jrdhxg.png\"><br \/>  <i>\u0414\u0438\u0441\u043a\u0440\u0435\u0442\u043d\u044b\u0435 \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u044b<\/i><\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/py\/d7\/1p\/pyd71p_fkyujixcn_x0tgbdzwdg.png\"><br \/>  <i>\u0420\u0430\u0437\u044a\u0451\u043c\u044b<\/i><\/p>\n<p>  \u041e\u0431\u044b\u0447\u043d\u044b\u0439 \u043d\u0430\u0431\u043e\u0440 \u0431\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a. \u0421\u043a\u043e\u0440\u0435\u0435 \u0432\u0441\u0435\u0433\u043e, \u0438\u0437 \u043f\u0430\u043a\u0435\u0442\u0430 \u043f\u043e\u0441\u0442\u0430\u0432\u043a\u0438 Cadence. \u0421\u0430\u043c\u0438 \u0444\u0430\u0439\u043b\u044b \u0434\u0430\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u044b 2012 \u0433\u043e\u0434\u043e\u043c.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 555146-kipsbay2-archive.zip<\/b><\/p>\n<p>  \u0422\u043e \u0436\u0435 \u0441\u0430\u043c\u043e\u0435 \u0434\u043b\u044f arduino-\u0441\u043e\u0432\u043c\u0435\u0441\u0442\u0438\u043c\u044b\u0445 \u043f\u043b\u0430\u0442 <a href=\"https:\/\/www.intel.ru\/content\/www\/ru\/ru\/support\/articles\/000005912\/boards-and-kits\/intel-galileo-boards.html\" rel=\"nofollow\">Intel Galileo<\/a>. \u0422\u043e\u0436\u0435 \u0431\u0435\u0437 \u0444\u0430\u0439\u043b\u043e\u0432 \u0442\u0440\u0430\u0441\u0441\u0438\u0440\u043e\u0432\u043a\u0438.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 607872-tgl-up3-up4-pdg-schchk-rev1-2.zip<\/b><\/p>\n<p>  \u041e\u0447\u0435\u043d\u044c \u043f\u043e\u0434\u0440\u043e\u0431\u043d\u0430\u044f \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043f\u043e \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c \u0438 \u0442\u0440\u0430\u0441\u0441\u0438\u0440\u043e\u0432\u043a\u0435 \u043f\u043b\u0430\u0442 \u0434\u043b\u044f \u0435\u0449\u0451 \u043d\u0435 \u0432\u044b\u0448\u0435\u0434\u0448\u0435\u0433\u043e 11-\u0433\u043e \u043f\u043e\u043a\u043e\u043b\u0435\u043d\u0438\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Core \u043f\u043e\u0434 \u043a\u043e\u0434\u043e\u0432\u044b\u043c \u043d\u0430\u0437\u0432\u0430\u043d\u0438\u0435\u043c Tiger Lake.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/vf\/tu\/uc\/vftuucig654wmmngcpbfwlkvj48.png\"><br \/>  <i>\u041c\u043d\u043e\u0433\u043e \u0442\u0430\u043a\u0438\u0445 \u043d\u0430\u0433\u043b\u044f\u0434\u043d\u044b\u0445 \u0438\u043b\u043b\u044e\u0441\u0442\u0440\u0430\u0446\u0438\u0439 \u0441 \u043f\u043e\u044f\u0441\u043d\u0435\u043d\u0438\u044f\u043c\u0438<\/i><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 615188-wilson-city-schematic-walkthrough-bmc.zip<\/b><\/p>\n<p>  \u0412\u0438\u0434\u0435\u043e\u043f\u0440\u0435\u0437\u0435\u043d\u0442\u0430\u0446\u0438\u044f \u0441 \u043f\u043e\u044f\u0441\u043d\u0435\u043d\u0438\u044f\u043c\u0438 \u043a \u0441\u0445\u0435\u043c\u0435 \u043a\u0430\u043a\u043e\u0433\u043e-\u0442\u043e \u0447\u0438\u043f\u0441\u0435\u0442\u0430 \u0441 \u043a\u043e\u0434\u043e\u0432\u044b\u043c \u0438\u043c\u0435\u043d\u0435\u043c Wilson City. \u041e\u0437\u0432\u0443\u0447\u0435\u043d\u043e \u0441\u0438\u043d\u0442\u0435\u0437\u0430\u0442\u043e\u0440\u043e\u043c \u0433\u043e\u043b\u043e\u0441\u0430.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/p3\/vz\/z5\/p3vzz5fg2r0fj0od3fegxzspmhy.png\"><br \/>  <i>\u041a\u0430\u0434\u0440 \u0438\u0437 \u044d\u0442\u043e\u0433\u043e \u0437\u0430\u0445\u0432\u0430\u0442\u044b\u0432\u0430\u044e\u0449\u0435\u0433\u043e \u0432\u0438\u0434\u0435\u043e<\/i><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 615704-cml-s-udimm-3200-cmp-h-rvp-tdk-rev0p7.zip<\/b><\/p>\n<p>  \u042d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u044b \u0438 \u043f\u0440\u043e\u0435\u043a\u0442 Cadence \u0441 \u0442\u0440\u0430\u0441\u0441\u0438\u0440\u043e\u0432\u043a\u043e\u0439 \u0442\u0438\u043f\u043e\u0432\u043e\u0439 \u043f\u043b\u0430\u0442\u044b \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 <a href=\"https:\/\/www.intel.ru\/content\/www\/ru\/ru\/design\/products-and-solutions\/processors-and-chipsets\/comet-lake-s\/overview.html?grouping=EMT_Content%20Type&amp;sort=title:asc\" rel=\"nofollow\">Comet Lake S<\/a> \u0441 UDIMM \u043f\u0430\u043c\u044f\u0442\u044c\u044e.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/bo\/he\/ag\/boheagcpen_fyvsob5llm8lx8ke.png\"><br \/>  <i>\u041a\u0440\u0430\u0441\u0438\u0432\u044b\u0435 10 \u0441\u043b\u043e\u0451\u0432<\/i><\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/vn\/am\/dh\/vnamdhc_v31uqos50l8iylna1ha.png\"><br \/>  <i>\u041f\u0440\u0435\u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c \u0443\u0440\u043e\u0432\u043d\u0435\u0439 \u0434\u043b\u044f HDMI<\/i><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 618525-tigerlake-up3-tsn-aic.zip<\/b><\/p>\n<p>  \u041f\u043e\u0445\u043e\u0436\u0435 \u043d\u0430 \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u0443 \u0438 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u0435 \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0439 \u043f\u043b\u0430\u0442\u044b \u0441 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0435\u0439 \u0434\u043b\u044f \u0435\u0449\u0451 \u043d\u0435 \u0432\u044b\u0448\u0435\u0434\u0448\u0435\u0433\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 Tiger Lake.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/bw\/5f\/lo\/bw5flobwzbljracjril5rlg-oye.png\"><br \/>  <i>PCIe \u043f\u043b\u0430\u0442\u0430 \u0441 \u0434\u0432\u0443\u043c\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430\u043c\u0438 Ethernet \u0438 PHY \u0434\u043b\u044f \u043d\u0438\u0445<\/i><\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/c7\/u2\/f7\/c7u2f7itu-szepzcxgy3oxsmjem.png\"><br \/>  <i>\u041f\u043e\u044f\u0441\u043d\u0435\u043d\u0438\u044f \u043a \u0438\u0437\u043c\u0435\u043d\u0435\u043d\u0438\u044f\u043c \u0432 \u044d\u0442\u043e\u0439 \u0440\u0435\u0432\u0438\u0437\u0438\u0438<\/i><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b 618730-ehl-mcl-hierarchical-schematic-lp4x-0-7.zip<\/b><\/p>\n<p>  \u0411\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a\u0430 \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u043e\u0432 Cadence \u0434\u043b\u044f \u0435\u0449\u0451 \u043d\u0435 \u0432\u044b\u0448\u0435\u0434\u0448\u0438\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Elkhart Lake (\u043b\u0438\u043d\u0435\u0439\u043a\u0430 Intel Atom). \u0411\u0435\u0437 \u0444\u0430\u0439\u043b\u043e\u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0430, \u043d\u043e \u0435\u0441\u0442\u044c \u043f\u043e\u043b\u043d\u0430\u044f \u044d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u0430 \u0434\u043b\u044f \u0432\u0441\u0435\u0439 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0438 \u0438 \u043f\u0438\u0442\u0430\u043d\u0438\u044f. \u0423\u0436\u0435 \u043c\u043e\u0436\u043d\u043e \u043f\u0440\u0438\u043a\u0438\u043d\u0443\u0442\u044c, \u043a\u0430\u043a\u0438\u0435 \u043f\u043e\u0440\u0442\u044b \u0431\u0443\u0434\u0443\u0442 \u043d\u0430 \u043f\u043b\u0430\u0442\u0435.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/ae\/f4\/rw\/aef4rwdanw8lgo7uqoqxjine7qw.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b adk_source.2.0.11.09.standalone.snowridge_transportip.tar.gz<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u0438 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u0434\u043b\u044f \u044d\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u0441\u0435\u0442\u0435\u0432\u043e\u0439 \u043f\u043e\u0434\u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0435\u0449\u0451 \u043d\u0435 \u0432\u044b\u0448\u0435\u0434\u0448\u0438\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 <a href=\"https:\/\/ark.intel.com\/content\/www\/us\/en\/ark\/products\/codename\/87586\/snow-ridge.html\" rel=\"nofollow\">Snowfish<\/a>. \u041a\u0430\u043a \u044f \u043f\u043e\u043d\u044f\u043b, \u043e\u043d\u0430 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0430\u0435\u0442\u0441\u044f \u043a \u044d\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0443 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Snowfish \u0438 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0441\u0435\u0442\u0435\u0432\u044b\u0435 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u0438.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b aml_cfl_s_kbl_skl-vbios_9.0.1062.zip<\/b><\/p>\n<p>  \u041a\u0430\u043a\u043e\u0439-\u0442\u043e \u0441\u043a\u0440\u0438\u043f\u0442 \u0434\u043b\u044f \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u0440\u0435\u0434\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f <a href=\"https:\/\/ru.wikipedia.org\/wiki\/Video_BIOS\" rel=\"nofollow\">VBIOS<\/a> \u0434\u043b\u044f OEM \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432. \u0412 \u0442\u0435\u043a\u0441\u0442\u043e\u0432\u043e\u043c \u0432\u0438\u0434\u0435 \u043e\u043f\u0438\u0441\u0430\u043d\u0430 \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u0430 \u0444\u0430\u0439\u043b\u0430 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438 VBIOS.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b apl-i_sic_1.1.1_v227_51_d20190502.zip<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u043a\u043e\u0434\u043e\u0432 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 <a href=\"https:\/\/ark.intel.com\/content\/www\/ru\/ru\/ark\/products\/codename\/80644\/apollo-lake.html\" rel=\"nofollow\">Apollo Lake<\/a> \u0438 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b core 10x00k 10x00kf v 1.0.5.zip<\/b><\/p>\n<p>  \u0421\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u0449\u0438\u043a \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u0441 \u043e\u0447\u0435\u043d\u044c \u043f\u0435\u0440\u0441\u043f\u0435\u043a\u0442\u0438\u0432\u043d\u044b\u043c \u043d\u0430\u0437\u0432\u0430\u043d\u0438\u0435\u043c:<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/sy\/ko\/ap\/sykoaplakl1fyr7ck5_jgl8bxje.png\"><\/p>\n<p>  \u0423 \u043c\u0435\u043d\u044f \u043d\u0435\u0442 \u0442\u0430\u043a\u043e\u0433\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430, \u0442\u0430\u043a \u0447\u0442\u043e \u043f\u0440\u043e\u0432\u0435\u0440\u0438\u0442\u044c \u043d\u0435 \u043f\u043e\u043b\u0443\u0447\u0438\u043b\u043e\u0441\u044c.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b elkhartlake_silicon_and_platformsamplecode_v1.0.0.zip<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u043a\u043e\u0434\u043e\u0432 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0442\u0435\u043f\u0435\u0440\u044c \u0443\u0436\u0435 \u0434\u043b\u044f Elkhart Lake, \u0441 \u0447\u0430\u0441\u0442\u044c\u044e \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u043e\u0432 \u0434\u043b\u044f BIOS \u0438 \u0444\u0430\u0439\u043b\u0430\u043c\u0438 Client Silicon. \u041f\u043e\u0434\u043e\u0437\u0440\u0435\u0432\u0430\u044e, \u0447\u0442\u043e \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043f\u0440\u0438\u043c\u0435\u0440 BIOS \u0434\u043b\u044f Kaby Lake, \u0447\u0442\u043e\u0431\u044b \u0441\u043e\u0431\u0440\u0430\u0442\u044c BIOS \u0434\u043b\u044f \u044d\u0442\u0438\u0445 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b intel&reg;pch chipset_init kit \u2014 tglpchlp_z0v5_a0v11.zip<\/b><\/p>\n<p>  \u041f\u0430\u0442\u0447 \u0434\u043b\u044f BIOS \u0432 \u0431\u0438\u043d\u0430\u0440\u043d\u043e\u043c \u0432\u0438\u0434\u0435 \u0438 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043a \u0443\u0442\u0438\u043b\u0438\u0442\u0435 \u0434\u043b\u044f \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043a\u0438 \u044d\u0442\u043e\u0433\u043e \u043f\u0430\u0442\u0447\u0430 \u0432 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0443. \u0421\u0430\u043c \u043f\u0430\u0442\u0447 \u0438\u0441\u043f\u0440\u0430\u0432\u043b\u044f\u0435\u0442 \u043a\u0430\u043a\u0438\u0435-\u0442\u043e \u043e\u0448\u0438\u0431\u043a\u0438 \u0432 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0447\u0438\u043f\u0441\u0435\u0442\u0430 \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Tiger Lake.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b intel&reg;powerandthermaldesignstudio_ext_2.1.1.zip<\/b><\/p>\n<p>  \u0417\u0430\u0433\u0430\u0434\u043e\u0447\u043d\u0430\u044f \u0443\u0442\u0438\u043b\u0438\u0442\u0430 Intel Power and Thermal Design Studio.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/aw\/li\/_l\/awli_l-b3mqpkn8ce4uc-3k3mla.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b\u044b KBL SST FDK training session 2.1.zip \u2014 KBL SST FDK training session 4.2.zip<\/b><\/p>\n<p>  \u0417\u0430\u043f\u0438\u0441\u044c \u0432\u0438\u0434\u0435\u043e\u0443\u0440\u043e\u043a\u043e\u0432 \u043f\u043e \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0435 \u0442\u043e \u043b\u0438 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438, \u0442\u043e \u043b\u0438 \u0434\u0440\u0430\u0439\u0432\u0435\u0440\u0430 \u0432 \u043a\u0430\u043a\u043e\u0439-\u0442\u043e \u0433\u0440\u0430\u0444\u0438\u0447\u0435\u0441\u043a\u043e\u0439 \u0443\u0442\u0438\u043b\u0438\u0442\u0435. \u0417\u0430 \u043a\u0430\u0434\u0440\u043e\u043c \u0441\u043b\u044b\u0448\u0435\u043d \u0433\u043e\u043b\u043e\u0441 \u0438\u043d\u0434\u0443\u0441\u0430 \u0441 \u043f\u043b\u043e\u0445\u0438\u043c \u043f\u0440\u043e\u0438\u0437\u043d\u043e\u0448\u0435\u043d\u0438\u0435\u043c.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b main_pld_adr_engineering_release_ww19.zip<\/b><\/p>\n<p>  <a href=\"https:\/\/ru.wikipedia.org\/wiki\/Verilog\" rel=\"nofollow\">Verilog<\/a>-\u043a\u043e\u0434\u044b \u0434\u043b\u044f \u0443\u0436\u0435 \u0443\u043f\u043e\u043c\u044f\u043d\u0443\u0442\u043e\u0433\u043e \u0447\u0438\u043f\u0441\u0435\u0442\u0430 Wilson City. \u0412\u0438\u0434\u0438\u043c\u043e, \u0434\u043b\u044f \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u0432 <a href=\"https:\/\/ru.wikipedia.org\/wiki\/%D0%9F%D0%9B%D0%98%D0%A1\" rel=\"nofollow\">\u041f\u041b\u0418\u0421<\/a> \u0434\u043e \u0438\u0437\u0433\u043e\u0442\u043e\u0432\u043b\u0435\u043d\u0438\u044f \u0432 \u043a\u0440\u0435\u043c\u043d\u0438\u0438.<\/p>\n<div class=\"spoiler\" role=\"button\" tabindex=\"0\">                         <b class=\"spoiler_title\">\u041e\u0447\u0435\u043d\u044c \u0434\u043b\u0438\u043d\u043d\u044b\u0439 \u043b\u0438\u0441\u0442\u0438\u043d\u0433<\/b>                         <\/p>\n<div class=\"spoiler_text\">\n<pre><code class=\"vhdl\">\/\/ (C) 2020 Intel Corporation. All rights reserved. \/\/ Your use of Intel Corporation's design tools, logic functions and other  \/\/ software and tools, and its AMPP partner logic functions, and any output  \/\/ files from any of the foregoing (including device programming or simulation  \/\/ files), and any associated documentation or information are expressly subject  \/\/ to the terms and conditions of the Intel Program License Subscription  \/\/ Agreement, Intel FPGA IP License Agreement, or other applicable  \/\/ license agreement, including, without limitation, that your use is for the  \/\/ sole purpose of programming logic devices manufactured by Intel and sold by  \/\/ Intel or its authorized distributors.  Please refer to the applicable  \/\/ agreement for further details.   `timescale 1ns\/1ns `define dedicated_debug_logic  module Wilson_City_Main ( \/\/ Input CLK \tinput      \tiClk_2M, \tinput      \tiClk_50M, \toutput \t\to1mSCE,  \/\/GSX Interface with BMC \tinput      \tSGPIO_BMC_CLK, \tinput      \tSGPIO_BMC_DOUT, \toutput     \tSGPIO_BMC_DIN, \tinput      \tSGPIO_BMC_LD_N,  \/\/I2C Support \tinout      \tSMB_PLD_SDA, \/\/ SMB_PCH_PMBUS2_STBY_LVC3_SDA \tinput      \tSMB_PLD_SCL, \/\/ SMB_PCH_PMBUS2_STBY_LVC3_SCL \toutput     \tonSDAOE,  \/\/LED and 7-Seg Control Logic \toutput [7:0] LED_CONTROL, \toutput     \tFM_CPU1_DIMM_CH1_4_FAULT_LED_SEL, \toutput     \tFM_CPU1_DIMM_CH5_8_FAULT_LED_SEL, \toutput     \tFM_CPU2_DIMM_CH1_4_FAULT_LED_SEL, \toutput     \tFM_CPU2_DIMM_CH5_8_FAULT_LED_SEL, \toutput     \tFM_FAN_FAULT_LED_SEL_N, \toutput     \tFM_POST_7SEG1_SEL_N, \toutput     \tFM_POST_7SEG2_SEL_N, \toutput     \tFM_POSTLED_SEL,   \/\/CATERR DLY \toutput     \tFM_CPU_CATERR_DLY_LVT3_N, \tinput      \tFM_CPU_CATERR_PLD_LVT3_N, \/\/% No Input FF  \/\/ADR \tinput      \tFM_ADR_COMPLETE, \/\/% Input FF  \toutput     \tFM_ADR_COMPLETE_DLY, \toutput     \tFM_ADR_SMI_GPIO_N, \tinout     \tFM_ADR_TRIGGER_N,  \tinput      \tFM_PLD_PCH_DATA, \/\/% Input FF \tinput      \tFM_PS_PWROK_DLY_SEL, \/\/% Input FF \tinput      \tFM_DIS_PS_PWROK_DLY, \/\/% Input FF  \/\/ESPI Support \toutput     \tFM_PCH_ESPI_MUX_SEL,  \/\/System THROTTLE \tinput      \tFM_PMBUS_ALERT_B_EN, \/\/% Input FF \tinput      \tFM_THROTTLE_N, \/\/% Input FF \tinput      \tIRQ_SML1_PMBUS_PLD_ALERT_N, \/\/% Input FF  \toutput     \tFM_SYS_THROTTLE_LVC3_PLD, \/\/ Termtrip dly \tinput      \tFM_CPU1_THERMTRIP_LVT3_PLD_N, \/\/% Input FF \tinput      \tFM_CPU2_THERMTRIP_LVT3_PLD_N, \/\/% Input FF \tinput      \tFM_MEM_THERM_EVENT_CPU1_LVT3_N, \/\/% Input FF \tinput      \tFM_MEM_THERM_EVENT_CPU2_LVT3_N, \/\/% Input FF  \toutput     \tFM_THERMTRIP_DLY, \/\/MEMHOT \tinput      \tIRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N,\/\/% Input FF \tinput      \tIRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N,\/\/% Input FF \tinput      \tIRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N,\/\/% Input FF \tinput      \tIRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N,\/\/% Input FF  \toutput     \tFM_CPU1_MEMHOT_IN, \toutput     \tFM_CPU2_MEMHOT_IN, \/\/MEMTRIP \tinput      \tFM_CPU1_MEMTRIP_N, \/\/% Input FF \tinput      \tFM_CPU2_MEMTRIP_N, \/\/% Input FF \/\/PROCHOT \tinput      \tFM_PVCCIN_CPU1_PWR_IN_ALERT_N, \/\/% Input FF \tinput      \tFM_PVCCIN_CPU2_PWR_IN_ALERT_N, \/\/% Input FF \tinput      \tIRQ_PVCCIN_CPU1_VRHOT_LVC3_N,  \/\/% Input FF \tinput      \tIRQ_PVCCIN_CPU2_VRHOT_LVC3_N,  \/\/% Input FF  \toutput     \tFM_CPU1_PROCHOT_LVC3_N, \toutput     \tFM_CPU2_PROCHOT_LVC3_N,   \/\/PERST &amp; RST \tinput      \tFM_RST_PERST_BIT0, \/\/% No-Input FF \tinput      \tFM_RST_PERST_BIT1, \/\/% No-Input FF \tinput      \tFM_RST_PERST_BIT2, \/\/% No-Input FF  \toutput     \tRST_PCIE_PERST0_N, \toutput     \tRST_PCIE_PERST1_N, \toutput     \tRST_PCIE_PERST2_N,  \toutput     \tRST_CPU1_LVC3_N, \toutput     \tRST_CPU2_LVC3_N,  \toutput     \tRST_PLTRST_B_N,\/\/RST_PLTRST_PLD_B_N \tinput      \tRST_PLTRST_N, \/\/RST_PLTRST_PLD_N \/\/% Input FF  \/\/FIVR \tinput      \tFM_CPU1_FIVR_FAULT_LVT3, \/\/FM_CPU1_FIVR_FAULT_LVT3_PLD  \/\/% Input FF \tinput      \tFM_CPU2_FIVR_FAULT_LVT3, \/\/FM_CPU2_FIVR_FAULT_LVT3_PLD  \/\/% Input FF  \/\/CPU Misc \tinput      \tFM_CPU1_PKGID0, \/\/% No-Input FF \tinput      \tFM_CPU1_PKGID1, \/\/% No-Input FF \tinput      \tFM_CPU1_PKGID2, \/\/% No-Input FF  \tinput      \tFM_CPU1_PROC_ID0, \/\/% No-Input FF \tinput      \tFM_CPU1_PROC_ID1, \/\/% No-Input FF  \tinput      \tFM_CPU1_INTR_PRSNT,  \/\/% No-Input FF \tinput      \tFM_CPU1_SKTOCC_LVT3_N, \/\/FM_CPU1_SKTOCC_LVT3_PLD_N \/\/% No-Input FF  \tinput      \tFM_CPU2_PKGID0, \/\/% No-Input FF \tinput      \tFM_CPU2_PKGID1, \/\/% No-Input FF \tinput      \tFM_CPU2_PKGID2, \/\/% No-Input FF  \tinput      \tFM_CPU2_PROC_ID0, \/\/% No-Input FF \tinput      \tFM_CPU2_PROC_ID1, \/\/% No-Input FF  \tinput      \tFM_CPU2_INTR_PRSNT, \/\/% No-Input FF \tinput     \tFM_CPU2_SKTOCC_LVT3_N, \/\/FM_CPU2_SKTOCC_LVT3_PLD_N \/\/% No-Input FF  \/\/BMC \tinput      \tFM_BMC_PWRBTN_OUT_N, \/\/% Input FF  \tinput      \tFM_BMC_ONCTL_N, \/\/FM_BMC_ONCTL_N_PLD \/\/% Input FF \toutput     \tRST_SRST_BMC_PLD_N, \/\/RST_SRST_BMC_PLD_R_N  \toutput     \tFM_P2V5_BMC_EN, \/\/FM_P2V5_BMC_EN_R \tinput      \tPWRGD_P1V1_BMC_AUX, \/\/% Input FF  \/\/PCH \toutput     \tRST_RSMRST_N, \/\/ RST_RSMRST_PLD_R_N  \toutput     \tPWRGD_PCH_PWROK, \/\/ PWRGD_PCH_PWROK_R \toutput     \tPWRGD_SYS_PWROK, \/\/ PWRGD_SYS_PWROK_R  \tinput      \tFM_SLP_SUS_RSM_RST_N, \/\/% Input FF \tinput      \tFM_SLPS3_N, \/\/ FM_SLPS3_PLD_N \/\/% Input FF \tinput      \tFM_SLPS4_N, \/\/ FM_SLPS4_PLD_N \/\/% Input FF \tinput      \tFM_PCH_PRSNT_N, \/\/% No-Input FF  \toutput     \tFM_PCH_P1V8_AUX_EN, \/\/ FM_PCH_P1V8_AUX_EN_R  \tinput      \tPWRGD_P1V05_PCH_AUX, \/\/% Input FF \tinput      \tPWRGD_P1V8_PCH_AUX, \/\/ PWRGD_P1V8_PCH_AUX_PLD \/\/% Input FF  \toutput     \tFM_PFR_MUX_OE_CTL_PLD,   \/\/% PFR Mux Sel \tinput      \tRST_DEDI_BUSY_PLD_N,     \/\/% Dediprog RST  \/\/PSU Ctl \toutput     \tFM_PS_EN, \/\/ FM_PS_EN_PLD_R \tinput      \tPWRGD_PS_PWROK, \/\/ PWRGD_PS_PWROK_PLD_R \/\/% Input FF  \/\/Clock Logic \toutput     \tFM_PLD_CLKS_OE_N,\/\/ FM_PLD_CLKS_OE_R_N \toutput \t\tFM_CPU_BCLK5_OE_R_N,  \/\/Base Logic \tinput      \tPWRGD_P3V3_AUX, \/\/PWRGD_P3V3_AUX_PLD_R \/\/% Input FF  \/\/Main VR &amp; Logic \tinput      \tPWRGD_P3V3, \/\/% Input FF  \toutput     \tFM_P5V_EN, \toutput     \tFM_AUX_SW_EN,  \/\/Mem \tinput      \tPWRGD_CPU1_PVDDQ_ABCD, \/\/% Input FF \tinput      \tPWRGD_CPU1_PVDDQ_EFGH, \/\/% Input FF \tinput      \tPWRGD_CPU2_PVDDQ_ABCD, \/\/% Input FF \tinput      \tPWRGD_CPU2_PVDDQ_EFGH, \/\/% Input FF  \toutput     \tFM_PVPP_CPU1_EN, \toutput     \tFM_PVPP_CPU2_EN,  \/\/CPU \toutput     \tPWRGD_CPU1_LVC3, \toutput     \tPWRGD_CPU2_LVC3,  \tinput      \tPWRGD_CPUPWRGD, \/\/PWRGD_CPUPWRGD_PLD_R \/\/% Input FF \toutput     \tPWRGD_DRAMPWRGD_CPU,  \toutput     \tFM_P1V1_EN, \/\/ Used to turn on PCIE re-timmer  vr  \toutput     \tFM_P1V8_PCIE_CPU1_EN, \toutput     \tFM_P1V8_PCIE_CPU2_EN,  \toutput     \tFM_PVCCANA_CPU1_EN, \toutput     \tFM_PVCCANA_CPU2_EN,  \toutput     \tFM_PVCCIN_CPU1_EN, \toutput     \tFM_PVCCIN_CPU2_EN,  \toutput     \tFM_PVCCIO_CPU1_EN, \toutput     \tFM_PVCCIO_CPU2_EN,  \toutput     \tFM_PVCCSA_CPU1_EN, \toutput     \tFM_PVCCSA_CPU2_EN,  \tinput      \tPWRGD_BIAS_P1V1, \/\/% Input FF  \tinput      \tPWRGD_P1V8_PCIE_CPU1, \/\/% Input FF \tinput      \tPWRGD_P1V8_PCIE_CPU2, \/\/% Input FF  \tinput      \tPWRGD_PVCCIN_CPU1, \/\/% Input FF \tinput      \tPWRGD_PVCCIN_CPU2, \/\/% Input FF  \tinput      \tPWRGD_PVCCIO_CPU1, \/\/% Input FF \tinput      \tPWRGD_PVCCIO_CPU2, \/\/% Input FF  \tinput      \tPWRGD_PVCCSA_CPU1, \/\/% Input FF \tinput      \tPWRGD_PVCCSA_CPU2, \/\/% Input FF  \tinput      \tPWRGD_VCCANA_PCIE_CPU1, \/\/% Input FF \tinput      \tPWRGD_VCCANA_PCIE_CPU2, \/\/% Input FF  \/\/DBP \tinput      \tDBP_POWER_BTN_N, \/\/% Input FF \tinput      \tDBP_SYSPWROK, \/\/DBP_SYSPWROK_PLD \/\/% Input FF  \/\/Debug \tinput      \tFM_FORCE_PWRON_LVC3, \toutput     \tFM_PLD_HEARTBEAT_LVC3,  \/\/ Front Panel \toutput    \tFP_LED_FAN_FAULT_PWRSTBY_PLD_N, \/\/ Emeral ridge support \toutput    \tFP_BMC_PWR_BTN_CO_N, \/\/ need add support OD  \/\/Debug pins I\/O \toutput \t\tSGPIO_DEBUG_PLD_CLK, \tinput \t\tSGPIO_DEBUG_PLD_DIN, \toutput \t\tSGPIO_DEBUG_PLD_DOUT, \toutput \t\tSGPIO_DEBUG_PLD_LD_N,  \tinput \t\tSMB_DEBUG_PLD_SCL, \tinput \t\tSMB_DEBUG_PLD_SDA, \toutput \t\toSMB_DEBUG_PLD_SDA_OE,  \tinput \t\tFM_PLD_REV_N,  \tinput \t\tSPI_BMC_BOOT_R_CS1_N, \toutput \t\tSPI_PFR_BOOT_CS1_N );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Parameters \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ parameter  LOW =1'b0; parameter  HIGH=1'b1; parameter  FPGA_MAJOR_REV = 8'd00; parameter  FPGA_MINOR_REV = 8'd06; parameter  FPGA_DEBUG_MINIMUM_MAJOR_REV = 8'd00; parameter  FPGA_DEBUG_MINIMUM_MINOR_REV = 8'd01;  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Internal Signals \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ wire wCLK_20mSCE, wCLK_250mS, wCLK1SCE;  wire w1uSCE; wire w5uSCE; wire w10uSCE; wire w500uSCE; wire w1mSCE; wire w250mSCE; wire w20mSCE; wire w1SCE;  wire wvRstPCIePERst_n [2:0]; wire wRstPchPerstN,wRstCPU0PerstN,wRstCPU1PerstN;  wire wPsuPwrEn,wPsuPwrFlt,wPsuPwrgd,wPwrgd_Ps_Pwrok_Dly; wire wRst_n, wMemPwrEn; wire wBmcPwrgd,wBmcPwrFlt; wire wPchPwrgd,wPchPwrFlt; wire wMemPwrgd,wMemPwrFlt; wire wCpuPwrEn,wCpuPwrgd,wCpuPwrFlt;  wire wFault; wire wTimeout;  wire [2:0]  wDbgMemSt_CPU1; wire [2:0]  wDbgMemSt_CPU2; wire [3:0]  wDbgCpuSt_CPU1; wire [3:0]  wDbgCpuSt_CPU2; wire [3:0]  wDbgMstSt; wire [3:0]  wDbgMstSt7Seg; wire [3:0]  wFaultStage; wire [7:0]  wFaultState; wire [254:0] wMonitorFaultState;  wire wGoOutFltSt;  wire FM_THROTTLE_N_FF; wire IRQ_SML1_PMBUS_PLD_ALERT_N_FF;  wire FM_CPU1_THERMTRIP_LVT3_PLD_N_FF; wire FM_CPU2_THERMTRIP_LVT3_PLD_N_FF; wire FM_MEM_THERM_EVENT_CPU1_LVT3_N_FF; wire FM_MEM_THERM_EVENT_CPU2_LVT3_N_FF;  wire IRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N_FF; wire IRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N_FF; wire IRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N_FF; wire IRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N_FF;  wire FM_CPU1_MEMTRIP_N_FF; wire FM_CPU2_MEMTRIP_N_FF;  wire FM_PVCCIN_CPU1_PWR_IN_ALERT_N_FF; wire FM_PVCCIN_CPU2_PWR_IN_ALERT_N_FF; wire IRQ_PVCCIN_CPU1_VRHOT_LVC3_N_FF; wire IRQ_PVCCIN_CPU2_VRHOT_LVC3_N_FF;  wire FM_BMC_PWRBTN_OUT_N_FF; wire FM_BMC_ONCTL_N_FF;  wire FM_SLP_SUS_RSM_RST_N_FF;  wire DBP_POWER_BTN_N_FF;  wire RST_PLTRST_N_FF; wire FM_SLPS3_N_FF; wire FM_SLPS4_N_FF;  wire PWRGD_P1V1_BMC_AUX_FF; wire PWRGD_P1V8_PCH_AUX_FF; wire PWRGD_P1V05_PCH_AUX_FF; wire PWRGD_PS_PWROK_FF; wire PWRGD_P3V3_AUX_FF; wire PWRGD_P3V3_FF; wire PWRGD_CPU1_PVDDQ_ABCD_FF; wire PWRGD_CPU1_PVDDQ_EFGH_FF; wire PWRGD_CPU2_PVDDQ_ABCD_FF; wire PWRGD_CPU2_PVDDQ_EFGH_FF; wire PWRGD_CPUPWRGD_FF; wire PWRGD_BIAS_P1V1_FF; wire PWRGD_P1V8_PCIE_CPU1_FF; wire PWRGD_P1V8_PCIE_CPU2_FF; wire PWRGD_PVCCIN_CPU1_FF; wire PWRGD_PVCCIN_CPU2_FF; wire PWRGD_PVCCIO_CPU1_FF; wire PWRGD_PVCCIO_CPU2_FF; wire PWRGD_PVCCSA_CPU1_FF; wire PWRGD_PVCCSA_CPU2_FF; wire PWRGD_VCCANA_PCIE_CPU1_FF; wire PWRGD_VCCANA_PCIE_CPU2_FF;  wire FM_ADR_COMPLETE_FF; wire FM_PLD_PCH_DATA_FF; wire FM_PS_PWROK_DLY_SEL_FF; wire FM_DIS_PS_PWROK_DLY_FF; wire FM_PMBUS_ALERT_B_EN_FF;  wire FM_CPU1_FIVR_FAULT_LVT3_FF; wire FM_CPU2_FIVR_FAULT_LVT3_FF;  wire DBP_SYSPWROK_FF;  wire wCPUPwrGd_Dly;   wire [7:0]  wvPOSTCodeLEDs; wire [7:0]  wvFanFaultLEDs; wire [15:0] wvP1DIMMLEDs; wire [15:0] wvP2DIMMLEDs; wire [15:0] wvP3DIMMLEDs; wire [15:0] wvP4DIMMLEDs; wire \t\twvMCPSilicon; wire        wSocketRemoved;  wire wValidForcePowerOn; wire wPWRGD_CPU_LVC3;  wire wPchPwrFltP1V05; wire wPchPwrFltP1V8; wire wSysOk; wire wCPUMismatch; wire wPWRGD_PS_PWROK_DLY; wire wPWRGD_PS_PWROK_DLY_ADR;  wire wMainVRPwrEn; wire wMainPwrFlt; wire wP3v3PwrFlt; wire wMainVRPwrgd; wire wFM_AUX_SW_EN; wire wFM_P5V_EN;  wire wMemPwrFltVDDQ_CPU1_ABCD; wire wMemPwrFltVDDQ_CPU1_EFHG; wire wMemPwrgd_CPU1; wire wMemPwrFlt_CPU1;  wire wMemPwrFltVDDQ_CPU2_ABCD; wire wMemPwrFltVDDQ_CPU2_EFHG; wire wMemPwrgd_CPU2; wire wMemPwrFlt_CPU2;  wire wCpuPwrgd_CPU1; wire wCpuPwrFlt_CPU1; wire wPWRGD_PVCCIO_CPU1; wire wCpuPwrFltVCCIO_CPU1; wire wCpuPwrFltP1V8_PCIE_CPU1; wire wCpuPwrFltVCCANA_CPU1; wire wCpuPwrFltVCCIN_CPU1; wire wCpuPwrFltVCCSA_CPU1;  wire wCpuPwrgd_CPU2; wire wCpuPwrFlt_CPU2; wire wFM_PVCCIO_CPU2_EN; wire wCpuPwrFltVCCIO_CPU2; wire wCpuPwrFltP1V8_PCIE_CPU2; wire wCpuPwrFltVCCANA_CPU2; wire wCpuPwrFltVCCIN_CPU2; wire wCpuPwrFltVCCSA_CPU2;  wire FM_BMC_ONCTL_N_LATCH;  wire wPwrEn;  wire wFM_CPU1_THERMTRIP_N; wire wFM_CPU2_THERMTRIP_N;  wire [127:0] wInputLEDMux; wire [7:0] wvPOSTCodeLEDMux;  wire wFM_CPU1_SKTOCC_LVT3_N; wire wFM_CPU2_SKTOCC_LVT3_N;  wire wRSMRST_Delay_Dedi, wRSMRST_N;  wire [6:0] wByteSeg1_RevMajor; wire [6:0] wByteSeg2_RevMinor;  wire [7:0] FPGA_REV_Major_DebugPLD; wire [7:0] FPGA_REV_Minor_DebugPLD;  wire FM_PLD_REV_N_FF; wire wDebugPLD_Valid;  wire wICX; \/\/This indicates PROC ID is the ICX one and 1.8 and 2.0 vrs are not enabled  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ \/\/ Continuous assignments                                                          \/\/ \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ \/\/ Signal by ByPass for Force Power on, will turn on if the silicon is not populated assign wFM_CPU1_SKTOCC_LVT3_N = wValidForcePowerOn ? LOW : FM_CPU1_SKTOCC_LVT3_N; assign wFM_CPU2_SKTOCC_LVT3_N = wValidForcePowerOn ? LOW : FM_CPU2_SKTOCC_LVT3_N;  assign wValidForcePowerOn = FM_FORCE_PWRON_LVC3 &amp;&amp; FM_PCH_PRSNT_N  &amp;&amp; (FM_CPU1_SKTOCC_LVT3_N || wSysOk) &amp;&amp; (FM_CPU2_SKTOCC_LVT3_N || wSysOk); \/\/this is only valid if silicon is not populated or STP is present (PROC_ID and PKG_ID are 1's)  assign FM_PLD_HEARTBEAT_LVC3 = RST_PLTRST_N_FF ? 1'b0 : (wDbgMstSt == 4'd0) ? wCLK_20mSCE : wCLK_250mS; \/\/ This will indicate if a fault coundtion is detected  GlitchFilter2 GlitchFilter2_inst (  .iClk(iClk_2M),\/\/% Clock Input  .iRst(wRst_n),\/\/% Asynchronous Reset Input  .iSignal(PWRGD_CPUPWRGD &amp;&amp; PWRGD_PCH_PWROK),\/\/% Input Signals  .oFilteredSignals(wPWRGD_CPU_LVC3)\/\/%Glitchless Signal );  assign PWRGD_CPU1_LVC3 = (!wFM_CPU1_SKTOCC_LVT3_N) ? wPWRGD_CPU_LVC3 : LOW; assign PWRGD_CPU2_LVC3 = (!wFM_CPU2_SKTOCC_LVT3_N) ? wPWRGD_CPU_LVC3 : LOW;  \/\/% This logic is for enable VCCIO of CPU2 in case the SKTOCC for CPU2 is empty, both VCCIO VR need be ON. assign FM_PVCCIO_CPU2_EN = (!wFM_CPU2_SKTOCC_LVT3_N)    ? wFM_PVCCIO_CPU2_EN    : FM_PVCCIO_CPU1_EN ; \/\/ VCCIO need be always ON to avoid SI issues. assign wPWRGD_PVCCIO_CPU1= (wFM_CPU2_SKTOCC_LVT3_N)     ? PWRGD_PVCCIO_CPU1_FF  : (PWRGD_PVCCIO_CPU1_FF &amp;&amp; PWRGD_PVCCIO_CPU2_FF) ; \/\/ VCCIO need be always ON to avoid SI issues.  assign RST_PLTRST_B_N = RST_PLTRST_N_FF;  assign RST_CPU1_LVC3_N = (!wFM_CPU1_SKTOCC_LVT3_N)  ? RST_PLTRST_N_FF : LOW; assign RST_CPU2_LVC3_N = (!wFM_CPU2_SKTOCC_LVT3_N)  ? RST_PLTRST_N_FF : LOW;  assign FP_LED_FAN_FAULT_PWRSTBY_PLD_N = (wvFanFaultLEDs==8'h00) ? HIGH : LOW; assign FM_P1V1_EN      = (FM_CPU1_INTR_PRSNT &amp;&amp; !wValidForcePowerOn) ? FM_PVCCIO_CPU1_EN : FM_P1V8_PCIE_CPU1_EN;  assign wMemPwrgd =  (!wFM_CPU2_SKTOCC_LVT3_N) ? (wMemPwrgd_CPU1 &amp;&amp; wMemPwrgd_CPU2) : (wMemPwrgd_CPU1); assign wCpuPwrgd =  (!wFM_CPU2_SKTOCC_LVT3_N) ? (wCpuPwrgd_CPU1 &amp;&amp; wCpuPwrgd_CPU2) : (wCpuPwrgd_CPU1);  assign wMemPwrFlt = (!wFM_CPU2_SKTOCC_LVT3_N) ? (wMemPwrFlt_CPU1 || wMemPwrFlt_CPU2) : (wMemPwrFlt_CPU1); assign wCpuPwrFlt = (!wFM_CPU2_SKTOCC_LVT3_N) ? (wCpuPwrFlt_CPU1 || wCpuPwrFlt_CPU2) : (wCpuPwrFlt_CPU1);  assign wRSMRST_N = RST_RSMRST_N; assign FM_PFR_MUX_OE_CTL_PLD = ( !wRSMRST_Delay_Dedi ) ? LOW : RST_DEDI_BUSY_PLD_N;\/\/Should be 0 until 500us after RSMRST is asserted. After this, follow RST_DEDI signal  assign SPI_PFR_BOOT_CS1_N = SPI_BMC_BOOT_R_CS1_N;\t\/\/PLD does not run security checks at its own.  assign wByteSeg1_RevMajor = !wCLK1SCE ? FPGA_MAJOR_REV[6:0]\t: FPGA_REV_Major_DebugPLD[6:0]; assign wByteSeg2_RevMinor = !wCLK1SCE ? FPGA_MINOR_REV[6:0]\t: FPGA_REV_Minor_DebugPLD[6:0];  assign o1mSCE \t\t\t\t\t= w1mSCE; assign wDebugPLD_Valid = ( (FPGA_REV_Major_DebugPLD &lt;= FPGA_DEBUG_MINIMUM_MAJOR_REV[6:0]) &amp;&amp; (FPGA_REV_Minor_DebugPLD &lt;= FPGA_DEBUG_MINIMUM_MINOR_REV[6:0]))? HIGH : LOW;   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Global Reset \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ reset mReset ( \t.PWRGD_P3V3_AUX(PWRGD_P3V3_AUX), \t.iClk_2M(iClk_2M), \t.oRst_n(wRst_n) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Clock generation and CE \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/% Clock divider three - Generates the following synchronous clock enables: 10uS, 50uS, 500uS, 1mS, 20mS and 250mS ClkDivTree mClkDivTree ( \t.iClk       ( iClk_2M  \t), \t.iRst       ( ~wRst_n  \t), \t.o1uSCE     ( w1uSCE   \t), \t.o5uSCE    \t( w5uSCE  \t), \t.o10uSCE    ( w10uSCE  \t), \t.o500uSCE   ( w500uSCE \t), \t.o1mSCE     ( w1mSCE   \t), \t.o250mSCE   ( w250mSCE \t), \t.o20mSCE    ( w20mSCE  \t), \t.o1SCE      ( w1SCE    \t) );  Toggle mToggle250mSCE \/\/ module to Toggle ( \t.iRst    (~wRst_n), \t\/\/%Reset Input \t.iClk    (iClk_2M), \t\/\/% Clock Input \t.iCE     (w250mSCE),   \t\/\/% Clock Enable \t.oTSignal(wCLK_250mS)\t\/\/% Output Signal Toggle );  Toggle mTogglew20mSCE \/\/ module to Toggle ( \t.iRst    (~wRst_n), \t\/\/%Reset Input \t.iClk    (iClk_2M), \t\/\/% Clock Input \t.iCE     (w20mSCE),   \t\/\/% Clock Enable \t.oTSignal(wCLK_20mSCE)\t\/\/% Output Signal Toggle );  Toggle mTogglew1SCE \/\/ module to Toggle ( \t.iRst    (~wRst_n), \/\/%Reset Input \t.iClk    (iClk_2M), \/\/% Clock Input \t.iCE     (w1SCE),   \/\/% Clock Enable \t.oTSignal(wCLK1SCE)\t\/\/% Output Signal Toggle );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/Inputs Synchronizer \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/% Active Low InputsSyncWithDefault # ( \t.SIZE               ( 5'd20 ), \t.DEFAULT_OUT    \t( 1'b1 ) )mSlpSync0 ( \t.iClk               ( iClk_2M ), \t.iRst_n             ( wRst_n ), \t.ivSync             ({ \t\t\t\t\t\t\tFM_THROTTLE_N, \t\t\t\t\t\t\tIRQ_SML1_PMBUS_PLD_ALERT_N,  \t\t\t\t\t\t\tFM_CPU1_THERMTRIP_LVT3_PLD_N, \t\t\t\t\t\t\tFM_CPU2_THERMTRIP_LVT3_PLD_N, \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU1_LVT3_N, \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU2_LVT3_N,  \t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N,  \t\t\t\t\t\t\tFM_CPU1_MEMTRIP_N, \t\t\t\t\t\t\tFM_CPU2_MEMTRIP_N,  \t\t\t\t\t\t\tFM_PVCCIN_CPU1_PWR_IN_ALERT_N, \t\t\t\t\t\t\tFM_PVCCIN_CPU2_PWR_IN_ALERT_N, \t\t\t\t\t\t\tIRQ_PVCCIN_CPU1_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVCCIN_CPU2_VRHOT_LVC3_N,  \t\t\t\t\t\t\tFM_BMC_PWRBTN_OUT_N, \t\t\t\t\t\t\tFM_BMC_ONCTL_N,  \t\t\t\t\t\t\tFM_SLP_SUS_RSM_RST_N,  \t\t\t\t\t\t\tDBP_POWER_BTN_N \t\t\t\t\t\t\t}), \t.ovSync             ({ \t\t\t\t\t\t\tFM_THROTTLE_N_FF, \t\t\t\t\t\t\tIRQ_SML1_PMBUS_PLD_ALERT_N_FF,  \t\t\t\t\t\t\tFM_CPU1_THERMTRIP_LVT3_PLD_N_FF, \t\t\t\t\t\t\tFM_CPU2_THERMTRIP_LVT3_PLD_N_FF, \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU1_LVT3_N_FF, \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU2_LVT3_N_FF,  \t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N_FF, \t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N_FF, \t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N_FF, \t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N_FF,  \t\t\t\t\t\t\tFM_CPU1_MEMTRIP_N_FF, \t\t\t\t\t\t\tFM_CPU2_MEMTRIP_N_FF,  \t\t\t\t\t\t\tFM_PVCCIN_CPU1_PWR_IN_ALERT_N_FF, \t\t\t\t\t\t\tFM_PVCCIN_CPU2_PWR_IN_ALERT_N_FF, \t\t\t\t\t\t\tIRQ_PVCCIN_CPU1_VRHOT_LVC3_N_FF, \t\t\t\t\t\t\tIRQ_PVCCIN_CPU2_VRHOT_LVC3_N_FF,  \t\t\t\t\t\t\tFM_BMC_PWRBTN_OUT_N_FF, \t\t\t\t\t\t\tFM_BMC_ONCTL_N_FF,  \t\t\t\t\t\t\tFM_SLP_SUS_RSM_RST_N_FF,  \t\t\t\t\t\t\tDBP_POWER_BTN_N_FF \t\t\t\t\t\t  }) );   \/\/% Active Low InputsSyncWithDefault # ( \t.SIZE               ( 3'd4 ), \t.DEFAULT_OUT    \t( 1'b0 ) )mSlpSync1 ( \t.iClk               ( iClk_2M ), \t.iRst_n             ( wRst_n ), \t.ivSync             ({ \t\t\t\t\t\t\tRST_PLTRST_N, \t\t\t\t\t\t\tFM_SLPS3_N, \t\t\t\t\t\t\tFM_SLPS4_N,  \t\t\t\t\t\t\tFM_PLD_REV_N \t\t\t\t\t\t}), \t.ovSync             ({ \t\t\t\t\t\t\tRST_PLTRST_N_FF, \t\t\t\t\t\t\tFM_SLPS3_N_FF, \t\t\t\t\t\t\tFM_SLPS4_N_FF,  \t\t\t\t\t\t\tFM_PLD_REV_N_FF \t\t\t\t\t\t}) );   \/\/% Active High InputsSyncWithDefault # ( \t.SIZE               ( 5'd22 ), \t.DEFAULT_OUT    \t( 1'b0  ) )mSlpSync2 ( \t.iClk               ( iClk_2M ), \t.iRst_n             ( wRst_n ), \t.ivSync             ({ \t\t\t\t\t\t\tPWRGD_P1V1_BMC_AUX, \t\t\t\t\t\t\tPWRGD_P1V8_PCH_AUX, \t\t\t\t\t\t\tPWRGD_P1V05_PCH_AUX, \t\t\t\t\t\t\tPWRGD_PS_PWROK, \t\t\t\t\t\t\tPWRGD_P3V3_AUX, \t\t\t\t\t\t\tPWRGD_P3V3, \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_ABCD, \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_EFGH, \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_ABCD, \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_EFGH, \t\t\t\t\t\t\tPWRGD_CPUPWRGD, \t\t\t\t\t\t\tPWRGD_BIAS_P1V1, \t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU1, \t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU2, \t\t\t\t\t\t\tPWRGD_PVCCIN_CPU1, \t\t\t\t\t\t\tPWRGD_PVCCIN_CPU2, \t\t\t\t\t\t\tPWRGD_PVCCIO_CPU1, \t\t\t\t\t\t\tPWRGD_PVCCIO_CPU2, \t\t\t\t\t\t\tPWRGD_PVCCSA_CPU1, \t\t\t\t\t\t\tPWRGD_PVCCSA_CPU2, \t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU1, \t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU2 \t\t\t\t\t\t\t}), \t.ovSync             ({ \t\t\t\t\t\t\tPWRGD_P1V1_BMC_AUX_FF, \t\t\t\t\t\t\tPWRGD_P1V8_PCH_AUX_FF, \t\t\t\t\t\t\tPWRGD_P1V05_PCH_AUX_FF, \t\t\t\t\t\t\tPWRGD_PS_PWROK_FF, \t\t\t\t\t\t\tPWRGD_P3V3_AUX_FF, \t\t\t\t\t\t\tPWRGD_P3V3_FF, \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_ABCD_FF, \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_EFGH_FF, \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_ABCD_FF, \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_EFGH_FF, \t\t\t\t\t\t\tPWRGD_CPUPWRGD_FF, \t\t\t\t\t\t\tPWRGD_BIAS_P1V1_FF, \t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU1_FF, \t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU2_FF, \t\t\t\t\t\t\tPWRGD_PVCCIN_CPU1_FF, \t\t\t\t\t\t\tPWRGD_PVCCIN_CPU2_FF, \t\t\t\t\t\t\tPWRGD_PVCCIO_CPU1_FF, \t\t\t\t\t\t\tPWRGD_PVCCIO_CPU2_FF, \t\t\t\t\t\t\tPWRGD_PVCCSA_CPU1_FF, \t\t\t\t\t\t\tPWRGD_PVCCSA_CPU2_FF, \t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU1_FF, \t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU2_FF \t\t\t\t\t\t  }) );  \/\/% Active High InputsSyncWithDefault # ( \t.SIZE               ( 4'd8 ), \t.DEFAULT_OUT    \t( 1'b0 ) )mSlpSync3 ( \t.iClk               ( iClk_2M ), \t.iRst_n             ( wRst_n ), \t.ivSync             ({ \t\t\t\t\t\t\tFM_ADR_COMPLETE, \t\t\t\t\t\t\tFM_PLD_PCH_DATA, \t\t\t\t\t\t\tFM_PS_PWROK_DLY_SEL, \t\t\t\t\t\t\tFM_DIS_PS_PWROK_DLY, \t\t\t\t\t\t\tFM_PMBUS_ALERT_B_EN,  \t\t\t\t\t\t\tFM_CPU1_FIVR_FAULT_LVT3, \t\t\t\t\t\t\tFM_CPU2_FIVR_FAULT_LVT3,  \t\t\t\t\t\t\tDBP_SYSPWROK \t\t\t\t\t\t\t}), \t.ovSync             ({ \t\t\t\t\t\t\tFM_ADR_COMPLETE_FF, \t\t\t\t\t\t\tFM_PLD_PCH_DATA_FF, \t\t\t\t\t\t\tFM_PS_PWROK_DLY_SEL_FF, \t\t\t\t\t\t\tFM_DIS_PS_PWROK_DLY_FF, \t\t\t\t\t\t\tFM_PMBUS_ALERT_B_EN_FF,  \t\t\t\t\t\t\tFM_CPU1_FIVR_FAULT_LVT3_FF, \t\t\t\t\t\t\tFM_CPU2_FIVR_FAULT_LVT3_FF,  \t\t\t\t\t\t\tDBP_SYSPWROK_FF \t\t\t\t\t\t  }) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Power Secuence \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ Bmc_Seq mBmc_Seq ( \t.iClk               (iClk_2M), \t.iRst_n             (wRst_n), \t.i1mSCE             (w1mSCE), \t.iGoOutFltSt        (wGoOutFltSt), \t\/\/input \t.PWRGD_P1V1_BMC_AUX (PWRGD_P1V1_BMC_AUX_FF), \t.PWRGD_P3V3_AUX     (PWRGD_P3V3_AUX_FF), \t.PWRGD_PCH_P1V8     (PWRGD_P1V8_PCH_AUX_FF), \t.FM_SLP_SUS_N       (FM_SLP_SUS_RSM_RST_N_FF),  \t.RST_DEDI_BUSY_PLD_N(wRST_DEDI_BUSY_PLD_N),  \t\/\/output \t.FM_BMC_P2V5_AUX_EN (FM_P2V5_BMC_EN), \t.RST_SRST_BMC_N     (RST_SRST_BMC_PLD_N),  \t.oBmcPwrgd          (wBmcPwrgd), \t.oBmcPwrFlt         (wBmcPwrFlt) );   Pch_Seq mPch_Seq ( \t.iClk          \t\t\t(iClk_2M), \t.iRst_n        \t\t\t(wRst_n), \t.i1mSCE        \t\t\t(w1mSCE), \t.i1uSCE        \t\t\t(w1uSCE), \t.iGoOutFltSt   \t\t\t(wGoOutFltSt), \t\/\/input \t.FM_PCH_PRSNT_N        \t(wValidForcePowerOn ? LOW : FM_PCH_PRSNT_N), \t.PWRGD_P3V3_AUX        \t(PWRGD_P3V3_AUX_FF), \t.FM_SLP_SUS_N          \t(FM_SLP_SUS_RSM_RST_N_FF), \t.RST_SRST_BMC_N        \t(RST_SRST_BMC_PLD_N),  \t.PWRGD_PCH_P1V8_AUX    \t(PWRGD_P1V8_PCH_AUX_FF), \t.PWRGD_PCH_P1V05_AUX   \t(PWRGD_P1V05_PCH_AUX_FF),  \t.RST_DEDI_BUSY_PLD_N   \t(RST_DEDI_BUSY_PLD_N),  \t\/\/output  \t.FM_PCH_P1V8_AUX_EN    \t(FM_PCH_P1V8_AUX_EN), \t.RST_RSMRST_N          \t(RST_RSMRST_N),  \t.oPchPwrFltP1V05       \t(wPchPwrFltP1V05), \t.oPchPwrFltP1V8        \t(wPchPwrFltP1V8),  \t.oPchPwrgd             \t(wPchPwrgd), \t.oPchPwrFlt            \t(wPchPwrFlt) );   SysCheck mSysCheck ( \t.iClk                   (iClk_2M), \t.iRst                   (wRst_n), \t.invCPUSktOcc           ({wFM_CPU2_SKTOCC_LVT3_N,wFM_CPU1_SKTOCC_LVT3_N}), \t.ivProcIDCPU1           ({FM_CPU1_PROC_ID1,FM_CPU1_PROC_ID0}), \t.ivProcIDCPU2           ({FM_CPU2_PROC_ID1,FM_CPU2_PROC_ID0}), \t.ivPkgIDCPU1            ({FM_CPU1_PKGID2,FM_CPU1_PKGID1,FM_CPU1_PKGID0}), \t.ivPkgIDCPU2            ({FM_CPU2_PKGID2,FM_CPU2_PKGID1,FM_CPU2_PKGID0}), \t.ivIntr                 ({FM_CPU2_INTR_PRSNT,FM_CPU1_INTR_PRSNT}), \t.iAuxPwrDone            ( PWRGD_P1V05_PCH_AUX_FF ), \t.oSysOk                 ( wSysOk ), \t.oCPUMismatch           ( wCPUMismatch ), \t.oMCPSilicon            ( wvMCPSilicon ), \t.oSocketRemoved\t(wSocketRemoved), \t.oICX\t\t\t(wICX) );   \/\/S5 to S0 VR logic PSU_Seq mPSU_Seq ( \t.iClk                  \t(iClk_2M), \t.iRst_n                \t(wRst_n), \t.i1mSCE                \t(w1mSCE), \t.iGoOutFltSt           \t(wGoOutFltSt), \t\/\/input \t.iPsuPwrEn             \t(wPsuPwrEn), \t.PWRGD_PS_PWROK        \t(wPWRGD_PS_PWROK_DLY_ADR\/*PWRGD_PS_PWROK_FF*\/),\t\/\/ need cover ADR logic \t\/\/output \t.oPsuPwrFlt            \t(wPsuPwrFlt),   \t\/\/ output \t.oPsuPwrgd             \t(wPsuPwrgd),   \t\/\/ output \t.PWRGD_PS_PWROK_DLY    \t(wPWRGD_PS_PWROK_DLY),  \/\/ output  include power up 100ms delay \t.FM_PS_EN              \t(FM_PS_EN)     \t\/\/ output );   MainVR_Seq mMainVR_Seq ( \t.iClk                  \t(iClk_2M), \t\/\/ input \t.iRst_n                \t(wRst_n), \t\/\/ input \t.iGoOutFltSt           \t(wGoOutFltSt), \t\/\/input \t.iMainVRPwrEn          \t(wMainVRPwrEn), \t.PWRGD_PS_PWROK        \t(wPWRGD_PS_PWROK_DLY_ADR),\/\/% PWRGD PS PWROK . \t.PWRGD_P3V3            \t(PWRGD_P3V3_FF),\/\/% Pwrgd from P3V3 VR  \t\/\/ output \t.oMainPwrFlt           \t(wMainPwrFlt),\t\/\/% Fault condition. \t.oP3v3PwrFlt           \t(wP3v3PwrFlt), \t\/\/% Fault P3V3 VR \t.oMainVRPwrgd          \t(wMainVRPwrgd),\t\/\/% Main Vr's Enable  \t.FM_AUX_SW_EN          \t(FM_AUX_SW_EN),\t\/\/% 12V Only PSU Control  AUX to Main SW \t.FM_P5V_EN             \t(FM_P5V_EN)\t\t\/\/% P5V and P3V3 main Voltage enable );   ClockLogic mClockLogic ( \t.iClk                 \t(iClk_2M), \/\/ input \t.iRst_n               \t(wRst_n), \/\/ input  \t.iMainVRPwrgd     \t\t(wMainVRPwrgd), \t.iMCP_EN_CLK      \t\t(wvMCPSilicon),    \/\/ICX MCP \t.PWRGD_PCH_PWROK  \t\t(PWRGD_PCH_PWROK),  \t\/\/output \t.FM_PLD_CLKS_OE_N   \t(FM_PLD_CLKS_OE_N), \t.FM_CPU_BCLK5_OE_N \t\t(FM_CPU_BCLK5_OE_R_N) );   Mem_Seq mMem_SeqCPU1 ( \t.iClk                  \t(iClk_2M), \t.iRst_n                \t(wRst_n), \t.i1mSCE                \t(w1mSCE), \t.iMemPwrEn             \t(wMemPwrEn),    \/\/ input \t.iGoOutFltSt           \t(wGoOutFltSt),  \/\/ input \t.iEnableTimeOut        \t(LOW), \t.PWRGD_P3V3            \t(PWRGD_P3V3_FF),                 \/\/ input \t.PWRGD_VDDQ_ABCD       \t(PWRGD_CPU1_PVDDQ_ABCD_FF),   \/\/ input \t.PWRGD_VDDQ_EFGH       \t(PWRGD_CPU1_PVDDQ_EFGH_FF),   \/\/ input \t.FM_SLPS4_N            \t(FM_SLPS4_N_FF || wValidForcePowerOn),\/\/input  \t.FM_MEM_VPP_EN         \t(FM_PVPP_CPU1_EN),  \/\/ output  \t.oMemPwrFltVDDQ_ABCD   \t(wMemPwrFltVDDQ_CPU1_ABCD), \t.oMemPwrFltVDDQ_EFHG   \t(wMemPwrFltVDDQ_CPU1_EFHG), \t.oMemPwrgd             \t(wMemPwrgd_CPU1),    \/\/ output \t.oMemPwrFlt            \t(wMemPwrFlt_CPU1),   \/\/ output \t.oDbgMemSt             \t(wDbgMemSt_CPU1)  \/\/ output [2:0] oDbgMemSt );   Mem_Seq mMem_SeqCPU2 ( \t.iClk                  \t(iClk_2M), \t.iRst_n                \t(wRst_n), \t.i1mSCE                \t(w1mSCE), \t.iMemPwrEn             \t(wMemPwrEn &amp;&amp; (!wFM_CPU2_SKTOCC_LVT3_N)),    \/\/ input \t.iGoOutFltSt           \t(wGoOutFltSt),  \/\/ input \t.iEnableTimeOut        \t(LOW), \t.PWRGD_P3V3            \t(PWRGD_P3V3_FF),                 \/\/ input \t.PWRGD_VDDQ_ABCD       \t(PWRGD_CPU2_PVDDQ_ABCD_FF),   \/\/ input \t.PWRGD_VDDQ_EFGH       \t(PWRGD_CPU2_PVDDQ_EFGH_FF),   \/\/ input \t.FM_SLPS4_N        \t\t(FM_SLPS4_N_FF || wValidForcePowerOn),  \/\/input  \t.FM_MEM_VPP_EN         \t(FM_PVPP_CPU2_EN),  \/\/ output  \t.oMemPwrFltVDDQ_ABCD   \t(wMemPwrFltVDDQ_CPU2_ABCD), \t.oMemPwrFltVDDQ_EFHG   \t(wMemPwrFltVDDQ_CPU2_EFHG), \t.oMemPwrgd             \t(wMemPwrgd_CPU2),    \/\/ output \t.oMemPwrFlt            \t(wMemPwrFlt_CPU2),   \/\/ output \t.oDbgMemSt             \t(wDbgMemSt_CPU2)  \/\/ output [2:0] oDbgMemSt );   Cpu_Seq mCpu_Seq_CPU1 ( \t.iClk                   (iClk_2M), \t.iRst_n                 (wRst_n), \t.i1mSCE                 (w1mSCE),  \t.iCpuPwrEn              (wCpuPwrEn),    \/\/ input \t.iGoOutFltSt            (wGoOutFltSt),  \/\/ input \t.iEnableTimeOut         (LOW), \t.iICX\t\t\t\t(wICX),  \t.FM_INTR_PRSNT          (wValidForcePowerOn ? LOW : FM_CPU1_INTR_PRSNT),\/\/ input  \t.PWRGD_PVCCIO           (wPWRGD_PVCCIO_CPU1), \/\/ input \t.PWRGD_P1V8_PCIE        (PWRGD_P1V8_PCIE_CPU1_FF &amp;&amp; PWRGD_BIAS_P1V1_FF),\/\/ input \/\/ PWRGD_BIAS_P1V1 to support PCIE retimmer VR \t.PWRGD_PVCCANA          (PWRGD_VCCANA_PCIE_CPU1_FF),\/\/ input \t.PWRGD_PVCCIN           (PWRGD_PVCCIN_CPU1_FF),\/\/ input \t.PWRGD_PVCCSA           (PWRGD_PVCCSA_CPU1_FF),\/\/ input   \t.FM_PVCCIO_EN           (FM_PVCCIO_CPU1_EN),  \/\/ output \t.FM_P1V8_PCIE_EN        (FM_P1V8_PCIE_CPU1_EN),  \/\/ output \t.FM_PVCCANA_EN          (FM_PVCCANA_CPU1_EN),   \/\/ output \t.FM_PVCCIN_EN           (FM_PVCCIN_CPU1_EN),    \/\/ output \t.FM_PVCCSA_EN           (FM_PVCCSA_CPU1_EN), \/\/ output  \t.oCpuPwrFltVCCIO        (wCpuPwrFltVCCIO_CPU1), \t.oCpuPwrFltP1V8_PCIE    (wCpuPwrFltP1V8_PCIE_CPU1), \t.oCpuPwrFltVCCANA       (wCpuPwrFltVCCANA_CPU1), \t.oCpuPwrFltVCCIN        (wCpuPwrFltVCCIN_CPU1), \t.oCpuPwrFltVCCSA        (wCpuPwrFltVCCSA_CPU1),  \t.oCpuPwrgd              (wCpuPwrgd_CPU1),    \/\/ output \t.oCpuPwrFlt             (wCpuPwrFlt_CPU1),   \/\/ output \t.oDbgCpuSt              (wDbgCpuSt_CPU1)  \/\/ output [3:0] oDbgCpuSt );   Cpu_Seq mCpu_Seq_CPU2 ( \t.iClk                   (iClk_2M), \t.iRst_n                 (wRst_n), \t.i1mSCE                 (w1mSCE),  \t.iCpuPwrEn              (wCpuPwrEn &amp;&amp; !wFM_CPU2_SKTOCC_LVT3_N),    \/\/ input \t.iGoOutFltSt            (wGoOutFltSt),  \/\/ input \t.iEnableTimeOut         (LOW), \t.iICX\t\t\t\t(wICX),  \t.FM_INTR_PRSNT          (wValidForcePowerOn ? LOW : FM_CPU2_INTR_PRSNT),\/\/ input  \t.PWRGD_PVCCIO           (PWRGD_PVCCIO_CPU2_FF), \/\/ input \t.PWRGD_P1V8_PCIE        (PWRGD_P1V8_PCIE_CPU2_FF),\/\/ input \t.PWRGD_PVCCANA          (PWRGD_VCCANA_PCIE_CPU2_FF),\/\/ input \t.PWRGD_PVCCIN           (PWRGD_PVCCIN_CPU2_FF),\/\/ input \t.PWRGD_PVCCSA           (PWRGD_PVCCSA_CPU2_FF),\/\/ input   \t.FM_PVCCIO_EN           (wFM_PVCCIO_CPU2_EN),  \/\/ output \t.FM_P1V8_PCIE_EN        (FM_P1V8_PCIE_CPU2_EN),  \/\/ output \t.FM_PVCCANA_EN          (FM_PVCCANA_CPU2_EN),   \/\/ output \t.FM_PVCCIN_EN           (FM_PVCCIN_CPU2_EN),    \/\/ output \t.FM_PVCCSA_EN           (FM_PVCCSA_CPU2_EN), \/\/ output  \t.oCpuPwrFltVCCIO        (wCpuPwrFltVCCIO_CPU2), \t.oCpuPwrFltP1V8_PCIE    (wCpuPwrFltP1V8_PCIE_CPU2), \t.oCpuPwrFltVCCANA       (wCpuPwrFltVCCANA_CPU2), \t.oCpuPwrFltVCCIN        (wCpuPwrFltVCCIN_CPU2), \t.oCpuPwrFltVCCSA        (wCpuPwrFltVCCSA_CPU2),  \t.oCpuPwrgd              (wCpuPwrgd_CPU2),    \/\/ output \t.oCpuPwrFlt             (wCpuPwrFlt_CPU2),   \/\/ output \t.oDbgCpuSt              (wDbgCpuSt_CPU2)  \t\/\/ output [3:0] oDbgCpuSt );   PwrgdLogic mPwrgdLogic ( \t.iClk                  \t(iClk_2M), \t.iRst_n                \t(wRst_n), \t.i1mSCE                \t(w1mSCE),  \t.iMemPwrgd             \t(wMemPwrgd),    \t\/\/ input \t.iCpuPwrgd             \t(wCpuPwrgd),    \t\/\/ input \t.iBmcPwrgd             \t(wBmcPwrgd),    \t\/\/ input \t.iPchPwrgd             \t(wPchPwrgd),    \t\/\/ input \t.FM_SLPS3_N            \t(FM_SLPS3_N_FF || wValidForcePowerOn),\t\/\/ input \t.FM_SLPS4_N            \t(FM_SLPS4_N_FF || wValidForcePowerOn),\t\/\/ input \t.PWRGD_PS_PWROK_DLY    \t(wPWRGD_PS_PWROK_DLY_ADR), \t.DBP_SYSPWROK          \t(DBP_SYSPWROK_FF),\t\/\/input \t.PWRGD_CPUPWRGD        \t(PWRGD_CPUPWRGD),  \t.PWRGD_DRAMPWRGD_CPU   \t(PWRGD_DRAMPWRGD_CPU), \t\/\/ output \t\/\/.PWRGD_CPU_LVC3        \t(wPWRGD_CPU_LVC3), \t\t\/\/output \t.PWRGD_PCH_PWROK       (PWRGD_PCH_PWROK),\t\t\/\/ output \t.PWRGD_SYS_PWROK       \t(PWRGD_SYS_PWROK)  \t\t\/\/ output );   ADR mADR ( \t.iClk                   (iClk_2M),    \t\/\/ input \t.iRst_n                 (wRst_n),   \t\/\/ input \t.i10uSCE                (w10uSCE),  \t.PWRGD_PS_PWROK         (PWRGD_PS_PWROK_FF),  \/\/ 100ms delay power-up  \t.FM_SLPS4_N\t\t\t\t(FM_SLPS4_N_FF), \t.FM_PS_EN         \t\t(FM_PS_EN), \t.PWRGD_CPUPWRGD         (PWRGD_CPUPWRGD_FF), \t.RST_PLTRST_N\t\t\t(RST_PLTRST_N_FF),  \t.FM_PS_PWROK_DLY_SEL    (FM_PS_PWROK_DLY_SEL_FF), \t.FM_DIS_PS_PWROK_DLY    (FM_DIS_PS_PWROK_DLY_FF),  \t.FM_ADR_COMPLETE        (FM_ADR_COMPLETE_FF), \t.FM_PLD_PCH_DATA        (FM_PLD_PCH_DATA_FF), \/\/ this logic is not used since need FW support  \t\/\/ output \t.FM_ADR_SMI_GPIO_N      (FM_ADR_SMI_GPIO_N), \t.FM_ADR_TRIGGER_N       (FM_ADR_TRIGGER_N), \t.FM_ADR_COMPLETE_DLY    (FM_ADR_COMPLETE_DLY), \t.PWRGD_PS_PWROK_DLY_ADR (wPWRGD_PS_PWROK_DLY_ADR) );   Mstr_Seq Mstr_Seq_inst ( \t.iClk(iClk_2M),    \/\/ input \t.iRst_n(wRst_n),   \/\/ input \t.iForcePwrOn        (wValidForcePowerOn), \t.iEnableGoOutFltSt (LOW), \/\/disable RP dont need go out fault state. \t.iEnableTimeOut   (LOW), \t.iSysOk (wSysOk), \t\/\/input \t.iDebugPLD_Valid(wDebugPLD_Valid),  \t.iMemPwrgd(wMemPwrgd), \t\/\/ input \t.iMemPwrFlt(wMemPwrFlt),   \/\/ input  \t.iCpuPwrgd(wCpuPwrgd), \t\/\/ input \t.iCpuPwrFlt(wCpuPwrFlt),   \/\/ input  \t.iBmcPwrgd(wBmcPwrgd), \t\/\/ input \t.iBmcPwrFlt(wBmcPwrFlt),   \/\/ input  \t.iPchPwrgd(wPchPwrgd), \t\/\/ input \t.iPchPwrFlt(wPchPwrFlt),   \/\/ input  \t.iPSUPwrgd(wPsuPwrgd), \t\/\/ input \t.iPsuPwrFlt(wPsuPwrFlt),   \/\/ input  \t.iMainVRPwrgd    (wMainVRPwrgd), \/\/input \t.iMainPwrFlt     (wMainPwrFlt),  \/\/input  \t.iSocketRemoved(wSocketRemoved),  \t.PWRGD_P3V3_AUX(PWRGD_P3V3_AUX_FF),    \/\/ input \t.PWRGD_SYS_PWROK(PWRGD_SYS_PWROK),   \t\/\/ input \t.PWRGD_CPUPWRGD(PWRGD_CPUPWRGD_FF),    \/\/ input  \t.FM_BMC_ONCTL_N(FM_BMC_ONCTL_N_LATCH), \/\/ input  \t.FM_SLPS4_N(\t(!FM_PCH_PRSNT_N) ? FM_SLPS4_N_FF \t: wValidForcePowerOn), \/\/ input \t.FM_SLPS3_N(\t(!FM_PCH_PRSNT_N) ? FM_SLPS3_N_FF \t: wValidForcePowerOn), \/\/ input \t.RST_PLTRST_N(\t(!FM_PCH_PRSNT_N) ? RST_PLTRST_N_FF : wValidForcePowerOn), \/\/ input \t.RST_RSMRST_PCH_N(RST_RSMRST_N), \/\/ input \t.RST_SRST_BMC_N(RST_SRST_BMC_PLD_N), \/\/ input  \t.FM_ADR_TRIGGER_N(FM_ADR_TRIGGER_N),  \t.oMemPwrEn(wMemPwrEn), \/\/ output \t.oCpuPwrEn(wCpuPwrEn), \/\/ output \t.oPsuPwrEn(wPsuPwrEn), \/\/ output \t.oMainVRPwrEn(wMainVRPwrEn), \/\/ output  \t.oGoOutFltSt(wGoOutFltSt), \/\/ output \t.oTimeOut(wTimeout),   \/\/ output  \t.oFault(wFault),   \t\/\/ output \t.oPwrEn (wPwrEn), \t\/\/ output  \t.oDbgMstSt7Seg(wDbgMstSt7Seg), \/\/ output [3:0] wDbgMstSt7Seg \t.oDbgMstSt(wDbgMstSt)   \/\/ output [3:0] oDbgMstSt );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/Memhot \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ Memhot mMemhot_CPU1 ( \t.iClk                          (iClk_2M), \t.iRst_n                        (wRst_n), \t\/\/ input \t.PWRGD_SYS_PWROK               (PWRGD_SYS_PWROK), \t.IRQ_PVDDQ_ABCD_VRHOT_LVC3_N   (IRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N_FF), \t.IRQ_PVDDQ_EFGH_VRHOT_LVC3_N   (IRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N_FF), \t.FM_SYS_THROTTLE_LVC3          (FM_SYS_THROTTLE_LVC3_PLD), \t.FM_SKTOCC_LVT3_N              (wFM_CPU1_SKTOCC_LVT3_N), \t\/\/ output \t.FM_MEMHOT_IN                  (FM_CPU1_MEMHOT_IN)\/\/% The logic is inverted using a FET );  Memhot mMemhot_CPU2 ( \t.iClk                          (iClk_2M), \t.iRst_n                        (wRst_n), \t\/\/ input \t.PWRGD_SYS_PWROK               (PWRGD_SYS_PWROK), \t.IRQ_PVDDQ_ABCD_VRHOT_LVC3_N   (IRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N_FF), \t.IRQ_PVDDQ_EFGH_VRHOT_LVC3_N   (IRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N_FF), \t.FM_SYS_THROTTLE_LVC3          (FM_SYS_THROTTLE_LVC3_PLD), \t.FM_SKTOCC_LVT3_N              (wFM_CPU2_SKTOCC_LVT3_N), \t\/\/output \t.FM_MEMHOT_IN                  (FM_CPU2_MEMHOT_IN)\/\/% The logic is inverted using a FET );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/Prochot \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/  Prochot mProchot_CPU1 ( \t.iClk                          (iClk_2M), \t.iRst_n                        (wRst_n), \t.PWRGD_SYS_PWROK               (PWRGD_SYS_PWROK), \t.FM_PVCCIN_PWR_IN_ALERT_N      (FM_PVCCIN_CPU1_PWR_IN_ALERT_N_FF), \t.IRQ_PVCCIN_VRHOT_LVC3_N       (IRQ_PVCCIN_CPU1_VRHOT_LVC3_N_FF), \t.FM_SYS_THROTTLE_LVC3          (FM_SYS_THROTTLE_LVC3_PLD), \t.FM_SKTOCC_LVT3_N              (wFM_CPU1_SKTOCC_LVT3_N), \t\/\/output \t.FM_PROCHOT_LVC3_N             (FM_CPU1_PROCHOT_LVC3_N) );  Prochot mProchot_CPU2 ( \t.iClk                          (iClk_2M), \t.iRst_n                        (wRst_n), \t.PWRGD_SYS_PWROK               (PWRGD_SYS_PWROK), \t.FM_PVCCIN_PWR_IN_ALERT_N      (FM_PVCCIN_CPU2_PWR_IN_ALERT_N_FF), \t.IRQ_PVCCIN_VRHOT_LVC3_N       (IRQ_PVCCIN_CPU2_VRHOT_LVC3_N_FF), \t.FM_SYS_THROTTLE_LVC3          (FM_SYS_THROTTLE_LVC3_PLD), \t.FM_SKTOCC_LVT3_N              (wFM_CPU2_SKTOCC_LVT3_N), \t\/\/output \t.FM_PROCHOT_LVC3_N             (FM_CPU2_PROCHOT_LVC3_N) );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/SmaRT \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ SmaRT mSmaRT ( \t.iClk            (iClk_2M), \t.iRst_n          (wRst_n),  \t.IRQ_SML1_PMBUS_PLD_ALERT_N(IRQ_SML1_PMBUS_PLD_ALERT_N_FF), \t.FM_PMBUS_ALERT_B_EN       (FM_PMBUS_ALERT_B_EN_FF), \t.FM_THROTTLE_N             (FM_THROTTLE_N), \t.PWRGD_SYS_PWROK           (PWRGD_SYS_PWROK), \t\/\/output \t.FM_SYS_THROTTLE_LVC3      (FM_SYS_THROTTLE_LVC3_PLD)\/\/% The logic is inverted using a FET );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/THERMTRIP DLY \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/  \/\/% CPUPWRGD 1.5ms delay SignalValidationDelay# ( \t.VALUE                  ( 1'b1 ), \t.TOTAL_BITS             ( 3'd4 ), \t.POL                    ( 1'b1 ) )mThermTripDly ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( ~wRst_n ), \t.iCE                    ( w500uSCE ), \t.ivMaxCnt               ( 4'd3 ),    \/\/ 500us * 3 = 1.5ms this because thermtrip condition is only valid after 1.5 ms \t.iStart                 ( PWRGD_CPUPWRGD_FF ), \t.oDone                  ( wCPUPwrGd_Dly ) );   thermtrip_dly mthermtrip_dly ( \t.iClk_2M                         (iClk_2M), \t.iRst_n                          (wRst_n), \t.iCpuPwrgdDly                    (wCPUPwrGd_Dly), \t.FM_CPU1_THERMTRIP_LVT3_N        ( !wCPUPwrGd_Dly \t? HIGH : FM_CPU1_THERMTRIP_LVT3_PLD_N_FF), \t.FM_CPU2_THERMTRIP_LVT3_N        ( !wCPUPwrGd_Dly \t? HIGH : FM_CPU2_THERMTRIP_LVT3_PLD_N_FF), \t.FM_MEM_THERM_EVENT_CPU1_LVT3_N  ( !wMemPwrgd_CPU1 \t? HIGH : FM_MEM_THERM_EVENT_CPU1_LVT3_N_FF), \t.FM_MEM_THERM_EVENT_CPU2_LVT3_N  ( !wMemPwrgd_CPU2 \t? HIGH : FM_MEM_THERM_EVENT_CPU2_LVT3_N_FF), \t.FM_CPU2_SKTOCC_LVT3_N           (wFM_CPU2_SKTOCC_LVT3_N), \t\/\/output \t.FM_THERMTRIP_DLY              (FM_THERMTRIP_DLY) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ LED Logic control \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ led_control mled_control( \t.iClk                   (iClk_2M), \t.iRst_n                 (wRst_n),  \t.iPostCodeLed           (wvPOSTCodeLEDs),  \t.iDimmFltLed_CPU1_1     (wvP1DIMMLEDs[7:0]), \t.iDimmFltLed_CPU1_2     (wvP1DIMMLEDs[15:8]), \t.iDimmFltLed_CPU2_1     (wvP2DIMMLEDs[7:0]), \t.iDimmFltLed_CPU2_2     (wvP2DIMMLEDs[15:8]),  \t.iFanFltLed             (wvFanFaultLEDs),  \t.iShowDebug7seg         ( (!FM_PCH_PRSNT_N ? (!RST_PLTRST_N_FF) : 1'b1) || wValidForcePowerOn), \/\/ 7 Segment Support \t.iShowDebugPostCode     ( (!FM_PCH_PRSNT_N ? (!RST_PLTRST_N_FF) : 1'b1) || wValidForcePowerOn), \t.iDebugPostcode         (wvPOSTCodeLEDMux), \/\/change wPostcodeLedMux to wDbgMstSt7Seg for PC  \t.iShowMainVer_N \t\t( wCLK1SCE ), \t.iShowPLDVersion \t\t( FM_PLD_REV_N_FF ),  \t.iByteSeg1_RevMajor \t( wByteSeg1_RevMajor ), \t.iByteSeg2_RevMinor \t( wByteSeg2_RevMinor ),  \t.iByteSeg1              ( wFault ? {3'b000,wFaultStage} : 7'd16 ), \t\/\/ 7 Segment Support (Left Display, value 16 is hypen) \t.iByteSeg2              ( {3'b000,wDbgMstSt7Seg} ), \t\t\t\t\/\/ 7 Segment Support (Right Display)  \t.oLED_CONTROL           (LED_CONTROL),  \t.oFanFlt_Sel_N          (FM_FAN_FAULT_LED_SEL_N), \t.oPostCode_Led_Sel      (FM_POSTLED_SEL),  \t.oDimmFlt_CPU1_1_Led_Sel(FM_CPU1_DIMM_CH1_4_FAULT_LED_SEL), \t.oDimmFlt_CPU1_2_Led_Sel(FM_CPU1_DIMM_CH5_8_FAULT_LED_SEL), \t.oDimmFlt_CPU2_1_Led_Sel(FM_CPU2_DIMM_CH1_4_FAULT_LED_SEL), \t.oDimmFlt_CPU2_2_Led_Sel(FM_CPU2_DIMM_CH5_8_FAULT_LED_SEL),  \t.oPost7Seg1_Sel_N       (FM_POST_7SEG1_SEL_N),  \/\/ 7 Segment Support \t.oPost7Seg2_Sel_N       (FM_POST_7SEG2_SEL_N)   \/\/ 7 Segment Support );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Perst Logic \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ Rst_Perst # (    .NUM_PCIE_SIGNALS (3) \/\/% Number of PCIE resets  ) mRst_Perst ( \t.iClk             (iClk_2M), \/\/System Clock - 2MHz \t.iRst_n           (wRst_n), \/\/System asynchronous reset \t\/\/PERST Table control \t.ivOverride_Enable({~FM_RST_PERST_BIT2,~FM_RST_PERST_BIT1,~FM_RST_PERST_BIT0}), \t.ivOvrValues      ({PWRGD_CPUPWRGD_FF,PWRGD_CPUPWRGD_FF,PWRGD_CPUPWRGD_FF}), \t.ivDefaultValues  ({RST_PLTRST_N_FF,RST_PLTRST_N_FF,RST_PLTRST_N_FF}), \t\/\/Output PCIE Resets for PERST Table \t.ovRstPCIePERst_n ({RST_PCIE_PERST2_N,RST_PCIE_PERST1_N,RST_PCIE_PERST0_N}) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/\/CATERR \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ caterr mCaterr ( \t.iClk_50M                   (iClk_50M),  \t.iCpuPwrgdDly               (wCPUPwrGd_Dly), \t.RST_PLTRST_N               (RST_PLTRST_N_FF), \/\/in This is used as the RESET \t.FM_CPU_CATERR_PLD_LVT3_N   (FM_CPU_CATERR_PLD_LVT3_N),   \/\/in \t.FM_CPU_CATERR_DLY_LVT3_N   (FM_CPU_CATERR_DLY_LVT3_N)    \/\/out );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/eSPI control \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ eSPI_Ctl meSPI_Ctl ( \t.iClk            (iClk_2M), \t.iRst_n          (wRst_n), \t.i1uSCE          (w1uSCE),  \t.RST_SRST_BMC_N  (RST_SRST_BMC_PLD_N), \t.iRsmRst_N       (RST_RSMRST_N), \t.oEspiMuxPCHSel  (FM_PCH_ESPI_MUX_SEL) );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/BMC Workaround \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ onctl_fix mOnctl_fix ( \t.iClk_2M(iClk_2M), \t.iRst_n(wRst_n), \t.FM_BMC_ONCTL_N(FM_BMC_ONCTL_N_FF), \t.FM_SLPS3_N(FM_SLPS3_N_FF ), \t.FM_SLPS4_N(FM_SLPS4_N_FF), \t\/\/.FM_BMC_PWRBTN_OUT_N(FM_BMC_PWRBTN_OUT_N_FF), \t\/\/output \t.FM_BMC_ONCTL_N_LATCH(FM_BMC_ONCTL_N_LATCH) );  assign FP_BMC_PWR_BTN_CO_N = DBP_POWER_BTN_N;  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ BMC Serial GPIO Logic \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/% BMC Serial GPIO expander: Tx - {CPUs  info and CPLDs version} Rx - {Port80 decoded Data} GSX # ( \t.TOTAL_INPUT_MODULES \t( 4'd10 ), \t.TOTAL_OUTPUT_MODULES \t( 4'd10 ) )mGSX ( \t.iGSXDataIn             ( SGPIO_BMC_DOUT ), \t.iGSXClk                ( SGPIO_BMC_CLK ), \t.inGSXLoad              ( SGPIO_BMC_LD_N ), \t.inGSXReset             ( RST_PLTRST_N_FF || wValidForcePowerOn ), \t.ivTxData               ({ \t\t\t\t\t\t\t\t\/\/ First Byte \t\t\t\t\t\t\t\tFM_CPU1_PROC_ID1,        \/\/ SGPIO 7 \t\t\t\t\t\t\t\tFM_CPU1_PROC_ID0,        \/\/ SGPIO 6 \t\t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N_FF,    \/\/ SGPIO 5 \t\t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N_FF,    \/\/ SGPIO 4 \t\t\t\t\t\t\t\t(wCPUPwrGd_Dly &amp;&amp; !wFM_CPU1_SKTOCC_LVT3_N) ? ~FM_CPU1_FIVR_FAULT_LVT3_FF :HIGH,       \/\/ SGPIO 3 \t\t\t\t\t\t\t\tIRQ_PVCCIN_CPU1_VRHOT_LVC3_N_FF,   \/\/ SGPIO 2 \t\t\t\t\t\t\t\twFM_CPU1_THERMTRIP_N,     \/\/ SGPIO 1 \t\t\t\t\t\t\t\twFM_CPU1_SKTOCC_LVT3_N,        \/\/ SGPIO 0  \t\t\t\t\t\t\t\t\/\/ Second Byte \t\t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N_FF,    \/\/ SGPIO 15 \t\t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N_FF,    \/\/ SGPIO 14 \t\t\t\t\t\t\t\t(wCPUPwrGd_Dly &amp;&amp; !wFM_CPU2_SKTOCC_LVT3_N)? ~FM_CPU2_FIVR_FAULT_LVT3_FF :HIGH,            \/\/ SGPIO 13 \t\t\t\t\t\t\t\tIRQ_PVCCIN_CPU2_VRHOT_LVC3_N_FF,   \/\/ SGPIO 12 \t\t\t\t\t\t\t\twFM_CPU2_THERMTRIP_N,     \/\/ SGPIO 11 \t\t\t\t\t\t\t\twFM_CPU2_SKTOCC_LVT3_N,        \/\/ SGPIO 10 \t\t\t\t\t\t\t\t(!wFM_CPU1_SKTOCC_LVT3_N) ? FM_MEM_THERM_EVENT_CPU1_LVT3_N_FF : HIGH,    \/\/ SGPIO 9 \t\t\t\t\t\t\t\twCPUMismatch,           \/\/ SGPIO 8  \t\t\t\t\t\t\t\t\/\/ Third Byte \t\t\t\t\t\t\t\t4'b1111,                \/\/ SGPIO [23:20] - CPU3 info \t\t\t\t\t\t\t\t(!wFM_CPU2_SKTOCC_LVT3_N) ? ~FM_MEM_THERM_EVENT_CPU2_LVT3_N_FF : HIGH,    \/\/ SGPIO 19 \t\t\t\t\t\t\t\twCPUMismatch,           \/\/ SGPIO 18 \t\t\t\t\t\t\t\tFM_CPU2_PROC_ID1,        \/\/ SGPIO 17 \t\t\t\t\t\t\t\tFM_CPU2_PROC_ID0,        \/\/ SGPIO 16  \t\t\t\t\t\t\t\t\/\/ Fourth Byte \t\t\t\t\t\t\t\t8'b11101111,            \/\/ SGPIO [31:24] - CPU3 and CPU4 info  \t\t\t\t\t\t\t\t\/\/ Fifth Byte \t\t\t\t\t\t\t\t8'b10111111,            \/\/ SGPIO [39:32] - CPU4 info  \t\t\t\t\t\t\t\t\/\/ Sixth Byte \t\t\t\t\t\t\t\tFPGA_MINOR_REV,     \/\/ SGPIO [47:40] - Revision code  \t\t\t\t\t\t\t\t \/\/ Seventh Byte \t\t\t\t\t\t\t\tFPGA_MAJOR_REV,\/\/ SGPIO [55:48] - PLD Rev  \t\t\t\t\t\t\t\t \/\/ Eighth Byte \t\t\t\t\t\t\t\t~wPchPwrFlt ,   \/\/ SGPIO63 \t\t\t\t\t\t\t\t1'b1,   \/\/ SGPIO62 \t\t\t\t\t\t\t\t1'b1, \/\/ SGPIO61 \t\t\t\t\t\t\t\t~wPsuPwrFlt,\/\/ SGPIO60 \t\t\t\t\t\t\t\t~wP3v3PwrFlt,\/\/ SGPIO59 \t\t\t\t\t\t\t\t~wCpuPwrFlt_CPU1 &amp;&amp; ~wCpuPwrFlt_CPU2, \/\/ SGPIO58 \t\t\t\t\t\t\t\t~wMemPwrFlt_CPU1 &amp;&amp; ~wMemPwrFlt_CPU2, \/\/ SGPIO57 \t\t\t\t\t\t\t\t1'b0, \/\/ SGPIO56  \t\t\t\t\t\t\t\t\/\/ Nineth Byte \t\t\t\t\t\t\t\t(wCPUPwrGd_Dly &amp;&amp; !wFM_CPU2_SKTOCC_LVT3_N) ? FM_CPU2_MEMTRIP_N_FF :HIGH,          \/\/ SGPIO71 \t\t\t\t\t\t\t\tFM_CPU2_PKGID2,\/\/ SGPIO70 \t\t\t\t\t\t\t\tFM_CPU2_PKGID1,\/\/ SGPIO69 \t\t\t\t\t\t\t\tFM_CPU2_PKGID0,\/\/ SGPIO68 \t\t\t\t\t\t\t\t(wCPUPwrGd_Dly &amp;&amp; !wFM_CPU1_SKTOCC_LVT3_N) ? FM_CPU1_MEMTRIP_N_FF :HIGH,          \/\/ SGPIO67 \t\t\t\t\t\t\t\tFM_CPU1_PKGID2,\/\/ SGPIO66 \t\t\t\t\t\t\t\tFM_CPU1_PKGID1,\/\/ SGPIO65 \t\t\t\t\t\t\t\tFM_CPU1_PKGID0,\/\/ SGPIO64  \t\t\t\t\t\t\t\t\/\/ Tenth Byte \t\t\t\t\t\t\t\t8'hff   \/\/\/ SGPIO [79-72]   PKG CPU3 and CPU4 info \t\t\t\t\t\t\t}), \t.oGSXDataOut            ( SGPIO_BMC_DIN ), \t.ovRxData               ({ \t\t\t\t\t\t\t\t\/\/Pin definition pending \t\t\t\t\t\t\t\twvP4DIMMLEDs[15:12],                   \/\/ 4   76 - 79 \t\t\t\t\t\t\t\twvP3DIMMLEDs[15:12],                   \/\/ 4   72 - 75 \t\t\t\t\t\t\t\twvP2DIMMLEDs[15:12],                   \/\/ 4   68 - 71 \t\t\t\t\t\t\t\twvP1DIMMLEDs[15:12],                   \/\/ 4   64 - 67 \t\t\t\t\t\t\t\twvP4DIMMLEDs[11:0],                   \/\/ 12   52 - 63 \t\t\t\t\t\t\t\twvP3DIMMLEDs[11:0],                   \/\/ 12   40 - 51 \t\t\t\t\t\t\t\twvP2DIMMLEDs[11:0],                   \/\/ 12   28 - 39 \t\t\t\t\t\t\t\twvFanFaultLEDs,                       \/\/ 8    20 - 27 \t\t\t\t\t\t\t\twvP1DIMMLEDs[11:0],                   \/\/ 12   8 - 19 \t\t\t\t\t\t\t\twvPOSTCodeLEDs                        \/\/ 8    0-7 \t\t\t\t\t\t\t\t\/\/ First Byte \t\t\t\t\t\t\t}) );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ THERMTRIP Latcher \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ SingleLatcher# ( \t.EDGELATCH         (1'b0) ) mLatchThermTrip_N_CPU1 ( \t.iClk           \t(iClk_2M ), \t.iRst_n         \t(wRst_n   ),  \t.iEnableLatch    \t(wCPUPwrGd_Dly),\/\/Enable latch \/ \t.iSignalLatch    \t(( wFM_CPU1_SKTOCC_LVT3_N | ~wCPUPwrGd_Dly ) ? 1'b1 :  (FM_CPU1_THERMTRIP_LVT3_PLD_N_FF)),  \t.oSignalLatched  \t(wFM_CPU1_THERMTRIP_N)  );  SingleLatcher# ( \t.EDGELATCH         \t(1'b0) ) mLatchThermTrip_N_CPU2 ( \t.iClk           \t(iClk_2M ), \t.iRst_n         \t(wRst_n   ),  \t.iEnableLatch     \t(wCPUPwrGd_Dly),\/\/Enable latch \/ \t.iSignalLatch     \t(( wFM_CPU2_SKTOCC_LVT3_N | ~wCPUPwrGd_Dly ) ? 1'b1 :  (FM_CPU2_THERMTRIP_LVT3_PLD_N_FF)),  \t.oSignalLatched   \t(wFM_CPU2_THERMTRIP_N)  );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Led Mux Logic \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ assign wInputLEDMux = {         \/\/Signals To measure \t8'hFF,                      \/\/7:0  - register F  \t\/\/ST_PS_OFF \tLOW,                        \/\/7  - register E \tLOW,                        \/\/6  - register E \tLOW,                        \/\/5  - register E \tLOW,                        \/\/4  - register E \tLOW,                        \/\/3  - register E \tLOW,                        \/\/2  - register E \tLOW,                        \/\/1  - register E \tFM_SLPS3_N_FF,              \/\/0  - register E  \t\/\/ST_MAIN_OFF \tLOW,                        \/\/7  - register D \tLOW,                        \/\/6  - register D \tLOW,                        \/\/5  - register D \tLOW,                        \/\/4  - register D \tFM_AUX_SW_EN,               \/\/3  - register D \tPWRGD_PS_PWROK_FF,          \/\/2  - register D \tPWRGD_P3V3_FF,              \/\/1  - register D \tFM_P5V_EN,                  \/\/0  - register D  \t\/\/ST_SHUTDOWN \twDbgCpuSt_CPU2,             \/\/4:7 register C \twDbgCpuSt_CPU1,             \/\/0:3 register C  \t\/\/ST_DONE \tLOW,                        \/\/7  - register B \tLOW,                        \/\/6  - register B \tLOW,                        \/\/5  - register B \tLOW,                        \/\/4  - register B \tLOW,                        \/\/3  - register B \tFM_BMC_ONCTL_N_FF,          \/\/2  - register B \tFM_SLPS3_N_FF,              \/\/1  - register B \tRST_PLTRST_N_FF,            \/\/0  - register B  \t\/\/ST_RESET \tLOW,                        \/\/7  - register A \tLOW,                        \/\/6  - register A \tLOW,                        \/\/5  - register A \tLOW,                        \/\/4  - register A \tLOW,                        \/\/3  - register A \tLOW,                        \/\/2  - register A \tLOW,                        \/\/1  - register A \tRST_PLTRST_N_FF,            \/\/0  - register A  \t\/\/ST_CPUPWRGD \tLOW,                        \/\/7  - register 9 \tLOW,                        \/\/6  - register 9 \tLOW,                        \/\/5  - register 9 \tLOW,                        \/\/4  - register 9 \tLOW,                        \/\/3  - register 9 \tLOW,                        \/\/2  - register 9 \tLOW,                        \/\/1  - register 9 \tPWRGD_CPUPWRGD_FF,          \/\/0  - register 9  \t\/\/ST_SYSPWROK \tLOW,                        \/\/7  - register 8 \twMemPwrgd,                  \/\/6  - register 8 \twCpuPwrgd,                  \/\/5  - register 8 \twBmcPwrgd,                  \/\/4  - register 8 \twPchPwrgd,                  \/\/3  - register 8 \tFM_SLPS3_N_FF,              \/\/2  - register 8 \twPWRGD_PS_PWROK_DLY_ADR,    \/\/1  - register 8 \tDBP_SYSPWROK_FF,            \/\/0  - register 8  \t\/\/ST_CPU \twDbgCpuSt_CPU2,             \/\/4:7 register 7 \twDbgCpuSt_CPU1,             \/\/0:3 register 7  \t\/\/ST_MEM \tLOW,                        \/\/7  - register 6 \twMemPwrEn,                  \/\/6  - register 6 \tPWRGD_CPU2_PVDDQ_EFGH_FF,   \/\/5  - register 6 \tPWRGD_CPU2_PVDDQ_ABCD_FF,   \/\/4  - register 6 \tPWRGD_CPU1_PVDDQ_EFGH_FF,   \/\/3  - register 6 \tPWRGD_CPU1_PVDDQ_ABCD_FF,   \/\/2  - register 6 \tFM_PVPP_CPU2_EN,            \/\/1  - register 6 \tFM_PVPP_CPU1_EN,            \/\/0  - register 6  \t\/\/ST_MAIN \tLOW,                        \/\/7  - register 5 \tLOW,                        \/\/6  - register 5 \tLOW,                        \/\/5  - register 5 \tLOW,                        \/\/4  - register 5 \tFM_AUX_SW_EN,               \/\/3  - register 5 \tPWRGD_PS_PWROK_FF,          \/\/2  - register 5 \tPWRGD_P3V3_FF,              \/\/1  - register 5 \tFM_P5V_EN,                  \/\/0  - register 5  \t\/\/ST_PS \tLOW,                        \/\/7  - register 4 \tLOW,                        \/\/6  - register 4 \tLOW,                        \/\/5  - register 4 \tLOW,                        \/\/4  - register 4 \tLOW,                        \/\/3  - register 4 \tLOW,                        \/\/2  - register 4 \tPWRGD_PS_PWROK_FF,          \/\/1  - register 4 \tFM_PS_EN,                   \/\/0  - register 4  \t\/\/ST_S3 \tFM_PVPP_CPU2_EN,            \/\/7  - register 3 \tFM_PVPP_CPU1_EN,            \/\/6  - register 3 \tPWRGD_CPU2_PVDDQ_EFGH_FF,   \/\/5  - register 3 \tPWRGD_CPU2_PVDDQ_ABCD_FF,   \/\/4  - register 3 \tPWRGD_CPU1_PVDDQ_EFGH_FF,   \/\/3  - register 3 \tPWRGD_CPU1_PVDDQ_ABCD_FF,   \/\/2  - register 3 \tFM_SLPS4_N_FF,              \/\/1  - register 3 \tFM_SLPS3_N_FF,              \/\/0  - register 3  \t\/\/ST_OFF \tFM_CPU2_INTR_PRSNT,         \/\/7  - register 2 \tFM_CPU1_INTR_PRSNT,         \/\/6  - register 2 \tFM_CPU2_SKTOCC_LVT3_N,      \/\/5  - register 2 \tFM_CPU1_SKTOCC_LVT3_N,      \/\/4  - register 2 \twCPUMismatch,               \/\/3  - register 2 \twSysOk,                     \/\/2  - register 2 \tFM_SLPS3_N_FF,              \/\/1  - register 2 \tFM_BMC_ONCTL_N_FF,          \/\/0  - register 2  \t\/\/ST_STBY \tLOW,                        \/\/7  - register 1 \tFM_PCH_PRSNT_N,             \/\/6  - register 1 \tRST_RSMRST_N,               \/\/5  - register 1 \tRST_SRST_BMC_PLD_N,         \/\/4  - register 1 \tPWRGD_P1V1_BMC_AUX_FF,      \/\/3  - register 1 \tPWRGD_P1V05_PCH_AUX_FF,     \/\/2  - register 1 \tPWRGD_P1V8_PCH_AUX_FF,      \/\/1  - register 1 \tPWRGD_P3V3_AUX_FF,          \/\/0  - register 1  \t\/\/ST_FAULT \twFaultState                 \/\/7-0 - register 0 };    Mux128BitsTo8 mLEDMuxy8 ( \t.iSel        (wDbgMstSt), \/\/%Selector this will select what group you need measure. \t.ivSignals   (wInputLEDMux), \t.ovSignals   (wvPOSTCodeLEDMux) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/Fault detection \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ assign wMonitorFaultState= { \t236'd0, \twCpuPwrFltVCCIO_CPU2,       \/\/18 \twCpuPwrFltP1V8_PCIE_CPU2,   \/\/17 \twCpuPwrFltVCCANA_CPU2,      \/\/16 \twCpuPwrFltVCCIN_CPU2,       \/\/15 \twCpuPwrFltVCCSA_CPU2,       \/\/14  \twCpuPwrFltVCCIO_CPU1,       \/\/13 \twCpuPwrFltP1V8_PCIE_CPU1,   \/\/12 \twCpuPwrFltVCCANA_CPU1,      \/\/11 \twCpuPwrFltVCCIN_CPU1,       \/\/10 \twCpuPwrFltVCCSA_CPU1,       \/\/9  \twMemPwrFltVDDQ_CPU2_EFHG,   \/\/8 \twMemPwrFltVDDQ_CPU2_ABCD,   \/\/7  \twMemPwrFltVDDQ_CPU1_EFHG,   \/\/6 \twMemPwrFltVDDQ_CPU1_ABCD,   \/\/5  \twMainPwrFlt,                \/\/4 \twPsuPwrFlt,                 \/\/3 \twPchPwrFltP1V05,            \/\/2 \twPchPwrFltP1V8,             \/\/1 \twBmcPwrFlt                  \/\/0 };   Fault2Code8bits mFault2Code8bits ( \t.iClk       (iClk_2M), \t.iRst_n     (wRst_n), \t.iFaultstate(wMonitorFaultState), \t.i250mSCE   (w250mSCE), \t.iMaxNumberValue(8'd18), \t.oFaultStage(wFaultStage), \t.oFaultState(wFaultState) );  \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/SMBus registers module \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ wire wFilteredSDA, wFilteredSCL; wire [9:0] \twvEvAddr; wire [31:0]\twvEvData; wire       \twEvWE; wire [7:0] wSmbSelLai;   \/\/% SDA Filter GlitchFilter # ( \t.TOTAL_STAGES( 2'd3 ) ) mSDAGlitchFilter ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( !wRst_n ), \t.iCE                    ( 1'b1 ), \t.iSignal                ( SMB_PLD_SDA ), \t.oGlitchlessSignal      ( wFilteredSDA ) ); \/\/ \/\/% SCL Filter \/\/ GlitchFilter # ( \t.TOTAL_STAGES( 2'd3 ) ) mSCLGlitchFilter ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( !wRst_n ), \t.iCE                    ( 1'b1 ), \t.iSignal                ( SMB_PLD_SCL ), \t.oGlitchlessSignal      ( wFilteredSCL ) );  \/\/% SMBus registers module IICRegs# ( \t.MODULE_ADDRESS ( 7'h17 ) )mIICRegs ( \t.iClk               ( iClk_2M ), \t.iRst               ( !wRst_n), \t.iSCL               ( wFilteredSCL ), \t.iSDA               ( wFilteredSDA ), \t.onSDAOE            ( onSDAOE ),  \t.ivSMBusReg00       ({ \t\t\t\t\t\t\t4'b0000,                            \/\/  &lt;Reg|SeqState|RO|0x0000|7:4&gt; \t\t\t\t\t\t\twDbgMstSt7Seg                       \/\/  &lt;Reg|SeqState|RO|0x0000|3:0&gt; - Current power sequencer state \t\t\t\t\t\t}), \t.ivSMBusReg01       ({ \t\t\t\t\t\t\twCPUMismatch,                       \/\/  &lt;Reg|SeqState|RO|0x0001|7&gt; \t\t\t\t\t\t\tFM_CPU1_INTR_PRSNT,                 \/\/  &lt;Reg|SeqState|RO|0x0001|6&gt; \t\t\t\t\t\t\tFM_CPU1_SKTOCC_LVT3_N,              \/\/  &lt;Reg|SeqState|RO|0x0001|5&gt; \t\t\t\t\t\t\tFM_CPU1_PROC_ID1,                   \/\/  &lt;Reg|SeqState|RO|0x0001|4&gt; \t\t\t\t\t\t\tFM_CPU1_PROC_ID0,                   \/\/  &lt;Reg|SeqState|RO|0x0001|3&gt; \t\t\t\t\t\t\tFM_CPU1_PKGID2,                     \/\/  &lt;Reg|SeqState|RO|0x0001|2&gt; \t\t\t\t\t\t\tFM_CPU1_PKGID1,                     \/\/  &lt;Reg|SeqState|RO|0x0001|1&gt; \t\t\t\t\t\t\tFM_CPU1_PKGID0                      \/\/  &lt;Reg|SeqState|RO|0x0001|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg02       ({ \t\t\t\t\t\t\twSysOk,                             \/\/  &lt;Reg|SeqState|RO|0x0002|7&gt; \t\t\t\t\t\t\tFM_CPU2_INTR_PRSNT,                 \/\/  &lt;Reg|SeqState|RO|0x0002|6&gt; \t\t\t\t\t\t\tFM_CPU2_SKTOCC_LVT3_N,              \/\/  &lt;Reg|SeqState|RO|0x0002|5&gt; \t\t\t\t\t\t\tFM_CPU2_PROC_ID1,                   \/\/  &lt;Reg|SeqState|RO|0x0002|4&gt; \t\t\t\t\t\t\tFM_CPU2_PROC_ID0,                   \/\/  &lt;Reg|SeqState|RO|0x0002|3&gt; \t\t\t\t\t\t\tFM_CPU2_PKGID2,                     \/\/  &lt;Reg|SeqState|RO|0x0002|2&gt; \t\t\t\t\t\t\tFM_CPU2_PKGID1,                     \/\/  &lt;Reg|SeqState|RO|0x0002|1&gt; \t\t\t\t\t\t\tFM_CPU2_PKGID0                      \/\/  &lt;Reg|SeqState|RO|0x0002|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg03       ({ \t\t\t\t\t\t\t1'b1,                              \t\/\/  &lt;Reg|SeqState|RO|0x0003|7&gt; \t\t\t\t\t\t\tFM_BMC_ONCTL_N_LATCH,               \/\/  &lt;Reg|SeqState|RO|0x0003|6&gt; \t\t\t\t\t\t\tPWRGD_P3V3_AUX_FF,                  \/\/  &lt;Reg|SeqState|RO|0x0003|5&gt; \t\t\t\t\t\t\tPWRGD_P1V1_BMC_AUX_FF,              \/\/  &lt;Reg|SeqState|RO|0x0003|4&gt; \t\t\t\t\t\t\tFM_P2V5_BMC_EN,                     \/\/  &lt;Reg|SeqState|RO|0x0003|3&gt; \t\t\t\t\t\t\tRST_SRST_BMC_PLD_N,                 \/\/  &lt;Reg|SeqState|RO|0x0003|2&gt; \t\t\t\t\t\t\twBmcPwrgd,                          \/\/  &lt;Reg|SeqState|RO|0x0003|1&gt; \t\t\t\t\t\t\twBmcPwrFlt                          \/\/  &lt;Reg|SeqState|RO|0x0003|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg04       ({ \t\t\t\t\t\t\twValidForcePowerOn,                 \/\/  &lt;Reg|SeqState|RO|0x0004|7&gt; \t\t\t\t\t\t\tFM_PCH_PRSNT_N,                     \/\/  &lt;Reg|SeqState|RO|0x0004|6&gt; \t\t\t\t\t\t\tFM_SLP_SUS_RSM_RST_N_FF,            \/\/  &lt;Reg|SeqState|RO|0x0004|5&gt; \t\t\t\t\t\t\tRST_RSMRST_N,                       \/\/  &lt;Reg|SeqState|RO|0x0004|4&gt; \t\t\t\t\t\t\tFM_SLPS4_N_FF,                      \/\/  &lt;Reg|SeqState|RO|0x0004|3&gt; \t\t\t\t\t\t\tFM_SLPS3_N_FF,                      \/\/  &lt;Reg|SeqState|RO|0x0004|2&gt; \t\t\t\t\t\t\tPWRGD_PCH_PWROK,                    \/\/  &lt;Reg|SeqState|RO|0x0004|1&gt; \t\t\t\t\t\t\tPWRGD_SYS_PWROK                     \/\/  &lt;Reg|SeqState|RO|0x0004|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg05       ({ \t\t\t\t\t\t\twGoOutFltSt,                        \/\/  &lt;Reg|SeqState|RO|0x0005|7&gt; \t\t\t\t\t\t\tPWRGD_P1V8_PCH_AUX_FF,              \/\/  &lt;Reg|SeqState|RO|0x0005|6&gt; \t\t\t\t\t\t\tPWRGD_P1V05_PCH_AUX_FF,             \/\/  &lt;Reg|SeqState|RO|0x0005|5&gt; \t\t\t\t\t\t\tFM_PCH_P1V8_AUX_EN,                 \/\/  &lt;Reg|SeqState|RO|0x0005|4&gt; \t\t\t\t\t\t\twPchPwrFltP1V05,                    \/\/  &lt;Reg|SeqState|RO|0x0005|3&gt; \t\t\t\t\t\t\twPchPwrFltP1V8,                     \/\/  &lt;Reg|SeqState|RO|0x0005|2&gt; \t\t\t\t\t\t\twPchPwrgd,                          \/\/  &lt;Reg|SeqState|RO|0x0005|1&gt; \t\t\t\t\t\t\twPchPwrFlt                          \/\/  &lt;Reg|SeqState|RO|0x0005|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg06       ({ \t\t\t\t\t\t\twPwrEn,                             \/\/  &lt;Reg|SeqState|RO|0x0006|7&gt; \t\t\t\t\t\t\tFM_PS_EN,                           \/\/  &lt;Reg|SeqState|RO|0x0006|6&gt; \t\t\t\t\t\t\tPWRGD_PS_PWROK_FF,                  \/\/  &lt;Reg|SeqState|RO|0x0006|5&gt; \t\t\t\t\t\t\twPsuPwrFlt,                         \/\/  &lt;Reg|SeqState|RO|0x0006|4&gt; \t\t\t\t\t\t\tFM_AUX_SW_EN,                       \/\/  &lt;Reg|SeqState|RO|0x0006|3&gt; \t\t\t\t\t\t\tFM_P5V_EN,                          \/\/  &lt;Reg|SeqState|RO|0x0006|2&gt; \t\t\t\t\t\t\tPWRGD_P3V3_FF,                      \/\/  &lt;Reg|SeqState|RO|0x0006|1&gt; \t\t\t\t\t\t\twMainPwrFlt                         \/\/  &lt;Reg|SeqState|RO|0x0006|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg07       ({ \t\t\t\t\t\t\tFM_PLD_CLKS_OE_N,                   \/\/  &lt;Reg|SeqState|RO|0x0007|7&gt; \t\t\t\t\t\t\t1'b1,                               \/\/  &lt;Reg|SeqState|RO|0x0007|6&gt; \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_ABCD_FF,           \/\/  &lt;Reg|SeqState|RO|0x0007|5&gt; \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_EFGH_FF,           \/\/  &lt;Reg|SeqState|RO|0x0007|4&gt; \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_ABCD_FF,           \/\/  &lt;Reg|SeqState|RO|0x0007|3&gt; \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_EFGH_FF,           \/\/  &lt;Reg|SeqState|RO|0x0007|2&gt; \t\t\t\t\t\t\tFM_PVPP_CPU1_EN,                    \/\/  &lt;Reg|SeqState|RO|0x0007|1&gt; \t\t\t\t\t\t\tFM_PVPP_CPU2_EN                     \/\/  &lt;Reg|SeqState|RO|0x0007|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg08       ({ \t\t\t\t\t\t\twDbgCpuSt_CPU1,                     \/\/  &lt;Reg|SeqState|RO|0x0008|7:4&gt; \t\t\t\t\t\t\twDbgCpuSt_CPU2                      \/\/  &lt;Reg|SeqState|RO|0x0008|3:0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg09       ( wvPOSTCodeLEDs ),                     \/\/  &lt;Reg|BIOSPOST|RO|0x0009|7:0&gt; - BIOS POST Codes \t.ivSMBusReg0A       ( FPGA_MAJOR_REV ),                           \/\/  &lt;Reg|PLD Version|RO|0x000A|7:0&gt; - CPLD1 Version \t.ivSMBusReg0B       ({ \t\t\t\t\t\t\tFM_PS_PWROK_DLY_SEL_FF,             \/\/  &lt;Reg|SeqState|RO|0x000B|7&gt; \t\t\t\t\t\t\tFM_DIS_PS_PWROK_DLY_FF,             \/\/  &lt;Reg|SeqState|RO|0x000B|6&gt; \t\t\t\t\t\t\tFM_ADR_COMPLETE_FF,                 \/\/  &lt;Reg|SeqState|RO|0x000B|5&gt; \t\t\t\t\t\t\tFM_PLD_PCH_DATA,                    \/\/  &lt;Reg|SeqState|RO|0x000B|4&gt; \t\t\t\t\t\t\tFM_ADR_SMI_GPIO_N,                  \/\/  &lt;Reg|SeqState|RO|0x000B|3&gt; \t\t\t\t\t\t\tFM_ADR_TRIGGER_N,                   \/\/  &lt;Reg|SeqState|RO|0x000B|2&gt; \t\t\t\t\t\t\tFM_ADR_COMPLETE_DLY,                \/\/  &lt;Reg|SeqState|RO|0x000B|1&gt; \t\t\t\t\t\t\twPsuPwrFlt                          \/\/  &lt;Reg|SeqState|RO|0x000B|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg0C       ({ \t\t\t\t\t\t\tRST_PLTRST_N_FF,                    \/\/  &lt;Reg|SeqState|RO|0x000C|7&gt; \t\t\t\t\t\t\tFM_CPU1_MEMHOT_IN,                  \/\/  &lt;Reg|SeqState|RO|0x000C|6&gt; \t\t\t\t\t\t\tFM_CPU2_MEMHOT_IN,                  \/\/  &lt;Reg|SeqState|RO|0x000C|5&gt; \t\t\t\t\t\t\tFM_CPU1_PROCHOT_LVC3_N,             \/\/  &lt;Reg|SeqState|RO|0x000C|4&gt; \t\t\t\t\t\t\tFM_CPU2_PROCHOT_LVC3_N,             \/\/  &lt;Reg|SeqState|RO|0x000C|3&gt; \t\t\t\t\t\t\tFM_SYS_THROTTLE_LVC3_PLD,           \/\/  &lt;Reg|SeqState|RO|0x000C|2&gt; \t\t\t\t\t\t\tFM_THERMTRIP_DLY,                   \/\/  &lt;Reg|SeqState|RO|0x000C|1&gt; \t\t\t\t\t\t\twvEvAddr[9]                         \/\/  &lt;Reg|EvLoggerEvents|RO|0x000C|0&gt; - Event Logger Events Count MSB \t\t\t\t\t\t  } ), \t.ivSMBusReg0D       ( wvEvAddr[8:1] ),                      \/\/  &lt;Reg|EvLoggerEvents|RO|0x000D|7:0&gt; - Event Logger Events Count LSB \t.ivSMBusReg0E       (FPGA_MINOR_REV ),                       \/\/  &lt;Reg|CPLD1Version|RO|0x000E|7:0&gt; - PLD Version Test number \t.ivSMBusReg0F       ({ \t\t\t\t\t\t\twFM_CPU1_THERMTRIP_N,               \/\/  &lt;Reg|SeqState|RO|0x000F|7&gt; \t\t\t\t\t\t\twFM_CPU2_THERMTRIP_N,               \/\/  &lt;Reg|SeqState|RO|0x000F|6&gt; \t\t\t\t\t\t\tFM_CPU1_THERMTRIP_LVT3_PLD_N_FF,    \/\/  &lt;Reg|SeqState|RO|0x000F|5&gt; \t\t\t\t\t\t\tFM_CPU2_THERMTRIP_LVT3_PLD_N_FF,    \/\/  &lt;Reg|SeqState|RO|0x000F|4&gt; \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU1_LVT3_N_FF,  \/\/  &lt;Reg|SeqState|RO|0x000F|3&gt; \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU2_LVT3_N_FF,  \/\/  &lt;Reg|SeqState|RO|0x000F|2&gt; \t\t\t\t\t\t\tIRQ_SML1_PMBUS_PLD_ALERT_N_FF,      \/\/  &lt;Reg|SeqState|RO|0x000F|1&gt; \t\t\t\t\t\t\tFM_PMBUS_ALERT_B_EN_FF              \/\/  &lt;Reg|SeqState|RO|0x000F|0&gt; \t\t\t\t\t\t}),  \t.ovSMBusReg30       ({ \t\t\t\t\t\t\twSmbSelLai                          \/\/   &lt;Reg|StepControl|RW|0x0010|7:0&gt; \t\t\t\t\t\t}),  \t\/\/ &lt;Reg|EventLoggerStart|RO|0x1000|7:0&gt; \t\/\/ &lt;Reg|EventLoggerEnd|RO|0x1FFF|7:0&gt; \t.ivEventsAddress    ( wvEvAddr ), \t.iEventsWE          ( wEvWE ), \t.ivEventsInData     ( wvEvData ), \t.iEvRst             ( !wRst_n ) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ Event Logger \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ EventLogger mEventLogger ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( !wRst_n ), \t.iSample                ( w1uSCE ), \t.ivInputs               ({ \t\t\t\t\t\t\t\tRST_PLTRST_N_FF,            \/\/31 \t\t\t\t\t\t\t\tPWRGD_CPUPWRGD_FF,          \/\/30 \t\t\t\t\t\t\t\tPWRGD_SYS_PWROK,            \/\/29 \t\t\t\t\t\t\t\tPWRGD_PCH_PWROK,            \/\/28  \t\t\t\t\t\t\t\tPWRGD_PVCCSA_CPU2_FF,       \/\/27 \t\t\t\t\t\t\t\tPWRGD_PVCCIN_CPU2_FF,       \/\/26 \t\t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU2_FF,  \/\/25 \t\t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU2_FF,    \/\/24 \t\t\t\t\t\t\t\tPWRGD_PVCCIO_CPU2_FF,       \/\/23  \t\t\t\t\t\t\t\tPWRGD_PVCCSA_CPU1_FF,       \/\/22 \t\t\t\t\t\t\t\tPWRGD_PVCCIN_CPU1_FF,       \/\/21 \t\t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU1_FF,  \/\/20 \t\t\t\t\t\t\t\tPWRGD_BIAS_P1V1_FF,         \/\/19 \t\t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU1_FF,    \/\/18 \t\t\t\t\t\t\t\twPWRGD_PVCCIO_CPU1,         \/\/17  \t\t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_ABCD_FF,   \/\/16 \t\t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_ABCD_FF,   \/\/15  \t\t\t\t\t\t\t\tFM_PLD_CLKS_OE_N,           \/\/14  \t\t\t\t\t\t\t\tFM_AUX_SW_EN,               \/\/13 \t\t\t\t\t\t\t\tPWRGD_P3V3_FF,              \/\/12  \t\t\t\t\t\t\t\tPWRGD_PS_PWROK_FF,          \/\/11  \t\t\t\t\t\t\t\tFM_BMC_ONCTL_N_LATCH,       \/\/10 \t\t\t\t\t\t\t\tFM_SLPS3_N_FF,              \/\/9 \t\t\t\t\t\t\t\tFM_SLPS4_N_FF,              \/\/8 \t\t\t\t\t\t\t\t\/\/------------------  \t\t\t\t\t\t\t\tRST_RSMRST_N,               \/\/-7 \t\t\t\t\t\t\t\tRST_SRST_BMC_PLD_N,         \/\/-6  \t\t\t\t\t\t\t\tPWRGD_P1V05_PCH_AUX_FF,     \/\/-5 \t\t\t\t\t\t\t\tPWRGD_P1V1_BMC_AUX_FF,      \/\/-4  \t\t\t\t\t\t\t\tPWRGD_P1V8_PCH_AUX_FF,      \/\/3 \t\t\t\t\t\t\t\tPWRGD_P3V3_AUX_FF,          \/\/ -2 \t\t\t\t\t\t\t\tFM_SLP_SUS_RSM_RST_N_FF,    \/\/ - 1 \t\t\t\t\t\t\t\twSysOk                      \/\/ - 0  \t\t\t\t\t\t\t}), \t.ovAddress              ( wvEvAddr ), \t.ovData                 ( wvEvData ), \t.oWE                    ( wEvWE ) );  wire wRST_DEDI_BUSY_PLD_N;   SignalValidationDelay# ( \t.VALUE                  ( 1'b1 ), \t.TOTAL_BITS             ( 4'd6 ), \t.POL                    ( 1'b1 ) ) mRSMRST_Delay_Dedi ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( ~wRst_n), \t.iCE                    ( w10uSCE ), \t.ivMaxCnt               ( 6'd49 ),        \/\/500us delay \t.iStart                 ( wRSMRST_N ), \t.oDone                  ( wRSMRST_Delay_Dedi ) );  SignalValidationDelay# ( \t.VALUE                  ( 1'b0 ), \t.TOTAL_BITS             ( 3'd2 ), \t.POL                    ( 1'b0 ) ) mRST_DEDI_BUSY_PLD_N ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( ~wRst_n), \t.iCE                    ( w1uSCE ), \t.ivMaxCnt               ( 3'd2 ),        \/\/2us delay \t.iStart                 ( RST_DEDI_BUSY_PLD_N ), \t.oDone                  ( wRST_DEDI_BUSY_PLD_N ) );   \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/ DEBUG GSX PORT - Communication for Debug (Secondary) PLD \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ wire [7:0] wGSX_From_DebugPLD;  GSX_Master # ( \t.TOTAL_OUTPUT_MODULES( 2'd3 ) ) mGSX_Master ( \t.iClk(iClk_2M),         \/\/% 2MHz Reference Clock \t.iCE(w5uSCE),           \/\/% Chip enable to generate oSClock. 10uS to generate 100KHz SClock \t.iReset(wRst_n),        \/\/% Input reset.  \t.oSClock    (SGPIO_DEBUG_PLD_CLK),   \t\/\/% Output clock. \t.oSLoad     (SGPIO_DEBUG_PLD_LD_N),   \t\/\/% Output Last clock of a bit stream; begin a new bit stream on the next clock. \t.oSDataOut  (SGPIO_DEBUG_PLD_DOUT),   \t\/\/% Input serial data bit stream. \t.iSDataIn   (SGPIO_DEBUG_PLD_DIN),   \t\/\/% Output serial data bit stream. \t.ovDataIn( { \t\t\t\t\t\/\/Third Byte \t\t\t\t\twGSX_From_DebugPLD[7:0],\t\t\t\/\/8\t\t23:16 - Spare from Debug (0xAA)  \t\t\t\t\t\/\/ Second Byte \t\t\t\t\tFPGA_REV_Minor_DebugPLD,           \t\/\/ 8    15-8  \t\t\t\t\t\/\/ First Byte \t\t\t\t\tFPGA_REV_Major_DebugPLD          \t\/\/ 8    0-7 \t\t\t\t} ),     \t\t\/\/% Data receive vector. Master receives using DataIn. At Modular PPO baseboard, no data is pretended to be received from Global PLD \t.ivDataOut( {\t\/\/Debug PLD is not intended to receive data from Main PLD, however misc data is set to test \t\t\t\t\t8'h80,  \t\/\/ SGPIO [23:16]      - Third byte \t\t\t\t\t8'h86,  \t\/\/ SGPIO [15:8]       - Second Byte \t\t\t\t\t8'hAA   \t\/\/ SGPIO [7:0]        - First Byte \t\t\t\t} )     \/\/% Data transmit vector. Master transmits using DataOut );   `ifdef dedicated_debug_logic \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ \/\/SMBus registers module - Dedicated Debug Port \/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/\/ wire wDedicatedFilteredSDA, wDedicatedFilteredSCL;  \/\/% SDA Filter GlitchFilter # ( \t.TOTAL_STAGES( 2'd3 ) ) mSDAGlitchFilter_Dedicated ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( !wRst_n ), \t.iCE                    ( 1'b1 ), \t.iSignal                ( SMB_DEBUG_PLD_SDA ), \t.oGlitchlessSignal      ( wDedicatedFilteredSDA ) ); \/\/ \/\/% SCL Filter \/\/ GlitchFilter # ( \t.TOTAL_STAGES( 2'd3 ) ) mSCLGlitchFilter_Dedicated ( \t.iClk                   ( iClk_2M ), \t.iRst                   ( !wRst_n ), \t.iCE                    ( 1'b1 ), \t.iSignal                ( SMB_DEBUG_PLD_SCL ), \t.oGlitchlessSignal      ( wDedicatedFilteredSCL ) );  \/\/% SMBus registers module IICRegs# ( \t.MODULE_ADDRESS ( 7'h17 ) )mIICRegs_Dedicated ( \t.iClk               ( iClk_2M ), \t.iRst               ( !wRst_n), \t.iSCL               ( wDedicatedFilteredSCL ), \t.iSDA               ( wDedicatedFilteredSDA ), \t.onSDAOE            ( oSMB_DEBUG_PLD_SDA_OE ),  \t.ivSMBusReg00       ({ \t\t\t\t\t\t\t4'b0000,\t\t\t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0000|7:4&gt; \t\t\t\t\t\t\twDbgMstSt7Seg\t\t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0000|3:0&gt; - Current power sequencer state \t\t\t\t\t\t}), \t.ivSMBusReg01       ({ \t\t\t\t\t\t\twCPUMismatch,         \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|7&gt; \t\t\t\t\t\t\tFM_CPU1_INTR_PRSNT,   \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|6&gt; \t\t\t\t\t\t\tFM_CPU1_SKTOCC_LVT3_N,\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|5&gt; \t\t\t\t\t\t\tFM_CPU1_PROC_ID1,     \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|4&gt; \t\t\t\t\t\t\tFM_CPU1_PROC_ID0,     \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|3&gt; \t\t\t\t\t\t\tFM_CPU1_PKGID2,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|2&gt; \t\t\t\t\t\t\tFM_CPU1_PKGID1,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|1&gt; \t\t\t\t\t\t\tFM_CPU1_PKGID0        \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0001|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg02       ({ \t\t\t\t\t\t\twSysOk,               \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|7&gt; \t\t\t\t\t\t\tFM_CPU2_INTR_PRSNT,   \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|6&gt; \t\t\t\t\t\t\tFM_CPU2_SKTOCC_LVT3_N,\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|5&gt; \t\t\t\t\t\t\tFM_CPU2_PROC_ID1,     \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|4&gt; \t\t\t\t\t\t\tFM_CPU2_PROC_ID0,     \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|3&gt; \t\t\t\t\t\t\tFM_CPU2_PKGID2,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|2&gt; \t\t\t\t\t\t\tFM_CPU2_PKGID1,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|1&gt; \t\t\t\t\t\t\tFM_CPU2_PKGID0        \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0002|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg03       ({ \t\t\t\t\t\t\t1'b1,                 \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|7&gt; \t\t\t\t\t\t\tFM_BMC_ONCTL_N_LATCH, \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|6&gt; \t\t\t\t\t\t\tPWRGD_P3V3_AUX_FF,    \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|5&gt; \t\t\t\t\t\t\tPWRGD_P1V1_BMC_AUX_FF,\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|4&gt; \t\t\t\t\t\t\tFM_P2V5_BMC_EN,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|3&gt; \t\t\t\t\t\t\tRST_SRST_BMC_PLD_N,   \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|2&gt; \t\t\t\t\t\t\twBmcPwrgd,            \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|1&gt; \t\t\t\t\t\t\twBmcPwrFlt            \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0003|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg04       ({ \t\t\t\t\t\t\twValidForcePowerOn,     \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|7&gt; \t\t\t\t\t\t\tFM_PCH_PRSNT_N,         \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|6&gt; \t\t\t\t\t\t\tFM_SLP_SUS_RSM_RST_N_FF,\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|5&gt; \t\t\t\t\t\t\tRST_RSMRST_N,           \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|4&gt; \t\t\t\t\t\t\tFM_SLPS4_N_FF,          \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|3&gt; \t\t\t\t\t\t\tFM_SLPS3_N_FF,          \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|2&gt; \t\t\t\t\t\t\tPWRGD_PCH_PWROK,        \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|1&gt; \t\t\t\t\t\t\tPWRGD_SYS_PWROK         \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0004|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg05       ({ \t\t\t\t\t\t\twGoOutFltSt,           \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|7&gt; \t\t\t\t\t\t\tPWRGD_P1V8_PCH_AUX_FF, \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|6&gt; \t\t\t\t\t\t\tPWRGD_P1V05_PCH_AUX_FF,\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|5&gt; \t\t\t\t\t\t\tFM_PCH_P1V8_AUX_EN,    \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|4&gt; \t\t\t\t\t\t\twPchPwrFltP1V05,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|3&gt; \t\t\t\t\t\t\twPchPwrFltP1V8,        \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|2&gt; \t\t\t\t\t\t\twPchPwrgd,             \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|1&gt; \t\t\t\t\t\t\twPchPwrFlt             \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0005|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg06       ({ \t\t\t\t\t\t\twPwrEn,           \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|7&gt; \t\t\t\t\t\t\tFM_PS_EN,         \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|6&gt; \t\t\t\t\t\t\tPWRGD_PS_PWROK_FF,\t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|5&gt; \t\t\t\t\t\t\twPsuPwrFlt,       \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|4&gt; \t\t\t\t\t\t\tFM_AUX_SW_EN,     \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|3&gt; \t\t\t\t\t\t\tFM_P5V_EN,        \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|2&gt; \t\t\t\t\t\t\tPWRGD_P3V3_FF,    \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|1&gt; \t\t\t\t\t\t\twMainPwrFlt       \t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0006|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg07       ({ \t\t\t\t\t\t\tFM_PLD_CLKS_OE_N,        \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|7&gt; \t\t\t\t\t\t\t1'b1,                    \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|6&gt; \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_ABCD_FF,\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|5&gt; \t\t\t\t\t\t\tPWRGD_CPU1_PVDDQ_EFGH_FF,\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|4&gt; \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_ABCD_FF,\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|3&gt; \t\t\t\t\t\t\tPWRGD_CPU2_PVDDQ_EFGH_FF,\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|2&gt; \t\t\t\t\t\t\tFM_PVPP_CPU1_EN,         \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|1&gt; \t\t\t\t\t\t\tFM_PVPP_CPU2_EN          \t\t\t\/\/  &lt;Reg|SeqState|RO|0x0007|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg08       ({ \t\t\t\t\t\t\twDbgCpuSt_CPU1,\t\t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0008|7:4&gt; \t\t\t\t\t\t\twDbgCpuSt_CPU2 \t\t\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x0008|3:0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg09       ( wvPOSTCodeLEDs ),\t\t\t\t\t\t\/\/  &lt;Reg|BIOSPOST|RO|0x0009|7:0&gt; - BIOS POST Codes \t.ivSMBusReg0A       ( FPGA_MAJOR_REV ),   \t\t\t\t\t\/\/  &lt;Reg|PLD Version|RO|0x000A|7:0&gt; - CPLD1 Version \t.ivSMBusReg0B       ({ \t\t\t\t\t\t\tFM_PS_PWROK_DLY_SEL_FF,\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|7&gt; \t\t\t\t\t\t\tFM_DIS_PS_PWROK_DLY_FF,\t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|6&gt; \t\t\t\t\t\t\tFM_ADR_COMPLETE_FF,    \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|5&gt; \t\t\t\t\t\t\tFM_PLD_PCH_DATA,       \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|4&gt; \t\t\t\t\t\t\tFM_ADR_SMI_GPIO_N,     \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|3&gt; \t\t\t\t\t\t\tFM_ADR_TRIGGER_N,      \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|2&gt; \t\t\t\t\t\t\tFM_ADR_COMPLETE_DLY,   \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|1&gt; \t\t\t\t\t\t\twPsuPwrFlt             \t\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000B|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg0C       ({ \t\t\t\t\t\t\tRST_PLTRST_N_FF,         \t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|7&gt; \t\t\t\t\t\t\tFM_CPU1_MEMHOT_IN,       \t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|6&gt; \t\t\t\t\t\t\tFM_CPU2_MEMHOT_IN,       \t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|5&gt; \t\t\t\t\t\t\tFM_CPU1_PROCHOT_LVC3_N,  \t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|4&gt; \t\t\t\t\t\t\tFM_CPU2_PROCHOT_LVC3_N,  \t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|3&gt; \t\t\t\t\t\t\tFM_SYS_THROTTLE_LVC3_PLD,\t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|2&gt; \t\t\t\t\t\t\tFM_THERMTRIP_DLY,        \t\t\t\/\/  &lt;Reg|SeqState|RO|0x000C|1&gt; \t\t\t\t\t\t\twvEvAddr[9]              \t\t\t\/\/  &lt;Reg|EvLoggerEvents|RO|0x000C|0&gt; - Event Logger Events Count MSB \t\t\t\t\t\t  } ), \t.ivSMBusReg0D       ( wvEvAddr[8:1] ),                      \/\/  &lt;Reg|EvLoggerEvents|RO|0x000D|7:0&gt; - Event Logger Events Count LSB \t.ivSMBusReg0E       ( FPGA_MINOR_REV ),                    \t\/\/  &lt;Reg|CPLD1Version|RO|0x000E|7:0&gt; - PLD Version Test number \t.ivSMBusReg0F       ({ \t\t\t\t\t\t\twFM_CPU1_THERMTRIP_N,               \/\/  &lt;Reg|SeqState|RO|0x000F|7&gt; \t\t\t\t\t\t\twFM_CPU2_THERMTRIP_N,               \/\/  &lt;Reg|SeqState|RO|0x000F|6&gt; \t\t\t\t\t\t\tFM_CPU1_THERMTRIP_LVT3_PLD_N_FF,    \/\/  &lt;Reg|SeqState|RO|0x000F|5&gt; \t\t\t\t\t\t\tFM_CPU2_THERMTRIP_LVT3_PLD_N_FF,    \/\/  &lt;Reg|SeqState|RO|0x000F|4&gt; \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU1_LVT3_N_FF,  \/\/  &lt;Reg|SeqState|RO|0x000F|3&gt; \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU2_LVT3_N_FF,  \/\/  &lt;Reg|SeqState|RO|0x000F|2&gt; \t\t\t\t\t\t\tIRQ_SML1_PMBUS_PLD_ALERT_N_FF,      \/\/  &lt;Reg|SeqState|RO|0x000F|1&gt; \t\t\t\t\t\t\tFM_PMBUS_ALERT_B_EN_FF              \/\/  &lt;Reg|SeqState|RO|0x000F|0&gt; \t\t\t\t\t\t}), \t.ivSMBusReg10       ({ \t\t\t\t\t\t\tFM_P1V1_EN, \t\t\t\t\t\t\tFM_P1V8_PCIE_CPU1_EN, \t\t\t\t\t\t\tFM_PVCCANA_CPU1_EN, \t\t\t\t\t\t\tFM_PVCCIN_CPU1_EN, \t\t\t\t\t\t\tFM_PVCCIO_CPU1_EN, \t\t\t\t\t\t\tFM_PVCCSA_CPU1_EN, \t\t\t\t\t\t\tFM_CPU1_FIVR_FAULT_LVT3, \t\t\t\t\t\t\t1'b1 \t\t\t\t\t\t}), \t.ivSMBusReg11       ({ \t\t\t\t\t\t\tPWRGD_BIAS_P1V1, \t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU1, \t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU1, \t\t\t\t\t\t\tPWRGD_PVCCIN_CPU1, \t\t\t\t\t\t\tPWRGD_PVCCIO_CPU1, \t\t\t\t\t\t\tPWRGD_PVCCSA_CPU1, \t\t\t\t\t\t\tPWRGD_CPU1_LVC3, \t\t\t\t\t\t\t1'b1 \t\t\t\t\t\t}), \t.ivSMBusReg12       ({ \t\t\t\t\t\t\tFM_PVCCIN_CPU1_PWR_IN_ALERT_N, \t\t\t\t\t\t\tIRQ_PVCCIN_CPU1_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU1_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU1_VRHOT_LVC3_N, \t\t\t\t\t\t\tFM_CPU1_MEMTRIP_N, \t\t\t\t\t\t\twFM_CPU1_THERMTRIP_N, \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU1_LVT3_N, \t\t\t\t\t\t\tRST_CPU1_LVC3_N \t\t\t\t\t\t}), \t.ivSMBusReg13       ({ \t\t\t\t\t\t\twCpuPwrgd_CPU1, \t\t\t\t\t\t\twCpuPwrFlt_CPU1, \t\t\t\t\t\t\twPWRGD_PVCCIO_CPU1, \t\t\t\t\t\t\twCpuPwrFltVCCIO_CPU1, \t\t\t\t\t\t\twCpuPwrFltP1V8_PCIE_CPU1, \t\t\t\t\t\t\twCpuPwrFltVCCANA_CPU1, \t\t\t\t\t\t\twCpuPwrFltVCCIN_CPU1, \t\t\t\t\t\t\twCpuPwrFltVCCSA_CPU1 \t\t\t\t\t\t}), \t.ivSMBusReg14       ({ \t\t\t\t\t\t\twMemPwrFltVDDQ_CPU1_ABCD, \t\t\t\t\t\t\twMemPwrFltVDDQ_CPU1_EFHG, \t\t\t\t\t\t\twMemPwrFlt_CPU1, \t\t\t\t\t\t\twMemPwrgd_CPU1, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1 \t\t\t\t\t\t}), \t.ivSMBusReg15       ({ \t\t\t\t\t\t\tFM_P1V8_PCIE_CPU2_EN, \t\t\t\t\t\t\tFM_PVCCANA_CPU2_EN, \t\t\t\t\t\t\tFM_PVCCIN_CPU2_EN, \t\t\t\t\t\t\tFM_PVCCIO_CPU2_EN, \t\t\t\t\t\t\tFM_PVCCSA_CPU2_EN, \t\t\t\t\t\t\tFM_CPU2_FIVR_FAULT_LVT3, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1 \t\t\t\t\t\t}), \t.ivSMBusReg16       ({ \t\t\t\t\t\t\tPWRGD_P1V8_PCIE_CPU2, \t\t\t\t\t\t\tPWRGD_VCCANA_PCIE_CPU2, \t\t\t\t\t\t\tPWRGD_PVCCIN_CPU2, \t\t\t\t\t\t\tPWRGD_PVCCIO_CPU2, \t\t\t\t\t\t\tPWRGD_PVCCSA_CPU2, \t\t\t\t\t\t\tPWRGD_CPU2_LVC3, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1 \t\t\t\t\t\t}), \t.ivSMBusReg17       ({ \t\t\t\t\t\t\tFM_PVCCIN_CPU2_PWR_IN_ALERT_N, \t\t\t\t\t\t\tIRQ_PVCCIN_CPU2_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_ABCD_CPU2_VRHOT_LVC3_N, \t\t\t\t\t\t\tIRQ_PVDDQ_EFGH_CPU2_VRHOT_LVC3_N, \t\t\t\t\t\t\tFM_CPU2_MEMTRIP_N, \t\t\t\t\t\t\twFM_CPU2_THERMTRIP_N, \t\t\t\t\t\t\tFM_MEM_THERM_EVENT_CPU2_LVT3_N, \t\t\t\t\t\t\tRST_CPU2_LVC3_N \t\t\t\t\t\t}), \t.ivSMBusReg18       ({ \t\t\t\t\t\t\twCpuPwrgd_CPU2, \t\t\t\t\t\t\twCpuPwrFlt_CPU2, \t\t\t\t\t\t\twFM_PVCCIO_CPU2_EN, \t\t\t\t\t\t\twCpuPwrFltVCCIO_CPU2, \t\t\t\t\t\t\twCpuPwrFltP1V8_PCIE_CPU2, \t\t\t\t\t\t\twCpuPwrFltVCCANA_CPU2, \t\t\t\t\t\t\twCpuPwrFltVCCIN_CPU2, \t\t\t\t\t\t\twCpuPwrFltVCCSA_CPU2 \t\t\t\t\t\t}), \t.ivSMBusReg19       ({ \t\t\t\t\t\t\twMemPwrFltVDDQ_CPU2_ABCD, \t\t\t\t\t\t\twMemPwrFltVDDQ_CPU2_EFHG, \t\t\t\t\t\t\twMemPwrFlt_CPU2, \t\t\t\t\t\t\twMemPwrgd_CPU2, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1, \t\t\t\t\t\t\t1'b1 \t\t\t\t\t\t}), \t.ivSMBusReg1A       ({ \t\t\t\t\t\t\tFM_RST_PERST_BIT0, \t\t\t\t\t\t\tFM_RST_PERST_BIT1, \t\t\t\t\t\t\tFM_RST_PERST_BIT2, \t\t\t\t\t\t\tRST_PCIE_PERST0_N, \t\t\t\t\t\t\tRST_PCIE_PERST1_N, \t\t\t\t\t\t\tRST_PCIE_PERST2_N, \t\t\t\t\t\t\tRST_PLTRST_B_N, \t\t\t\t\t\t\tPWRGD_CPUPWRGD \t\t\t\t\t\t}), \t.ivSMBusReg1B       ({ \t\t\t\t\t\t\tRST_PLTRST_N, \t\t\t\t\t\t\tFM_CPU_CATERR_DLY_LVT3_N, \t\t\t\t\t\t\tFM_CPU_CATERR_PLD_LVT3_N, \t\t\t\t\t\t\tFM_PCH_ESPI_MUX_SEL, \t\t\t\t\t\t\tPWRGD_DRAMPWRGD_CPU, \t\t\t\t\t\t\tFM_THROTTLE_N, \t\t\t\t\t\t\tDBP_POWER_BTN_N, \t\t\t\t\t\t\tDBP_SYSPWROK \t\t\t\t\t\t}), \t.ivSMBusReg1C       ({ \t\t\t\t\t\t\tFM_PFR_MUX_OE_CTL_PLD, \t\t\t\t\t\t\tRST_DEDI_BUSY_PLD_N, \t\t\t\t\t\t\t1'b0, \t\t\t\t\t\t\tFM_CPU_BCLK5_OE_R_N, \t\t\t\t\t\t\tFM_PLD_CLKS_OE_N, \t\t\t\t\t\t\tFM_P5V_EN, \t\t\t\t\t\t\tFM_AUX_SW_EN, \t\t\t\t\t\t\tFP_LED_FAN_FAULT_PWRSTBY_PLD_N \t\t\t\t\t\t}), \t.ivSMBusReg1D       ({ \t\t\t\t\t\t\twPwrEn, \t\t\t\t\t\t\twPsuPwrEn, \t\t\t\t\t\t\twFM_P5V_EN, \t\t\t\t\t\t\twMainVRPwrEn, \t\t\t\t\t\t\twFM_AUX_SW_EN, \t\t\t\t\t\t\twMemPwrEn, \t\t\t\t\t\t\twCpuPwrEn, \t\t\t\t\t\t\twP3v3PwrFlt \t\t\t\t\t\t}), \t.ivSMBusReg1E       ({ \t\t\t\t\t\t\twPchPwrFltP1V8, \t\t\t\t\t\t\twPchPwrFltP1V05, \t\t\t\t\t\t\twPchPwrFlt, \t\t\t\t\t\t\twBmcPwrFlt, \t\t\t\t\t\t\twPsuPwrFlt, \t\t\t\t\t\t\twMainPwrFlt, \t\t\t\t\t\t\twMemPwrFlt, \t\t\t\t\t\t\twCpuPwrFlt \t\t\t\t\t\t}), \t.ivSMBusReg1F       ({ \t\t\t\t\t\t\twPsuPwrgd, \t\t\t\t\t\t\twPchPwrgd, \t\t\t\t\t\t\twBmcPwrgd, \t\t\t\t\t\t\twMainVRPwrgd, \t\t\t\t\t\t\twMemPwrgd, \t\t\t\t\t\t\twCpuPwrgd, \t\t\t\t\t\t\twFault, \t\t\t\t\t\t\twTimeout \t\t\t\t\t\t}),  \t.ivSMBusReg20       ({ \t\t\t\t\t\t\tFPGA_REV_Major_DebugPLD \t\t\t\t\t\t}),\/\/  &lt;Reg|MiscVal|RO|0x0020|7:0&gt; \t.ivSMBusReg21       ({ \t\t\t\t\t\t\tFPGA_REV_Minor_DebugPLD \t\t\t\t\t\t}),\/\/  &lt;Reg|MiscVal|RO|0x0021|7:0&gt; \t.ivSMBusReg22       ({ \t\t\t\t\t\t\t7'd0, \t\t\t\t\t\t\twDebugPLD_Valid \t\t\t\t\t\t}),\/\/  &lt;Reg|MiscVal|RO|0x0022|7:0&gt;  \t.ivSMBusReg23       ( 8'hAA ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0023|7:0&gt; \t.ivSMBusReg24       ( 8'h24 ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0024|7:0&gt; \t.ivSMBusReg25       ( 8'hAA ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0025|7:0&gt; \t.ivSMBusReg26       ( 8'h26 ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0026|7:0&gt; \t.ivSMBusReg27       ( 8'hAA ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0027|7:0&gt; \t.ivSMBusReg28       ( 8'h28 ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0028|7:0&gt; \t.ivSMBusReg29       ( 8'hAA ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x0029|7:0&gt; \t.ivSMBusReg2A       ( 8'h2A ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x002A|7:0&gt; \t.ivSMBusReg2B       ( 8'hAA ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x002B|7:0&gt; \t.ivSMBusReg2C       ( 8'h2C ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x002C|7:0&gt; \t.ivSMBusReg2D       ( 8'hAA ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x002D|7:0&gt; \t.ivSMBusReg2E       ( 8'h2E ),          \t\t\/\/  &lt;Reg|MiscVal|RO|0x002E|7:0&gt; \t.ivSMBusReg2F       ( 8'hAA )                 \t\/\/  &lt;Reg|MiscVal|RO|0x002F|7:0&gt; ); `else \tassign oSMB_DEBUG_PLD_SDA_OE = HIGH; `endif  endmodule <\/code><\/pre>\n<p>  <\/div>\n<\/p><\/div>\n<p>  <b>\u0424\u0430\u0439\u043b PPSampleApp_intel123.zip<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u0443\u0442\u0438\u043b\u0438\u0442\u044b \u043d\u0435\u0438\u0437\u0432\u0435\u0441\u0442\u043d\u043e\u0433\u043e \u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u043d\u0430 C++ \u0434\u043b\u044f VS2013. \u041f\u0430\u0440\u043e\u043b\u044c \u0430\u0440\u0445\u0438\u0432\u0430 \u00abintel123\u00bb.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b R5MR_DT_Firmware_Release_(8C2C17_8C1C12).zip<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438 \u043a\u0430\u043a\u043e\u0433\u043e-\u0442\u043e xDSL \u043c\u0430\u0440\u0448\u0440\u0443\u0442\u0438\u0437\u0430\u0442\u043e\u0440\u0430 Intel. \u0427\u0430\u0441\u0442\u044c \u043a\u043e\u0434\u0430 \u043d\u0430 ASM.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b TGL_3175_01_282_Engineering_Release.zip<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 BIOS, \u043a\u043e\u0434\u043e\u0432 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438, Client Silicon \u0438 \u043f\u043e\u0434\u043e\u0431\u043d\u043e\u0433\u043e \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Tiger Lake.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b tgl_bios_ww17_2020.zip<\/b><\/p>\n<p>  \u041d\u0435\u0441\u043a\u043e\u043b\u044c\u043a\u043e \u0432\u0435\u0440\u0441\u0438\u0439 \u0431\u0438\u043d\u0430\u0440\u043d\u0438\u043a\u043e\u0432 \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438 BIOS Tiger Lake.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b TGL_V2527_10_IPCM_Sample_Code_V1.0.0.zip<\/b><\/p>\n<p>  \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u0434\u0440\u0430\u0439\u0432\u0435\u0440\u0430 <a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/articles\/intel-performance-counter-monitor.html\" rel=\"nofollow\">IPCM<\/a> Tiger Lake \u0434\u043b\u044f \u0438\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u0438 \u0432 \u0441\u0432\u043e\u0439 BIOS.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b ucodeupdatecapsule_0x30_0x31.zip<\/b><\/p>\n<p>  \u041e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u0435 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u0434\u0430 \u0434\u043b\u044f \u043d\u0435\u0438\u0437\u0432\u0435\u0441\u0442\u043d\u043e\u0433\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430. \u0411\u0438\u043d\u0430\u0440\u043d\u0438\u043a\u0438 \u0434\u043b\u044f \u0432\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u044f \u0432 \u043e\u0431\u0449\u0438\u0439 \u043f\u0430\u043a\u0435\u0442 \u043e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u044f BIOS. \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u043e\u0432 <a href=\"https:\/\/ru.wikipedia.org\/wiki\/%D0%9C%D0%B8%D0%BA%D1%80%D0%BE%D0%BA%D0%BE%D0%B4\" rel=\"nofollow\">\u043c\u0438\u043a\u0440\u043e\u043a\u043e\u0434\u0430<\/a> \u043c\u044b \u043d\u0438\u043a\u043e\u0433\u0434\u0430 \u043d\u0435 \u0443\u0432\u0438\u0434\u0438\u043c.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b wav_fw_src_06.01.00_er7.87_20191226040022.zip<\/b><\/p>\n<p>  \u041f\u043e\u0445\u043e\u0436\u0435 \u043d\u0430 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438 \u0438\u043d\u0442\u0435\u043b\u043e\u0432\u0441\u043a\u043e\u0433\u043e \u043c\u0430\u0440\u0448\u0440\u0443\u0442\u0438\u0437\u0430\u0442\u043e\u0440\u0430.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b WW04&#8217;20_Ext_RKL_S_VP_PPR.zip<\/b><\/p>\n<p>  \u0411\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a\u0430 \u043c\u043e\u0434\u0435\u043b\u0435\u0439 \u0434\u043b\u044f \u044d\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Rocket Lake S \u0441 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u0435\u043c.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/ys\/gp\/nm\/ysgpnmmwsc30pu_vnxnz-ls-q-c.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b WW18&#8217;20_Ext_RKL_S_VP_PPR.zip<\/b><\/p>\n<p>  \u041e\u0431\u043d\u043e\u0432\u043b\u0435\u043d\u0438\u0435 \u043c\u043e\u0434\u0435\u043b\u0435\u0439 \u0434\u043b\u044f Rocket Lake S.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b WW11&#8217;20_Ext_TGL_H_VP_PPR.zip<\/b><\/p>\n<p>  \u0422\u043e \u0436\u0435 \u0441\u0430\u043c\u043e\u0435 \u0434\u043b\u044f Tiger Lake H.<\/p>\n<p>  <b>\u0424\u0430\u0439\u043b WW18&#8217;20_Ext_ADL_S_VP_PPR.zip<\/b><\/p>\n<p>  \u0422\u043e \u0436\u0435 \u0434\u043b\u044f Alder Lake S.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/sg\/yh\/qr\/sgyhqr7aehmr3bd5pbzrrj-uvig.png\"><\/p>\n<p>  <a name=\"addition\"><\/a><br \/>  \u041f\u043e\u0437\u0436\u0435 \u0431\u044b\u043b\u043e <a href=\"https:\/\/t.me\/exconfidential\/604\" rel=\"nofollow\">\u043d\u0435\u0431\u043e\u043b\u044c\u0448\u043e\u0435 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Switch. \u0418\u0437 \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f \u043c\u043e\u0436\u043d\u043e \u0443\u0437\u043d\u0430\u0442\u044c, \u0447\u0442\u043e \u043e\u043d\u0430 \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0430 \u0434\u043b\u044f \u0432\u0441\u0435\u0441\u0442\u043e\u0440\u043e\u043d\u043d\u0435\u0433\u043e \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u043e\u0433\u043e \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f <a href=\"https:\/\/software.intel.com\/content\/www\/us\/en\/develop\/documentation\/vtune-help\/top\/reference\/energy-analysis-metrics-reference\/p-state.html\" rel=\"nofollow\">p-states<\/a> (\u0440\u0435\u0433\u0443\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u043d\u0430\u043f\u0440\u044f\u0436\u0435\u043d\u0438\u044f \u0438 \u0447\u0430\u0441\u0442\u043e\u0442\u044b \u0432 \u0437\u0430\u0432\u0438\u0441\u0438\u043c\u043e\u0441\u0442\u0438 \u043e\u0442 \u043d\u0430\u0433\u0440\u0443\u0437\u043a\u0438) \u043c\u043e\u0431\u0438\u043b\u044c\u043d\u044b\u0445 \u0438 \u043d\u0430\u0441\u0442\u043e\u043b\u044c\u043d\u044b\u0445 \u0441\u0438\u0441\u0442\u0435\u043c. \u041f\u0440\u0438\u043b\u043e\u0436\u0435\u043d\u0430 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f \u0438 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u044f \u043f\u043e \u0430\u0434\u0430\u043f\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044e \u0442\u0435\u0441\u0442\u043e\u0432 OEM-\u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0430\u043c\u0438 \u0434\u043b\u044f \u0441\u0432\u043e\u0438\u0445 \u043d\u0443\u0436\u0434.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/o8\/gr\/st\/o8grstiodrgq-yggqhwwemhcwt8.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b Certificates.zip<\/b><\/p>\n<p>  \u0422\u0443\u0442 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tigerisland-rev1.zip<\/b><\/p>\n<p>  \u042d\u043b\u0435\u043a\u0442\u0440\u043e\u0441\u0445\u0435\u043c\u044b, \u0434\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u044b \u0438 \u0441\u043f\u0438\u0441\u043e\u043a \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u043e\u0432 \u043f\u0440\u043e\u0442\u043e\u0442\u0438\u043f\u0430 \u043d\u043e\u0443\u0442\u0431\u0443\u043a\u0430 \u043d\u0430 Tiger Lake.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/x6\/qt\/q3\/x6qtq3dkqjerex4fpveywhf6dlq.png\"><\/p>\n<p>  <b>\u0424\u0430\u0439\u043b Lakefield_Pets.zip<\/b><\/p>\n<p>  \u0414\u0438\u0441\u0442\u0440\u0438\u0431\u0443\u0442\u0438\u0432 \u0438 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b Intel Platform Enablement Test Suite. \u0415\u0449\u0451 \u043e\u0434\u043d\u043e \u043f\u0440\u0438\u043b\u043e\u0436\u0435\u043d\u0438\u0435 \u0434\u043b\u044f \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u043e\u0433\u043e \u0442\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f Intel ME \u0434\u043b\u044f \u043f\u043b\u0430\u0442\u0444\u043e\u0440\u043c\u044b <a href=\"https:\/\/newsroom.intel.com\/news\/intel-hybrid-processors-uncompromised-pc-experiences-innovative-form-factors-foldables-dual-screens\/\" rel=\"nofollow\">Lakefield<\/a>.<\/p>\n<p>  \u0412\u043e\u0442 \u0438 \u0432\u0441\u0451. <\/p>\n<p>  <a href=\"https:\/\/t.me\/govnokoder\" rel=\"nofollow\">\u041f\u043e\u0434\u043f\u0438\u0441\u044b\u0432\u0430\u0439\u0442\u0435\u0441\u044c \u043d\u0430 \u043a\u0430\u043d\u0430\u043b<\/a>, \u0441\u0442\u0430\u0432\u044c\u0442\u0435 \u043b\u0430\u0439\u043a\u0438, <a href=\"https:\/\/money.yandex.ru\/to\/41001516590259\" rel=\"nofollow\">\u043f\u0440\u0438\u0441\u044b\u043b\u0430\u0439\u0442\u0435 \u0432\u0430\u0448\u0438 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\u043e\u0446\u0435\u043d\u043a\u0438 \u0441\u0435\u0440\u044c\u0451\u0437\u043d\u043e\u0441\u0442\u0438 \u044d\u0442\u043e\u0439 \u0443\u0442\u0435\u0447\u043a\u0438.<\/p>\n<p>  <img decoding=\"async\" src=\"https:\/\/habrastorage.org\/webt\/x6\/qt\/q3\/x6qtq3dkqjerex4fpveywhf6dlq.png\"><br \/>  <i>\u041a\u0414\u041f\u0412. \u041f\u0440\u043e\u0442\u043e\u0442\u0438\u043f \u043d\u043e\u0443\u0442\u0431\u0443\u043a\u0430 \u043d\u0430 Tiger Lake.<\/i><\/p>\n<h4>\u041a\u0440\u0430\u0442\u043a\u043e\u0435 \u0440\u0435\u0437\u044e\u043c\u0435<\/h4>\n<p>  \u0411\u043e\u043b\u044c\u0448\u0430\u044f \u0447\u0430\u0441\u0442\u044c \u0441\u043b\u0438\u0442\u043e\u0439 \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u0438 \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0430 \u0434\u043b\u044f OEM\/ODM \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u043e\u0432 \u0438 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u0439, \u043d\u043e \u0437\u0430\u0438\u043d\u0442\u0435\u0440\u0435\u0441\u0443\u0435\u0442 \u044d\u043d\u0442\u0443\u0437\u0438\u0430\u0441\u0442\u043e\u0432, \u0438\u0441\u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u0445 BIOS \u0438 \u043d\u0435\u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0435 \u0440\u0435\u0436\u0438\u043c\u044b \u0440\u0430\u0431\u043e\u0442\u044b \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 Intel. \u0412 \u043d\u0438\u0445 \u043d\u0435\u0442 \u0432\u043d\u0443\u0442\u0440\u0435\u043d\u043d\u0435\u0439 \u0438\u043d\u0442\u0435\u043b\u043e\u0432\u0441\u043a\u043e\u0439 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u0438, \u043a\u0440\u0438\u0442\u0438\u0447\u043d\u043e\u0439 \u043a \u043e\u0431\u043d\u0430\u0440\u043e\u0434\u043e\u0432\u0430\u043d\u0438\u044e, \u0438\u043b\u0438 \u0441\u043f\u043e\u0441\u043e\u0431\u043d\u043e\u0439 \u0440\u0430\u0441\u043a\u0440\u044b\u0442\u044c \u0441\u0435\u043a\u0440\u0435\u0442\u043d\u044b\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438. \u0422\u0430\u043a\u0436\u0435 \u0437\u0434\u0435\u0441\u044c \u043d\u0435 \u043d\u0430\u0439\u0442\u0438 \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u0438 \u043e \u043d\u0435\u0438\u0437\u0432\u0435\u0441\u0442\u043d\u044b\u0445 \u0440\u0430\u043d\u0435\u0435 \u0443\u044f\u0437\u0432\u0438\u043c\u043e\u0441\u0442\u044f\u0445.  <\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-308240","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/308240","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=308240"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/308240\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=308240"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=308240"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=308240"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}