{"id":362640,"date":"2024-05-21T01:39:15","date_gmt":"2024-05-21T01:39:15","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=362640"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=362640","title":{"rendered":"The first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA<\/span>"},"content":{"rendered":"
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\"Maria,<\/p>\n
Maria, an engineer from Broadcom, will be on our meetup too<\/figcaption><\/div>\n<\/figure>\n

Need to start your career or hobby in digital design and verification of silicon chips or reconfigurable hardware? Explore multiple FPGA toolchains and open-source ASIC tools? Design your own RISC-V CPU or ML accelerator? Prepare for an interview in SystemVerilog? Come to our first Silicon Valley meetup on portable SystemVerilog examples for ASIC and FPGA.<\/p>\n

The meetup is scheduled on Sunday, January 14, 2024 from 2pm till 5pm<\/a>. We are going to meet in Hacker Dojo<\/a>, a famous coworking space located in MountainView<\/a>. You can get more information if you join the meetup group on LinkedIn<\/a> and Telegram<\/a>.<\/p>\n

\"Hacker<\/p>\n
Hacker Dojo in Mountain View, California<\/figcaption><\/div>\n<\/figure>\n

Some background<\/strong><\/p>\n

During the last three decades, practically all digital chips have been designed using logic synthesis from hardware description languages, Verilog and VHDL. A convenient way to train future designers of mass-market ASICs (Application-Specific Integrated Circuits) is to make them do projects using FPGA (Field-Programmable Gate Arrays), reconfigurable hardware chips. The problem is the steep learning curve:<\/p>\n

1. The model of computation used in hardware description languages, called Register Transfer Level (RTL), is sometimes counter-intuitive to students who are used to software programming languages.<\/p>\n

2. The tools are finicky, the educational boards are many, and the vendors (Xilinx, Altera, Lattice, Gowin) work hard to ensure vendor lock.<\/p>\n

3. The universities do not go far enough in teaching practical microarchitecture. Many students only learn the basics of HDL, the same five-stage-pipeline simple CPU, and can talk about processors, but have limited experience in designing pipelined circuits with modern flow-control techniques by themselves.<\/p>\n

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To address some of these shortcomings, a group of folks in different cities and countries created a set of board wrappers and scripts to make a number of SystemVerilog examples<\/a> running on more than 30 different boards, with FPGAs from Xilinx\/AMD, IntelFPGA\/Altera, Lattice and Gowin. You just select a board from a menu, then run a script that automatically synthesizes a wrapped design and configures your target.<\/p>\n

We also created a set of SystemVerilog coding problems ranging from elementary syntax to interview-level questions on microarchitecture<\/a> to improve coding and prepare students for real work in electronic companies (learning the university textbook is unfortunately not enough).<\/p>\n

These solutions have already been used for FPGA seminars in more than 20 universities, and now we want to extend them to offline meetings in Silicon Valley. If you are considering a career in the ASIC or FPGA field, or if you are already proficient in one FPGA toolchain and want to explore others, or if you want to create your own RISC-V CPU and don’t know where to start — you are welcome, we will help you.<\/p>\n

In exchange, we expect you to help adopt new FPGA boards (there are many not supported yet), create your own projects that can be used as examples for newcomers (particularly projects that work with graphics and sound), and publish articles about them in social media.<\/p>\n

One of our examples uses FPGA to recognize music<\/a> (no software involved, just a digital circuit implemented in reconfigurable hardware):<\/p>\n

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Another example features a Geiger-Muller radiation counter<\/a> connected to an FPGA board. You can even determine the direction where the radiation is coming from — because this counter has two tubes. A planned extension is to estimate the energy of a particle by measuring the timing of the associated signal. The radiation counter is from GGLabs<\/a>:<\/p>\n

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Join us in Hacker Dojo and we will go through those topics in great detail. We are going to bring a collection of more than 30 FPGA boards from different vendors. You can bring your notebook with Altera Quartus, Xilinx Vivado or Gowin IDE installation, either under Linux or Windows. We also have ~20 bootable SSDs with Linux and all the necessary software installed. You can just put one of those SSDs into your notebook, boot from it and work with a board you choose. See you there!<\/p>\n

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The related posts about the event:<\/p>\n