{"id":363793,"date":"2024-05-21T02:03:35","date_gmt":"2024-05-21T02:03:35","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=363793"},"modified":"-0001-11-30T00:00:00","modified_gmt":"2024-05-21T02:03:35","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=363793","title":{"rendered":"Toward the January meetup on portable SystemVerilog examples in Silicon Valley<\/span>"},"content":{"rendered":"
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The\u00a0team developing a set of portable SystemVerilog examples\u00a0<\/a>decided to organize the first event in Silicon Valley on Sunday, January 14 from 2PM till 5PM at\u00a0Hacker Dojo in Mountain View, CA<\/a>. If the first event is successful we are going to make it recurrent. You can register for the event on\u00a0Meetup<\/a>\u00a0or\u00a0LinkedIn<\/a>.<\/p>\n

The current directions of the group:<\/p>\n

1. Scripts for abstracting FPGA boards to develop board-independent and toolchain-independent SystemVerilog examples. This allows for teaching university courses and running educational seminars with a variety of boards available at a given place. The current state is in\u00a0basics-graphics-music<\/a>\u00a0GitHub repository.<\/p>\n

2. Integration of the peripherals to make the classes more interesting. Adding sound generation and recognition, computer graphics and sensors, also with an abstraction level to allow the students to use different microphones and display interfaces with different numbers of color bits per pixel.<\/p>\n

3. The examples and homework exercises to teach the students the mechanics of Register-Transfer Level (RTL) design methodology, the basics of pipelining, flow control, and microarchitectural primitives, such as FIFOs and arbiters. The current public (without solutions) repositories include\u00a0systemverilog-homework<\/a>\u00a0and\u00a0valid-ready-etc<\/a>\u00a0.<\/p>\n

4. Wrapping various RISC-V CPU cores in the board-independent platform to give the students an opportunity to compare different microarchitectures, from a simplified single-cycle implementation of a subset of RISC-V architecture — to cache-less MCU-level cores — to more complicated cores with caches, TLB MMU, superscalar execution and the ability to run Linux. The examples we have worked with so far included\u00a0schoolRISCV<\/a>\u00a0and\u00a0yrv-plus<\/a>\u00a0.<\/p>\n

5. Connecting FPGA-based training to ASIC design. Making sure all the microarchitectural and CPU-based examples are synthesizable with Open Lane ASIC synthesis, demonstrating how microarchitecture decisions affect ASIC timing, exploring ASIC platforms like Efabless Caravel, etc.<\/p>\n

\"Altera<\/p>\n
Altera Terasic: DE0, DE0-CV, DE0-Nano, DE10-Lite, DE1-SoC, DE2-115, Omdazz.
Altera: RzRd, Piswords-6, Saylinx, Zeowaa, EPI-MiniCY4.
Xilinx: Digilent Basys3, Nexys4, Nexys4-DDR, Nexys A7.
Gowin: Tang Primer 20K Dock.<\/figcaption><\/div>\n<\/figure>\n

More details about the scripts for abstracting FPGA boards:<\/p>\n

We implemented a push-button synthesis and simulation platform for a set of SystemVerilog examples. The platform is written in a way that the same SV source code works with any of the supported 30 FPGA boards, 5 synthesis toolchains (Altera, Xilinx, Gowin, Lattice, Yosys) and 2 simulators (Icarus and Questa).<\/p>\n

No complicated setup or scripting is required on the part of the platform user. He should install the necessary toolchains to their default locations, clone the example repository, select the board, go to the example directory and run a script, such as 03_synthesize_for_fpga.bash.<\/p>\n

The script automatically locates the necessary EDA and board configuration software, creates the project files, runs the synthesis and configures the FPGA on the selected board. The script produces meaningful error messages, so the user does not have to dig through the log files and scripts.<\/p>\n

The scripts work under Linux and Windows. For Windows, we are using bash shell from Git. The scripts could be adopted for Windows Subsystem for Linux (WSL), but it was not done yet. If you attempt to run it under WSL, it will ask to run either under true Linux or under true Windows with Git bash.<\/p>\n

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More details on integration of the peripherals to make the classes more interesting: right now our examples support the following parts:<\/p>\n

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  1. \n

    INMP441 and Pmod MIC3 microphones<\/p>\n<\/li>\n

  2. \n

    I2S audio output via Pmod AMP3 and HiLetgo PCM5102<\/p>\n<\/li>\n

  3. \n

    VGA connectors Pmod VGA and VGA666<\/p>\n<\/li>\n

  4. \n

    External I\/O module based on TM1638 chip <\/p>\n<\/li>\n<\/ol>\n

    TODO: It is necessary to improve support for VGA by adding the parameters for RGB channel width, from 1 to 8 bits per channel.<\/p>\n

    \"INMP441<\/p>\n
    INMP441 and Pmod MIC3 microphones connected to Omdazz FPGA board with Altera Cyclone IV FPGA<\/figcaption><\/div>\n<\/figure>\n
    \"TM1638-based<\/p>\n
    TM1638-based 7-segment \/ button \/ LED module and Pmod VGA connected to SiPEED Tang Primer 20K Doc board with Gowin FPGA<\/figcaption><\/div>\n<\/figure>\n

    It is necessary to test and adopt the following peripherals:<\/p>\n

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    1. \n

      HiLetgo and Adafruit I2S MEMS Microphone based on SPH0645LM4H<\/p>\n<\/li>\n

    2. \n

      I2S audio output based on CJMCU-1334 chip.<\/p>\n<\/li>\n

    3. \n

      TM1638-based external I\/O module (7-segment, buttons, LEDs) with keyboard matrix.<\/a><\/p>\n<\/li>\n

    4. \n

      USB-to-UART interfaces for the examples that require communication of FPGA board with a computer.<\/p>\n<\/li>\n

    5. \n

      HDMI support<\/p>\n<\/li>\n

    6. \n

      Rotary encoder — this is a good task for an exam<\/p>\n<\/li>\n

    7. \n

      Ultrasonic Distance Sensor based on HC-SR04 — this is a good task for an exam<\/p>\n<\/li>\n

    8. \n

      Infrared receiver<\/p>\n<\/li>\n

    9. \n

      MAX7219-based 7-segment display<\/a><\/p>\n<\/li>\n

    10. \n

      Matrix keyboard — this is a good task for an exam<\/a><\/p>\n<\/li>\n<\/ol>\n

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      We elaborate on board-specific topics in the follow-up article<\/a>.<\/p>\n

      Note that FPGA board and periphery support is only a part of the planned activity. It is suitable for those who wants to start or explore another FPGA toolchain. But the more we move we are going to focus on microarchitectural and CPU examples, as well as making sure the code is compatible with Open Lane ASIC synthesis toolchain.<\/p>\n

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      The related posts about the event:<\/p>\n