{"id":366261,"date":"2024-05-21T02:55:33","date_gmt":"2024-05-21T02:55:33","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=366261"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=366261","title":{"rendered":"Portable SystemVerilog Examples for ASIC and FPGA: the results of the meetup on 2024-01-21 and the next steps<\/span>"},"content":{"rendered":"
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The second meetup<\/a> of the Portable SystemVerilog Examples group<\/a> on January 21 2024 at Hacker Dojo in Mountain View, California<\/a>, went as planned: we moved from the stage of presenting the project<\/a> to the self-introductions of the participants and the initial tutorial with the first examples. We also started distributing the tasks. The next meetup is scheduled for January 28 at the same location, from 2 pm to 5 pm<\/a>. The contents of the meeting will be to work on the examples: basics-graphics-music<\/a> and systemverilog-homework<\/a>.<\/p>\n

Overall the goal of the group is to improve a set of portable SystemVerilog examples to use in educational seminars worldwide on digital design and microarchitecture. The focus is on solving three challenges:<\/p>\n

    \n
  1. \n

    Removing EDA and FPGA vendor locks for the educators. The examples support 30 boards with FPGAs from Xilinx, Altera, Gowin and Lattice and aim to be compatible with open-source ASIC design tools.<\/p>\n<\/li>\n

  2. \n

    Compensating the gap between academia and industry in solving microarchitectural problems necessary for a career in ASIC design, building CPU, GPU and networking chips.<\/p>\n<\/li>\n

  3. \n

    Reducing the barrier of entry for the novice or a person from a related field aiming to extend their expertise to become better in system design or software acceleration.<\/p>\n<\/li>\n<\/ol>\n

    The motivation to participate in the group for different participants varies:<\/p>\n

      \n
    1. \n

      One gentleman and one lady have long experience working as a design verification (DV) engineer. The gentleman knows SystemVerilog but needs to beef up his experience in RTL microarchitecture: building pipelines, data flow control, arbitration, and FIFOs. The lady also knows SystemVerilog but needs to get familiar with FPGAs. I would expect the following sequence of steps from them:<\/p>\n

      a) Go through all the systemverilog-homework<\/a> exercises. I will check the results. To go through the exercises you need to have Icarus Verilog version 12 installed either under Linux or Windows. Then you go to a subdirectory of the cloned repository and run either 01_combinational_logic\/run_all_using_iverilog_under_linux_or_macos_brew.sh<\/a> (Linux) or run_all_using_iverilog_under_windows.bat<\/a> (Windows).<\/p>\n

      b) Go through all the examples in basics-graphics-music<\/a> we did in the previous meetup.<\/p>\n

      c) Get from me a board we do not support yet and adopt the examples to that board by writing proper board-specific files and modifying the scripts.<\/p>\n

      d) Discuss with me the next microarchitectural examples to write. Some can be based on the information from Digital Design: A Systems Approach by William James Dally and R. Curtis Harting<\/a>.<\/p>\n<\/li>\n

    2. \n

      Another gentleman is already an RTL designer but has limited exposure to CPUs. We have tasks to integrate a number of CPU cores into other example infrastructure, starting from the simplest schoolRISCV<\/a> to several more complicated cores. We should create a series of interview-like problems, for example: «Get schoolRISCV, a single-cycle core with 240 lines of Verilog code, and show how you can add a multiplication instruction with a pipelined multiplier, implemented as a black box with latency 2 clock cycles».<\/p>\n

      I would recommend this gentleman to do a), b), c), then:<\/p>\n

      e) Read chapters 6 and 7 of Digital Design and Computer Architecture, RISC-V Edition by Sarah Harris and David Harris<\/a>.<\/p>\n

      f) Adopt schoolRISCV into the basics-graphics-music<\/a> infrastructure.
      g) Work on adopting several more RISC-V cores.
      h) Work on creating an example of multiple cores sharing multi-bank memory with arbitration.
      i) Work on creating an example of multiple cores exchanging messages with FIFOs.
      j) Work with me on creating interview questions similar to the one outlined above.<\/p>\n<\/li>\n

    3. \n

      There were several participants who went through the basic digital design classes in the university but later on worked on something else: embedded software or PCB design. There were also students who are looking to start or improve their knowledge. Not necessarily from scratch: one gentleman learned Verilog but wants to learn SystemVerilog. I would expect all of them to go through a), b), c) and also study the following two books:<\/p>\n

      k) Already mentioned Digital Design and Computer Architecture, RISC-V Edition by Sarah Harris and David Harris<\/a> but from the beginning.
      l)       Logic Design and Verification Using SystemVerilog \u2013 March 1, 2016 by Donald Thomas<\/a>. Not to be confused with the old (starting 1980s) books of the same author.
      m)       IEEE 1800-2017 — Standard for SystemVerilog<\/a> should be used as a reference.<\/p>\n<\/li>\n

    4. \n

      There was also a distinguished school teacher (ex-Xilinx) who wants to try FPGA lessons in his technology curriculum. I created a special set of minimalistic examples to be used with minimalistic boards<\/a>, and we can start from those examples at our next meetup on January 28. We can also try schoolRISCV with him. I would expect from him a) b) c) e) f) k) l).<\/p>\n<\/li>\n

    5. \n

      Finally, we have a lady who is interested in working on even more introductory examples for children, using small-scale integration chips on a breadboard. We can create a smooth transition from these examples and examples on FPGA boards. <\/p>\n<\/li>\n<\/ol>\n

      We also discussed the need to formulate a hackathon proposal that can be made for an FPGA, EDA, or electronic vendor.<\/p>\n

      See you all and possibly some new participants at the next meetup on Sunday, January 28, 2024, at Hacker Dojo in Mountain View, California, at 2 pm. For those who cannot join in person, you can try to use Zoom with the provided link<\/a>. <\/p>\n

      <\/figure>\n<\/p>\n<\/div>\n<\/div>\n<\/div>\n

      <\/div>\n


      \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438       https:\/\/habr.com\/ru\/articles\/788710\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

      <\/div>\n
      \n
      \n
      \n
      \n
      <\/figure>\n

      The second meetup<\/a> of the Portable SystemVerilog Examples group<\/a> on January 21 2024 at Hacker Dojo in Mountain View, California<\/a>, went as planned: we moved from the stage of presenting the project<\/a> to the self-introductions of the participants and the initial tutorial with the first examples. We also started distributing the tasks. The next meetup is scheduled for January 28 at the same location, from 2 pm to 5 pm<\/a>. The contents of the meeting will be to work on the examples: basics-graphics-music<\/a> and systemverilog-homework<\/a>.<\/p>\n

      Overall the goal of the group is to improve a set of portable SystemVerilog examples to use in educational seminars worldwide on digital design and microarchitecture. The focus is on solving three challenges:<\/p>\n

        \n
      1. \n

        Removing EDA and FPGA vendor locks for the educators. The examples support 30 boards with FPGAs from Xilinx, Altera, Gowin and Lattice and aim to be compatible with open-source ASIC design tools.<\/p>\n<\/li>\n

      2. \n

        Compensating the gap between academia and industry in solving microarchitectural problems necessary for a career in ASIC design, building CPU, GPU and networking chips.<\/p>\n<\/li>\n

      3. \n

        Reducing the barrier of entry for the novice or a person from a related field aiming to extend their expertise to become better in system design or software acceleration.<\/p>\n<\/li>\n<\/ol>\n

        The motivation to participate in the group for different participants varies:<\/p>\n

          \n
        1. \n

          One gentleman and one lady have long experience working as a design verification (DV) engineer. The gentleman knows SystemVerilog but needs to beef up his experience in RTL microarchitecture: building pipelines, data flow control, arbitration, and FIFOs. The lady also knows SystemVerilog but needs to get familiar with FPGAs. I would expect the following sequence of steps from them:<\/p>\n

          a) Go through all the systemverilog-homework<\/a> exercises. I will check the results. To go through the exercises you need to have Icarus Verilog version 12 installed either under Linux or Windows. Then you go to a subdirectory of the cloned repository and run either 01_combinational_logic\/run_all_using_iverilog_under_linux_or_macos_brew.sh<\/a> (Linux) or run_all_using_iverilog_under_windows.bat<\/a> (Windows).<\/p>\n

          b) Go through all the examples in basics-graphics-music<\/a> we did in the previous meetup.<\/p>\n

          c) Get from me a board we do not support yet and adopt the examples to that board by writing proper board-specific files and modifying the scripts.<\/p>\n

          d) Discuss with me the next microarchitectural examples to write. Some can be based on the information from Digital Design: A Systems Approach by William James Dally and R. Curtis Harting<\/a>.<\/p>\n<\/li>\n

        2. \n

          Another gentleman is already an RTL designer but has limited exposure to CPUs. We have tasks to integrate a number of CPU cores into other example infrastructure, starting from the simplest schoolRISCV<\/a> to several more complicated cores. We should create a series of interview-like problems, for example: «Get schoolRISCV, a single-cycle core with 240 lines of Verilog code, and show how you can add a multiplication instruction with a pipelined multiplier, implemented as a black box with latency 2 clock cycles».<\/p>\n

          I would recommend this gentleman to do a), b), c), then:<\/p>\n

          e) Read chapters 6 and 7 of Digital Design and Computer Architecture, RISC-V Edition by Sarah Harris and David Harris<\/a>.<\/p>\n

          f) Adopt schoolRISCV into the basics-graphics-music<\/a> infrastructure.
          g) Work on adopting several more RISC-V cores.
          h) Work on creating an example of multiple cores sharing multi-bank memory with arbitration.
          i) Work on creating an example of multiple cores exchanging messages with FIFOs.
          j) Work with me on creating interview questions similar to the one outlined above.<\/p>\n<\/li>\n

        3. \n

          There were several participants who went through the basic digital design classes in the university but later on worked on something else: embedded software or PCB design. There were also students who are looking to start or improve their knowledge. Not necessarily from scratch: one gentleman learned Verilog but wants to learn SystemVerilog. I would expect all of them to go through a), b), c) and also study the following two books:<\/p>\n

          k) Already mentioned Digital Design and Computer Architecture, RISC-V Edition by Sarah Harris and David Harris<\/a> but from the beginning.
          l)           Logic Design and Verification Using SystemVerilog \u2013 March 1, 2016 by Donald Thomas<\/a>. Not to be confused with the old (starting 1980s) books of the same author.
          m)           IEEE 1800-2017 — Standard for SystemVerilog<\/a> should be used as a reference.<\/p>\n<\/li>\n

        4. \n

          There was also a distinguished school teacher (ex-Xilinx) who wants to try FPGA lessons in his technology curriculum. I created a special set of minimalistic examples to be used with minimalistic boards<\/a>, and we can start from those examples at our next meetup on January 28. We can also try schoolRISCV with him. I would expect from him a) b) c) e) f) k) l).<\/p>\n<\/li>\n

        5. \n

          Finally, we have a lady who is interested in working on even more introductory examples for children, using small-scale integration chips on a breadboard. We can create a smooth transition from these examples and examples on FPGA boards. <\/p>\n<\/li>\n<\/ol>\n

          We also discussed the need to formulate a hackathon proposal that can be made for an FPGA, EDA, or electronic vendor.<\/p>\n

          See you all and possibly some new participants at the next meetup on Sunday, January 28, 2024, at Hacker Dojo in Mountain View, California, at 2 pm. For those who cannot join in person, you can try to use Zoom with the provided link<\/a>. <\/p>\n

          <\/figure>\n<\/p>\n<\/div>\n<\/div>\n<\/div>\n

          <\/div>\n


          \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438           https:\/\/habr.com\/ru\/articles\/788710\/<\/a>
          <\/br><\/br><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-366261","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/366261","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=366261"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/366261\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=366261"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=366261"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=366261"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}