{"id":380303,"date":"2024-06-29T03:00:22","date_gmt":"2024-06-29T03:00:22","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=380303"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=380303","title":{"rendered":"<span>Passcode Data Protection by Using FPGA and Verilog<\/span>"},"content":{"rendered":"<div><!--[--><!--]--><\/div>\n<div id=\"post-content-body\">\n<div>\n<div class=\"article-formatted-body article-formatted-body article-formatted-body_version-2\">\n<div xmlns=\"http:\/\/www.w3.org\/1999\/xhtml\">\n<h2>Passcode Data Protection by Using FPGA and Verilog<\/h2>\n<h4>Authors<\/h4>\n<p><a href=\"https:\/\/github.com\/art22m\" rel=\"noopener noreferrer nofollow\">Artem Murashko<\/a>, <a href=\"https:\/\/github.com\/SyrexMinus\" rel=\"noopener noreferrer nofollow\">Makar Shevchenko<\/a> and <a href=\"https:\/\/github.com\/aalexren\" rel=\"noopener noreferrer nofollow\">Artem Chernitsa<\/a>.<\/p>\n<h4>Introduction<\/h4>\n<p>There are many situations when you need to protect your data, and different tools can be used to do that. For example, a safe. We develop a passcode data protection mechanism by using an FPGA board and Quartus Prime software. It allows demonstrating the basic concepts of a combination lock such as entering data, setting and checking a passcode, and displaying data.<\/p>\n<h4>Hardware and software used<\/h4>\n<p>Our project is implemented by using following devices and technologies: <\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/ep\/px\/q4\/eppxq4_b9pnlyftw7orbmnqhn0k.png\" alt=\" Figure 1: The schematic representation of an FPGA board. \" title=\" Figure 1: The schematic representation of an FPGA board. \" width=\"611\" height=\"441\" data-src=\"https:\/\/habrastorage.org\/webt\/ep\/px\/q4\/eppxq4_b9pnlyftw7orbmnqhn0k.png\"\/><figcaption> Figure 1: The schematic representation of an FPGA board. <\/figcaption><\/figure>\n<\/p>\n<ul>\n<li>\n<p>Cyclone IV FPGA Device<\/p>\n<p>\u200b    Buttons (input device)<\/p>\n<p>\u200b    LEDs and 7-Segment display (output device)<\/p>\n<p>\u200b    Power Supply port (used to power FPGA board)<\/p>\n<p>\u200b    USB Blaster connector (used to upload firmware)<\/p>\n<\/li>\n<li>\n<p>Quartus Prime Lite Edition 18.1<\/p>\n<p>\u200b    Verilog HDL  <\/p>\n<\/li>\n<li>\n<p>Altera USB Blaster (USB Blaster transfers configuration data from PC to FPGA)<\/p>\n<\/li>\n<\/ul>\n<h4>Technical implementation<\/h4>\n<ul>\n<li>\n<p>Schematic representation of program execution<\/p>\n<p>The diagram in Figure 2 shows the flow of the program. The circles are states, arrows are transition conditions.<\/p>\n<\/li>\n<\/ul>\n<figure class=\"bordered\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/q4\/tc\/3o\/q4tc3otm8bfojvqlsv1rdoggh3q.png\" alt=\" Figure 2: The flowchart of the program. \" title=\" Figure 2: The flowchart of the program. \" width=\"538\" height=\"321\" data-src=\"https:\/\/habrastorage.org\/webt\/q4\/tc\/3o\/q4tc3otm8bfojvqlsv1rdoggh3q.png\"\/><figcaption> Figure 2: The flowchart of the program. <\/figcaption><\/figure>\n<\/p>\n<ul>\n<li>\n<p>Displaying the state of the program<\/p>\n<p>We used LEDs to display the current state of the program. Cyclone IV FPGA board have 12 LEDs and each LED has its own number. Figure 3 shows the LEDs arrangement.<\/p>\n<\/li>\n<\/ul>\n<figure class=\"float\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/bc\/2b\/3c\/bc2b3cajpyawdnx86fcfmkevvti.png\" alt=\"Figure 3: LEDs arrangement.    \" title=\"Figure 3: LEDs arrangement.    \" width=\"236\" height=\"218\" data-src=\"https:\/\/habrastorage.org\/webt\/bc\/2b\/3c\/bc2b3cajpyawdnx86fcfmkevvti.png\"\/><figcaption>Figure 3: LEDs arrangement.    <\/figcaption><\/figure>\n<p>                                                                                                                              D4 to indicate the state &#171;Enter data to be saved&#187;;                                                                                         D7 to indicate the state &#171;Set up the passcode&#187;;                                                        D10 to indicate the state &#171;Enter the passcode&#187;;                                                          D13 to indicate the state &#171;Show data has been saved&#187;;<\/p>\n<p>\u200b     <\/p>\n<ul>\n<li>\n<p>7-Segment display<\/p>\n<p>If we want to bind each cathode (stick) to the registers, than it would take 8*8=64 power tracks for each display. To save space on the board, the display developers decided to connect all the displays together. Therefore, if we want to light up element &#8216;C&#8217; on the display, then after applying power, all elements of &#8216;C&#8217; will light up. Figure 4 shows the individual segments of a display.<\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/ht\/hz\/5a\/hthz5avzci7oguatmj3ypqzzkly.png\" alt=\"Figure 4: The individual segments of a display.\" title=\"Figure 4: The individual segments of a display.\" width=\"200\" height=\"267\" data-src=\"https:\/\/habrastorage.org\/webt\/ht\/hz\/5a\/hthz5avzci7oguatmj3ypqzzkly.png\"\/><figcaption>Figure 4: The individual segments of a display.<\/figcaption><\/figure>\n<\/p>\n<p>The solution to this &#171;problem&#187; is very simple, we need to quickly switch between displays, lighting the necessary elements. This process is shown in Figure 5. The question comes up, with what frequency should we do this? By default, each FPGA has a clock generator that serves as a tool for synchronizing operations. On Cyclone IV, it operates at a frequency of 50 MHz. But if we switch displays at this speed, we will not have time to see the LED updates, and all displays will have the same combination. After experimenting, we came to the conclusion that the optimal refresh rate of the indicator is the FrequencyOfClock \/ (5*10^4) \u2248 10^3 updates per second.<\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/storage3\/47d\/93c\/64e\/47d93c64e1fe82795c545a87fa6d96f7.gif\" alt=\"Figure 5: Quick switching between displays.\" title=\"Figure 5: Quick switching between displays.\" width=\"412\" height=\"300\" data-src=\"https:\/\/habrastorage.org\/storage3\/47d\/93c\/64e\/47d93c64e1fe82795c545a87fa6d96f7.gif\"\/><figcaption>Figure 5: Quick switching between displays.<\/figcaption><\/figure>\n<\/p>\n<\/li>\n<li>\n<p>Buttons <\/p>\n<p>The problem is called &#171;button bounce&#187;. Button click occurs at an arbitrary time, therefore, relative to the rest of the circuit inside the FPGA, it is an asynchronous event. The change of the logical state on the input leg of the FPGA can coincide with the moment of switching the receiving trigger, and there is a possibility that the trigger will be in an undefined (&#171;non-digital&#187;) metastable state. Figure 6 shows the scheme of the key bounce.\u200b                                                                      <\/p>\n<\/li>\n<\/ul>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w780q1\/webt\/ro\/ri\/ai\/roriaipuibvjn2lcqqlwyfzzx_g.jpeg\" alt=\"Figure 6:  Scheme of the key bounce.\" title=\"Figure 6:  Scheme of the key bounce.\" width=\"300\" height=\"211\" data-src=\"https:\/\/habrastorage.org\/webt\/ro\/ri\/ai\/roriaipuibvjn2lcqqlwyfzzx_g.jpeg\" data-blurred=\"true\"\/><figcaption>Figure 6:  Scheme of the key bounce.<\/figcaption><\/figure>\n<p>The solution is to differentiate stable signals from false alarms using timer. You can read a detailed solution <a href=\"http:\/\/www.labfor.ru\/articles\/debouncer_verilog\" rel=\"noopener noreferrer nofollow\">here.<\/a><\/p>\n<h4>Demonstration<\/h4>\n<div class=\"tm-iframe_temp\" data-src=\"https:\/\/embedd.srv.habr.com\/iframe\/5ffdc28c05d782142ffea58f\" data-style=\"\" id=\"5ffdc28c05d782142ffea58f\" width=\"\"><\/div>\n<details class=\"spoiler\">\n<summary>Step-by-step instruction<\/summary>\n<div class=\"spoiler__content\">\n<p>Here is the step-by-step instruction, how to get the same result: <\/p>\n<p>1. Install Quartus Prime 18.1<\/p>\n<p>2. Open Quartus Prime 18.1<\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/5s\/d8\/fv\/5sd8fvdlvdhntywecsgxg0yfono.png\" alt=\"Quartus Prime 18.1\" title=\"Quartus Prime 18.1\" width=\"1920\" height=\"1030\" data-src=\"https:\/\/habrastorage.org\/webt\/5s\/d8\/fv\/5sd8fvdlvdhntywecsgxg0yfono.png\"\/><figcaption>Quartus Prime 18.1<\/figcaption><\/figure>\n<p>3. New project wizard<\/p>\n<p>4. Press &#171;Next&#187; (This section may not be displayed if you disabled it earlier).<\/p>\n<p>5. Choose directory for your project, set some name for project, set &#171;top&#187; as top-level entity. Press &#171;Next&#187; (Directory, Name, Top-Level Entity).<\/p>\n<p>6. Select &#171;Empty project&#187;. Press &#171;Next&#187; (Project type).<\/p>\n<p>7. Press &#171;Next&#187; (Add Files).<\/p>\n<p>8. Firstly, choose your device family in &#171;Family&#187; list. Secondly, select your device in the &#171;Available devices&#187; list (Usually device name is written on FPGA, in other words, on big black square). Finally, press &#171;Next&#187; (Family, Device &amp; Board Settings).<\/p>\n<p>9. Press &#171;Next&#187; (EDA Tool Settings).<\/p>\n<p>10. Press &#171;Finish&#187; (Summary).<\/p>\n<p>11. Create all files and copy paste corresponding code from GitHub <a href=\"https:\/\/github.com\/SyrexMinus\/Combinational_lock_code\/tree\/main\/Verilog%20code%20files\" rel=\"noopener noreferrer nofollow\">repository<\/a> using following approach: File -> New -> Verilog HDL -> OK -> copy paste the code -> File -> Save as&#8230; -> set corresponding to code name -> Save <\/p>\n<p><a href=\"https:\/\/github.com\/SyrexMinus\/Combinational_lock_code\" rel=\"noopener noreferrer nofollow\">Here<\/a> in README.md we placed description of the code<\/p>\n<p>12. Processing -> Start Compilation -> Wait for compilation to be finished<\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/1a\/n1\/vw\/1an1vwyglanz34ttbe1g9fjizpg.png\" alt=\"Compilation\" title=\"Compilation\" width=\"1920\" height=\"1030\" data-src=\"https:\/\/habrastorage.org\/webt\/1a\/n1\/vw\/1an1vwyglanz34ttbe1g9fjizpg.png\"\/><figcaption>Compilation<\/figcaption><\/figure>\n<\/p>\n<p>13. Assignments -> Pin planner.<\/p>\n<p>14. Now let&#8217;s assign pins to the inputs and outputs of the top module. You should examine the inscriptions on your board.<\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/su\/dq\/lb\/sudqlbqh1ir6rqghtgpcsxfektk.png\" alt=\"Pin connections\" title=\"Pin connections\" width=\"1327\" height=\"823\" data-src=\"https:\/\/habrastorage.org\/webt\/su\/dq\/lb\/sudqlbqh1ir6rqghtgpcsxfektk.png\"\/><figcaption>Pin connections<\/figcaption><\/figure>\n<p>Set the following pins for the anodes:<\/p>\n<p>&#8212; anode[0] \u2014 pin of BIT0 (most right digit)<\/p>\n<p>&#8212; anode[1] \u2014 pin of BIT1<\/p>\n<p>&#8212; &#8230;<\/p>\n<p>&#8212; anode[7] \u2014 pin of BIT7 (most left digit)<\/p>\n<\/p>\n<p>&#8212; button_increase \u2014 pin of some button 1. This button will increase selected digit.<\/p>\n<p>&#8212; button_left \u2014 pin of some button 2. This button will shift selection to more left digit.<\/p>\n<p>&#8212; button_next \u2014 pin of some button 3. This button will move to the next state of the combinational lock.<\/p>\n<\/p>\n<p>&#8212; cathode[0] \u2014 pin of A cathode<\/p>\n<p>&#8212; cathode[1] \u2014 pin of B cathode<\/p>\n<p>&#8212; &#8230;<\/p>\n<p>&#8212; cathode[7] \u2014 pin of H (DP) cathode<\/p>\n<\/p>\n<p>&#8212; clk \u2014 pin of CLK_50M(it could have different name of your plate, important that it should contain part &#171;CLK&#187;)<\/p>\n<\/p>\n<p>&#8212; lights[0] \u2014 pin of some light-emitting diode 1. It will indicate state 1<\/p>\n<p>&#8212; lights[1] \u2014 pin of some light-emitting diode 2. It will indicate state 2<\/p>\n<p>&#8212; &#8230;<\/p>\n<p>&#8212; lights[4] \u2014 pin of some light-emitting diode 5. It will indicate state 5<\/p>\n<\/p>\n<p>Pin planner will looks like that:<\/p>\n<figure class=\"\"><img loading=\"lazy\" decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/webt\/_3\/zm\/mq\/_3zmmqltwd2xpcaikegcjtxpfo8.png\" alt=\"Pin planner\" title=\"Pin planner\" width=\"1920\" height=\"1030\" data-src=\"https:\/\/habrastorage.org\/webt\/_3\/zm\/mq\/_3zmmqltwd2xpcaikegcjtxpfo8.png\"\/><figcaption>Pin planner<\/figcaption><\/figure>\n<\/p>\n<p>15. Close Pin planner.<\/p>\n<p>16. Tools -> Programmer -> Hardware setup -> Select your device (if you do not see it, make sure that you connected device to your PC and installed drivers for it. We installed drivers using <a href=\"https:\/\/www.youtube.com\/watch?v=qzTRw6xtZ3E\" rel=\"noopener noreferrer nofollow\">this<\/a> guide)<\/p>\n<p>17. Close Hardware setup.<\/p>\n<p>18. Press Start.<\/p>\n<p>19. Done, combinational lock installed on your device!<\/p>\n<\/div>\n<\/details>\n<h4>Conclusion<\/h4>\n<p>We described the key implement stages of a passcode-protection mechanism by using an FPGA board, Quartus Prime software and Verilog hardware description language. This work has been implemented in the scope of \u00abComputer Architecture\u00bb course in the <a href=\"https:\/\/innopolis.university\/en\/\" rel=\"noopener noreferrer nofollow\">Innopolis University<\/a>. The proposed implementation can be extended for usage in the industry application and for education process.<\/p>\n<h4>Acknowledgments<\/h4>\n<p>The authors would like to express gratitude to our professors <a href=\"https:\/\/ru.linkedin.com\/in\/artem-burmyakov-5597838\" rel=\"noopener noreferrer nofollow\">Artem Burmyakov<\/a>, <a href=\"https:\/\/scholar.google.com\/citations?user=HFp8hzMAAAAJ&amp;hl=en\" rel=\"noopener noreferrer nofollow\">Muhammad Fahim<\/a>, <a href=\"https:\/\/scholar.google.com\/citations?user=bsy2_u0AAAAJ&amp;hl=en\" rel=\"noopener noreferrer nofollow\">Alexander Tormasov<\/a>  and to our teacher assitant <a href=\"https:\/\/github.com\/vladostan\/comparchitecture\" rel=\"noopener noreferrer nofollow\">Vlad Ostankovich<\/a> for giving us deep knowledge and possibility to use it in practice. <\/p>\n<h4>References<\/h4>\n<p>\u200b    [1] <a href=\"https:\/\/github.com\/SyrexMinus\/Combinational_lock_code\" rel=\"noopener noreferrer nofollow\">Project on the GitHub<\/a><\/p>\n<p>\u200b    [2] <a href=\"http:\/\/www.labfor.ru\/articles\/debouncer_verilog\" rel=\"noopener noreferrer nofollow\">Debouncer using Verilog<\/a><\/p>\n<p>\u200b    [3] <a href=\"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/misc\/fpgas-for-dummies-ebook.pdf\" rel=\"noopener noreferrer nofollow\">FPGAs For Dummies<\/a><\/p>\n<p>\u200b    [4] <a href=\"https:\/\/fpgasoftware.intel.com\/18.1\/?edition=lite&amp;platform=windows\" rel=\"noopener noreferrer nofollow\">Quartus Prime Lite Edition<\/a><\/p>\n<p>    [5] <a href=\"https:\/\/www.youtube.com\/watch?v=qzTRw6xtZ3E\" rel=\"noopener noreferrer nofollow\">Driver installation<\/a><\/p>\n<\/p>\n<\/div>\n<\/div>\n<\/div>\n<p><!----><!----><\/div>\n<p><!----><!----><br \/> \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438 <a href=\"https:\/\/habr.com\/ru\/articles\/537042\/\"> https:\/\/habr.com\/ru\/articles\/537042\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<div><!--[--><!--]--><\/div>\n<div id=\"post-content-body\">\n<div>\n<div class=\"article-formatted-body article-formatted-body article-formatted-body_version-2\">\n<div xmlns=\"http:\/\/www.w3.org\/1999\/xhtml\">\n<h2>Passcode Data Protection by Using FPGA and Verilog<\/h2>\n<h4>Authors<\/h4>\n<p><a href=\"https:\/\/github.com\/art22m\" rel=\"noopener noreferrer nofollow\">Artem Murashko<\/a>, <a href=\"https:\/\/github.com\/SyrexMinus\" rel=\"noopener noreferrer nofollow\">Makar Shevchenko<\/a> and <a href=\"https:\/\/github.com\/aalexren\" rel=\"noopener noreferrer nofollow\">Artem Chernitsa<\/a>.<\/p>\n<h4>Introduction<\/h4>\n<p>There are many situations when you need to protect your data, and different tools can be used to do that. For example, a safe. We develop a passcode data protection mechanism by using an FPGA board and Quartus Prime software. It allows demonstrating the basic concepts of a combination lock such as entering data, setting and checking a passcode, and displaying data.<\/p>\n<h4>Hardware and software used<\/h4>\n<p>Our project is implemented by using following devices and technologies: <\/p>\n<figure class=\"\"><figcaption> Figure 1: The schematic representation of an FPGA board. <\/figcaption><\/figure>\n<\/p>\n<ul>\n<li>\n<p>Cyclone IV FPGA Device<\/p>\n<p>\u200b    Buttons (input device)<\/p>\n<p>\u200b    LEDs and 7-Segment display (output device)<\/p>\n<p>\u200b    Power Supply port (used to power FPGA board)<\/p>\n<p>\u200b    USB Blaster connector (used to upload firmware)<\/p>\n<\/li>\n<li>\n<p>Quartus Prime Lite Edition 18.1<\/p>\n<p>\u200b    Verilog HDL  <\/p>\n<\/li>\n<li>\n<p>Altera USB Blaster (USB Blaster transfers configuration data from PC to FPGA)<\/p>\n<\/li>\n<\/ul>\n<h4>Technical implementation<\/h4>\n<ul>\n<li>\n<p>Schematic representation of program execution<\/p>\n<p>The diagram in Figure 2 shows the flow of the program. The circles are states, arrows are transition conditions.<\/p>\n<\/li>\n<\/ul>\n<figure class=\"bordered\"><figcaption> Figure 2: The flowchart of the program. <\/figcaption><\/figure>\n<\/p>\n<ul>\n<li>\n<p>Displaying the state of the program<\/p>\n<p>We used LEDs to display the current state of the program. Cyclone IV FPGA board have 12 LEDs and each LED has its own number. Figure 3 shows the LEDs arrangement.<\/p>\n<\/li>\n<\/ul>\n<figure class=\"float\"><figcaption>Figure 3: LEDs arrangement.    <\/figcaption><\/figure>\n<p>                                                                                                                              D4 to indicate the state &#171;Enter data to be saved&#187;;                                                                                         D7 to indicate the state &#171;Set up the passcode&#187;;                                                        D10 to indicate the state &#171;Enter the passcode&#187;;                                                          D13 to indicate the state &#171;Show data has been saved&#187;;<\/p>\n<p>\u200b     <\/p>\n<ul>\n<li>\n<p>7-Segment display<\/p>\n<p>If we want to bind each cathode (stick) to the registers, than it would take 8*8=64 power tracks for each display. To save space on the board, the display developers decided to connect all the displays together. Therefore, if we want to light up element &#8216;C&#8217; on the display, then after applying power, all elements of &#8216;C&#8217; will light up. Figure 4 shows the individual segments of a display.<\/p>\n<figure class=\"\"><figcaption>Figure 4: The individual segments of a display.<\/figcaption><\/figure>\n<\/p>\n<p>The solution to this &#171;problem&#187; is very simple, we need to quickly switch between displays, lighting the necessary elements. This process is shown in Figure 5. The question comes up, with what frequency should we do this? By default, each FPGA has a clock generator that serves as a tool for synchronizing operations. On Cyclone IV, it operates at a frequency of 50 MHz. But if we switch displays at this speed, we will not have time to see the LED updates, and all displays will have the same combination. After experimenting, we came to the conclusion that the optimal refresh rate of the indicator is the FrequencyOfClock \/ (5*10^4) \u2248 10^3 updates per second.<\/p>\n<figure class=\"\"><figcaption>Figure 5: Quick switching between displays.<\/figcaption><\/figure>\n<\/p>\n<\/li>\n<li>\n<p>Buttons <\/p>\n<p>The problem is called &#171;button bounce&#187;. Button click occurs at an arbitrary time, therefore, relative to the rest of the circuit inside the FPGA, it is an asynchronous event. The change of the logical state on the input leg of the FPGA can coincide with the moment of switching the receiving trigger, and there is a possibility that the trigger will be in an undefined (&#171;non-digital&#187;) metastable state. Figure 6 shows the scheme of the key bounce.\u200b                                                                      <\/p>\n<\/li>\n<\/ul>\n<figure class=\"\"><figcaption>Figure 6:  Scheme of the key bounce.<\/figcaption><\/figure>\n<p>The solution is to differentiate stable signals from false alarms using timer. You can read a detailed solution <a href=\"http:\/\/www.labfor.ru\/articles\/debouncer_verilog\" rel=\"noopener noreferrer nofollow\">here.<\/a><\/p>\n<h4>Demonstration<\/h4>\n<div class=\"tm-iframe_temp\" data-src=\"https:\/\/embedd.srv.habr.com\/iframe\/5ffdc28c05d782142ffea58f\" data-style=\"\" id=\"5ffdc28c05d782142ffea58f\" width=\"\"><\/div>\n<details class=\"spoiler\">\n<summary>Step-by-step instruction<\/summary>\n<div class=\"spoiler__content\">\n<p>Here is the step-by-step instruction, how to get the same result: <\/p>\n<p>1. Install Quartus Prime 18.1<\/p>\n<p>2. Open Quartus Prime 18.1<\/p>\n<figure class=\"\"><figcaption>Quartus Prime 18.1<\/figcaption><\/figure>\n<p>3. New project wizard<\/p>\n<p>4. Press &#171;Next&#187; (This section may not be displayed if you disabled it earlier).<\/p>\n<p>5. Choose directory for your project, set some name for project, set &#171;top&#187; as top-level entity. Press &#171;Next&#187; (Directory, Name, Top-Level Entity).<\/p>\n<p>6. Select &#171;Empty project&#187;. Press &#171;Next&#187; (Project type).<\/p>\n<p>7. Press &#171;Next&#187; (Add Files).<\/p>\n<p>8. Firstly, choose your device family in &#171;Family&#187; list. Secondly, select your device in the &#171;Available devices&#187; list (Usually device name is written on FPGA, in other words, on big black square). Finally, press &#171;Next&#187; (Family, Device &amp; Board Settings).<\/p>\n<p>9. Press &#171;Next&#187; (EDA Tool Settings).<\/p>\n<p>10. Press &#171;Finish&#187; (Summary).<\/p>\n<p>11. Create all files and copy paste corresponding code from GitHub <a href=\"https:\/\/github.com\/SyrexMinus\/Combinational_lock_code\/tree\/main\/Verilog%20code%20files\" rel=\"noopener noreferrer nofollow\">repository<\/a> using following approach: File -> New -> Verilog HDL -> OK -> copy paste the code -> File -> Save as&#8230; -> set corresponding to code name -> Save <\/p>\n<p><a href=\"https:\/\/github.com\/SyrexMinus\/Combinational_lock_code\" rel=\"noopener noreferrer nofollow\">Here<\/a> in README.md we placed description of the code<\/p>\n<p>12. Processing -> Start Compilation -> Wait for compilation to be finished<\/p>\n<figure class=\"\"><figcaption>Compilation<\/figcaption><\/figure>\n<\/p>\n<p>13. Assignments -> Pin planner.<\/p>\n<p>14. Now let&#8217;s assign pins to the inputs and outputs of the top module. You should examine the inscriptions on your board.<\/p>\n<figure class=\"\"><figcaption>Pin connections<\/figcaption><\/figure>\n<p>Set the following pins for the anodes:<\/p>\n<p>&#8212; anode[0] \u2014 pin of BIT0 (most right digit)<\/p>\n<p>&#8212; anode[1] \u2014 pin of BIT1<\/p>\n<p>&#8212; &#8230;<\/p>\n<p>&#8212; anode[7] \u2014 pin of BIT7 (most left digit)<\/p>\n<\/p>\n<p>&#8212; button_increase \u2014 pin of some button 1. This button will increase selected digit.<\/p>\n<p>&#8212; button_left \u2014 pin of some button 2. This button will shift selection to more left digit.<\/p>\n<p>&#8212; button_next \u2014 pin of some button 3. This button will move to the next state of the combinational lock.<\/p>\n<\/p>\n<p>&#8212; cathode[0] \u2014 pin of A cathode<\/p>\n<p>&#8212; cathode[1] \u2014 pin of B cathode<\/p>\n<p>&#8212; &#8230;<\/p>\n<p>&#8212; cathode[7] \u2014 pin of H (DP) cathode<\/p>\n<\/p>\n<p>&#8212; clk \u2014 pin of CLK_50M(it could have different name of your plate, important that it should contain part &#171;CLK&#187;)<\/p>\n<\/p>\n<p>&#8212; lights[0] \u2014 pin of some light-emitting diode 1. It will indicate state 1<\/p>\n<p>&#8212; lights[1] \u2014 pin of some light-emitting diode 2. It will indicate state 2<\/p>\n<p>&#8212; &#8230;<\/p>\n<p>&#8212; lights[4] \u2014 pin of some light-emitting diode 5. It will indicate state 5<\/p>\n<\/p>\n<p>Pin planner will looks like that:<\/p>\n<figure class=\"\"><figcaption>Pin planner<\/figcaption><\/figure>\n<\/p>\n<p>15. Close Pin planner.<\/p>\n<p>16. Tools -> Programmer -> Hardware setup -> Select your device (if you do not see it, make sure that you connected device to your PC and installed drivers for it. We installed drivers using <a href=\"https:\/\/www.youtube.com\/watch?v=qzTRw6xtZ3E\" rel=\"noopener noreferrer nofollow\">this<\/a> guide)<\/p>\n<p>17. Close Hardware setup.<\/p>\n<p>18. Press Start.<\/p>\n<p>19. Done, combinational lock installed on your device!<\/p>\n<\/div>\n<\/details>\n<h4>Conclusion<\/h4>\n<p>We described the key implement stages of a passcode-protection mechanism by using an FPGA board, Quartus Prime software and Verilog hardware description language. This work has been implemented in the scope of \u00abComputer Architecture\u00bb course in the <a href=\"https:\/\/innopolis.university\/en\/\" rel=\"noopener noreferrer nofollow\">Innopolis University<\/a>. The proposed implementation can be extended for usage in the industry application and for education process.<\/p>\n<h4>Acknowledgments<\/h4>\n<p>The authors would like to express gratitude to our professors <a href=\"https:\/\/ru.linkedin.com\/in\/artem-burmyakov-5597838\" rel=\"noopener noreferrer nofollow\">Artem Burmyakov<\/a>, <a href=\"https:\/\/scholar.google.com\/citations?user=HFp8hzMAAAAJ&amp;hl=en\" rel=\"noopener noreferrer nofollow\">Muhammad Fahim<\/a>, <a href=\"https:\/\/scholar.google.com\/citations?user=bsy2_u0AAAAJ&amp;hl=en\" rel=\"noopener noreferrer nofollow\">Alexander Tormasov<\/a>  and to our teacher assitant <a href=\"https:\/\/github.com\/vladostan\/comparchitecture\" rel=\"noopener noreferrer nofollow\">Vlad Ostankovich<\/a> for giving us deep knowledge and possibility to use it in practice. <\/p>\n<h4>References<\/h4>\n<p>\u200b    [1] <a href=\"https:\/\/github.com\/SyrexMinus\/Combinational_lock_code\" rel=\"noopener noreferrer nofollow\">Project on the GitHub<\/a><\/p>\n<p>\u200b    [2] <a href=\"http:\/\/www.labfor.ru\/articles\/debouncer_verilog\" rel=\"noopener noreferrer nofollow\">Debouncer using Verilog<\/a><\/p>\n<p>\u200b    [3] <a href=\"https:\/\/www.intel.com\/content\/dam\/www\/programmable\/us\/en\/pdfs\/literature\/misc\/fpgas-for-dummies-ebook.pdf\" rel=\"noopener noreferrer nofollow\">FPGAs For Dummies<\/a><\/p>\n<p>\u200b    [4] <a href=\"https:\/\/fpgasoftware.intel.com\/18.1\/?edition=lite&amp;platform=windows\" rel=\"noopener noreferrer nofollow\">Quartus Prime Lite Edition<\/a><\/p>\n<p>    [5] <a href=\"https:\/\/www.youtube.com\/watch?v=qzTRw6xtZ3E\" rel=\"noopener noreferrer nofollow\">Driver installation<\/a><\/p>\n<\/p>\n<\/div>\n<\/div>\n<\/div>\n<p><!----><!----><\/div>\n<p><!----><!----><br \/> \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438 <a href=\"https:\/\/habr.com\/ru\/articles\/537042\/\"> https:\/\/habr.com\/ru\/articles\/537042\/<\/a><br \/><\/br><\/br><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-380303","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/380303","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=380303"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/380303\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=380303"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=380303"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=380303"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}