{"id":381488,"date":"2024-06-29T03:41:42","date_gmt":"2024-06-29T03:41:42","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=381488"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=381488","title":{"rendered":"FPGA Weekly News #002<\/span>"},"content":{"rendered":"
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\u0420\u0435\u0431\u044f\u0442\u0430 \u0438\u0437\u00a0FPGA \u043a\u043e\u043c\u0443\u043d\u0438\u0442\u0438<\/a>\u00a0\u043a\u0430\u0436\u0434\u044b\u0439 \u0434\u0435\u043d\u044c \u0434\u0435\u043b\u0430\u044e\u0442\u00a0\u043d\u0435\u0431\u043e\u043b\u044c\u0448\u0443\u044e \u043f\u043e\u0434\u0431\u043e\u0440\u043a\u0443 \u043d\u043e\u0432\u043e\u0441\u0442\u0435\u0439<\/a>\u00a0\u0438\u0437 \u043c\u0438\u0440\u0430 FPGA \u0438 \u0440\u0435\u0448\u0438\u043b\u0438 \u043f\u043e\u0434\u0435\u043b\u0438\u0442\u044c\u0441\u044f \u0435\u044e \u0441 \u0447\u0438\u0442\u0430\u0442\u0435\u043b\u044f\u043c\u0438 \u0445\u0430\u0431\u0430 FPGA.\u00a0\u0412\u043d\u0438\u043c\u0430\u043d\u0438\u0435: \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u044b \u043f\u043e\u0432\u0442\u043e\u0440\u044b!<\/strong><\/p>\n

\"HABR
HABR FPGA weekly<\/figcaption><\/figure>\n

\u0421\u0432\u0435\u0436\u0438\u0435 \u043e\u0442\u0435\u0447\u0435\u0441\u0442\u0432\u0435\u043d\u043d\u044b\u0435 \u0441\u0442\u0430\u0442\u044c\u0438<\/h2>\n
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    \u041e\u0441\u043d\u043e\u0432\u044b \u0441\u0442\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u043d\u043e\u0433\u043e \u0430\u043d\u0430\u043b\u0438\u0437\u0430. \u0427\u0430\u0441\u0442\u044c 2.1: System Synchronous Input Delay Constraint<\/a>.<\/p>\n<\/li>\n

  2. \n

    \u0418\u0433\u0440\u0430 «Create FPGA content»<\/a><\/p>\n<\/li>\n

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    \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u0430\u0437\u043e\u0432\u044b\u0445 \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u043e\u0432 \u0426\u041e\u0421: \u041a\u0418\u0425 \u0444\u0438\u043b\u044c\u0442\u0440<\/a><\/p>\n<\/li>\n

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    \u0422\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u044f \u0432\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u044b\u0445 FPGA (eFPGA): \u043f\u0440\u043e\u0448\u043b\u043e\u0435 \u043d\u0430\u0441\u0442\u043e\u044f\u0449\u0435\u0435 \u0438 \u0431\u0443\u0434\u0443\u0449\u0435\u0435<\/a><\/p>\n<\/li>\n

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    FIFO \u0434\u043b\u044f \u0441\u0430\u043c\u044b\u0445 \u043c\u0430\u043b\u0435\u043d\u044c\u043a\u0438\u0445 (\u0432\u043c\u0435\u0441\u0442\u0435 \u0441 \u0432\u043e\u043f\u0440\u043e\u0441\u0430\u043c\u0438 \u043d\u0430 \u0438\u043d\u0442\u0435\u0440\u0432\u044c\u044e)<\/a><\/p>\n<\/li>\n

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    \u041a\u0430\u043a \u043f\u0440\u043e\u0448\u043b\u0430 \u041f\u041b\u0418\u0421\u043e\u0432\u0430\u044f \u043a\u043e\u043d\u0444\u0435\u0440\u0435\u043d\u0446\u0438\u044f \u0432 \u041f\u0438\u0442\u0435\u0440\u0435?<\/a><\/p>\n<\/li>\n

  7. \n

    \u041d\u0430\u0432\u043e\u0434\u0438\u043c \u043a\u0440\u0430\u0441\u043e\u0442\u0443 \u0432 \u043a\u043e\u0434\u0435 \u0434\u043b\u044f \u041f\u041b\u0418\u0421 Lattice, \u043f\u043e\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u043e\u043c \u043d\u0430 \u0431\u0430\u0437\u0435 \u043f\u0430\u043a\u0435\u0442\u0430 LiteX<\/a><\/p>\n<\/li>\n<\/ol>\n

    \u041e\u0441\u0442\u0430\u043b\u044c\u043d\u043e\u0435 \u0430\u043d\u0433\u043b\u043e\u044f\u0437\u044b\u0447\u043d\u043e\u0435<\/h2>\n
      \n
    1. \n

      CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs<\/a><\/p>\n<\/li>\n

    2. \n

      Semtech Speeds Development of Digital Receiver FPGAs and ASICs — MATLAB & Simulink<\/a><\/p>\n<\/li>\n

    3. \n

      Scaling Suricata Performance to 100 Gbps with Napatech SmartNICs<\/a><\/p>\n<\/li>\n

    4. \n

      Enclustra FPGA Solutions | Mercury+ XU6 | Xilinx Zynq UltraScale+ MPSoC Module | System-on-Chip (SoC) Module | System-on-Module (SOM) | ZU2CG | ZU2EG | ZU3EG | ZU4CG | ZU4EV | ZU5EV<\/a><\/p>\n<\/li>\n

    5. \n

      Building a SoC with Litex. \u2013 controlpaths.<\/a><\/p>\n<\/li>\n

    6. \n

      Antmicro \u00b7 Open source keystroke injector implementation on the Fomu FPGA board<\/a><\/p>\n<\/li>\n

    7. \n

      MicroZed Chronicles: Versal Part Two \u2013 Device Architecture<\/a><\/p>\n<\/li>\n

    8. \n

      An FPGA Based Multi-Sensor Atmospheric Testing Device for Confined Spaces | IEEE Conference Publication | IEEE Xplore<\/a><\/p>\n<\/li>\n

    9. \n

      Utilizing Fine Line PCBs with High Density BGAs | Signal Integrity Journal<\/a><\/p>\n<\/li>\n

    10. \n

      3x n2disk Performance Increase for Intel PAC<\/a><\/p>\n<\/li>\n

    11. \n

      Imagination and Andes jointly validate GPU with RISC-V CPU IP<\/a><\/p>\n<\/li>\n

    12. \n

      PMIC Solutions<\/a><\/p>\n<\/li>\n

    13. \n

      tinyML Talks webcast: FFConv: An FPGA-based Accelerator for Fast Convolution Layers in Convolutional Neural Network<\/a><\/p>\n<\/li>\n

    14. \n

      Accelerate AI applications using VITIS AI on Xilinx ZynqMP UltraScale+ FPGA — Softnautics<\/a><\/p>\n<\/li>\n

    15. \n

      Lattice Propel System Design Environment<\/a><\/p>\n<\/li>\n

    16. \n

      HAFLANG — Hardware Acceleration of Functional Languages<\/a><\/p>\n<\/li>\n

    17. \n

      Electronics | Free Full-Text | Novel FPGA-Based Visual Stimulation Method for Eye Movement Analysis | HTML<\/a><\/p>\n<\/li>\n

    18. \n

      Working with Block Diagram\/Schematic Files — Verilog Development Tutorial p.3 — YouTube<\/a><\/p>\n<\/li>\n

    19. \n

      Migration from Xilinx Spartan-6 FPGA — Sandeepani<\/a><\/p>\n<\/li>\n

    20. \n

      FPGA opensource Ecosystem | LinkedIn<\/a><\/p>\n<\/li>\n

    21. \n

      Powerful Test & Measurement up to 100G Line Rate<\/a><\/p>\n<\/li>\n

    22. \n

      What is ASIC — FPGA — SoC? | Explanation, Differences & Applications — YouTube<\/a><\/p>\n<\/li>\n

    23. \n

      Open-Source Oscilloscope Demo Video — YouTube<\/a><\/p>\n<\/li>\n

    24. \n

      RDMA RoCE v2 IP by Grovf | How is it Unique? | by Astghik Nalchajyan | grovf | Jan, 2022 | Medium<\/a><\/p>\n<\/li>\n

    25. \n

      Robotics<\/a><\/p>\n<\/li>\n

    26. \n

      Enclustra FPGA Solutions | Mercury+ XU6 | Xilinx Zynq UltraScale+ MPSoC Module | System-on-Chip (SoC) Module | System-on-Module (SOM) | ZU2CG | ZU2EG | ZU3EG | ZU4CG | ZU4EV | ZU5EV<\/a><\/p>\n<\/li>\n

    27. \n

      FPGA technology and Supply Chain Cyber Security — cyrene<\/a><\/p>\n<\/li>\n

    28. \n

      TH53\/TH53L FPGA Crypto Mining Boards ETH Mining Demo — YouTube<\/a><\/p>\n<\/li>\n

    29. \n

      Campera-ES Utility Library on GitHub! | LinkedIn<\/a><\/p>\n<\/li>\n

    30. \n

      System on modules | TOPIC Embedded Systems<\/a><\/p>\n<\/li>\n

    31. \n

      WebTech Janvier ENG<\/a><\/p>\n<\/li>\n

    32. \n

      HandsOn Training — FPGA Security Bootcamp<\/a><\/p>\n<\/li>\n

    33. \n

      DSP basic — FIR filter + UVM — FPGA-Systems<\/a><\/p>\n<\/li>\n

    34. \n

      Event Lobby (EVENT: 3549953)<\/a><\/p>\n<\/li>\n

    35. \n

      FFT development on an FPGA — Simulation Design Flow using Vivado Software and Zynq Processor. — YouTube<\/a><\/p>\n<\/li>\n

    36. \n

      VHDL VERIFICATION \u2013 Mehmet Burak Aykenar<\/a><\/p>\n<\/li>\n

    37. \n

      Mercury ACAP eBook Final<\/a><\/p>\n<\/li>\n

    38. \n

      fpga-operator 2.7.4 \u00b7 inaccel\/inaccel<\/a><\/p>\n<\/li>\n

    39. \n

      Embedded Processor Market 2021-26: Share, Scope, Growth, Demand And Forecast | LinkedIn<\/a><\/p>\n<\/li>\n

    40. \n

      FAST Project<\/a><\/p>\n<\/li>\n

    41. \n

      Spartan-6 Replacement using Microchip<\/a><\/p>\n<\/li>\n

    42. \n

      028 — Standalone Simulation in Vivado (2) | RTL Audio Lab<\/a><\/p>\n<\/li>\n

    43. \n

      Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals — CNX Software<\/a><\/p>\n<\/li>\n

    44. \n

      Events — Company — Aldec<\/a><\/p>\n<\/li>\n

    45. \n

      Campera-ES Utility Library on GitHub! | LinkedIn<\/a><\/p>\n<\/li>\n

    46. \n

      Introduction to FPGA Part 10 — Metastability and Clock Domain Crossing | Digi-Key Electronics — YouTube<\/a><\/p>\n<\/li>\n

    47. \n

      xDNN: Inference for Deep Convolutional Neural Networks | ACM Transactions on Reconfigurable Technology and Systems<\/a><\/p>\n<\/li>\n

    48. \n

      Mouser Electronics Signs Global Distribution Deal with Liquid Instruments, Offers Moku FPGA-Based Testing Platforms<\/a><\/p>\n<\/li>\n

    49. \n

      Scaling Suricata Performance to 100 Gbps with Napatech SmartNICs<\/a><\/p>\n<\/li>\n

    50. \n

      DAC 2021 — Embedded FPGA IP from Menta — SemiWiki<\/a><\/p>\n<\/li>\n

    51. \n

      Home | SiliconCompiler<\/a><\/p>\n<\/li>\n

    52. \n

      Getting started \u2014 TerosHDL 2.0.1 documentation<\/a><\/p>\n<\/li>\n

    53. \n

      tinyML Talks webcast: FFConv: An FPGA-based Accelerator for Fast Convolution Layers in Convolutional Neural Network<\/a><\/p>\n<\/li>\n

    54. \n

      Synective Labs & Chalmers Launch FPGA Project Course — Recab<\/a><\/p>\n<\/li>\n

    55. \n

      Entropy | Free Full-Text | Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source<\/a><\/p>\n<\/li>\n

    56. \n

      Speed up your R&D processes with Red Pitaya<\/a><\/p>\n<\/li>\n

    57. \n

      Microcontroller in FPGA? This is how to do it … | Step by Step Tutorial | Adam Taylor — YouTube<\/a><\/p>\n<\/li>\n

    58. \n

      Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals — CNX Software<\/a><\/p>\n<\/li>\n

    59. \n

      Issue 14: Accelerated Verification of Block-Based FPGA Designs | Blue Pearl Software Inc.<\/a><\/p>\n<\/li>\n

    60. \n

      Industrial Robotics System Veo FreeMove* Using Intel FPGAs<\/a><\/p>\n<\/li>\n

    61. \n

      SAFE VPN10G-PCIe | sitehop<\/a><\/p>\n<\/li>\n

    62. \n

      Get Your Code Future-Ready with FREE Technical Webinars<\/a><\/p>\n<\/li>\n

    63. \n

      Intel\u00ae FPGA Technical Training<\/a><\/p>\n<\/li>\n

    64. \n

      Efinix, Inc. | Titanium Ti60 F225 Development Kit<\/a>UVM kit<\/a><\/p>\n<\/li>\n

    65. \n

      tinyML Talks: CFU Playground: Customize Your ML Processor for Your Specific TinyML Model — YouTube<\/a><\/p>\n<\/li>\n

    66. \n

      Prototype and Adjust a Deep Learning Network on FPGA Video — MATLAB & Simulink<\/a><\/p>\n<\/li>\n

    67. \n

      Xilinx Technologies for New Space \/ Space 2.0<\/a><\/p>\n<\/li>\n

    68. \n

      filtering with FPGA using object oriented design principles in VHDL — YouTube<\/a><\/p>\n<\/li>\n

    69. \n

      SystemVerilog Test Bench Transaction Class #verilog #uvm #semiconductor #vlsi #systemverilog — YouTube<\/a><\/p>\n<\/li>\n

    70. \n

      LiFi #2 — Behavioral Modules — Blog — Summer of FPGA — element14 Community<\/a><\/p>\n<\/li>\n

    71. \n

      FPGA Mining vs ASIC Mining: What Is More Profitable? | LetsExchange.io<\/a><\/p>\n<\/li>\n

    72. \n

      Rapixo CL Pro | Camera Link Frame Grabbers | Matrox Imaging<\/a><\/p>\n<\/li>\n

    73. \n

      A Tunable Parameter, High Linearity Time-to-Digital Converter Implemented in 28-nm FPGA | IEEE Journals & Magazine | IEEE Xplore<\/a><\/p>\n<\/li>\n

    74. \n

      Course Schedule | Microsemi<\/a><\/p>\n<\/li>\n

    75. \n

      Simulating and downloading a PIC circuit to Xilinx FPGA boards using TINACloud — YouTube<\/a><\/p>\n<\/li>\n

    76. \n

      AXI4-FULL AXI4-LITE and UART INTERFACE SIMULATION in MODELSIM with UVVM LIBRARY \u2013 Mehmet Burak Aykenar<\/a><\/p>\n<\/li>\n

    77. \n

      Efinix Demonstration of Using Titanium FPGAs with Quantum Acceleration to Optimize Edge AI Performance while Reducing Time to Market — Edge AI and Vision Alliance<\/a><\/p>\n<\/li>\n

    78. \n

      Lattice, Lenovo technology integration will usher in new era of smart PC\u2019s \u2013 PCR<\/a><\/p>\n<\/li>\n

    79. \n

      Programming Your First FPGA — Verilog Development Tutorial p.2 — YouTube<\/a><\/p>\n<\/li>\n

    80. \n

      FPGA — Developing new Hardware |\u00a0Concept Reply<\/a><\/p>\n<\/li>\n

    81. \n

      Google, Purdue & Harvard U\u2019s Open-Source Framework for TinyML Achieves up to 75x Speedups on FPGAs | Synced<\/a><\/p>\n<\/li>\n

    82. \n

      Xylon releases a new version of its MPSoC IP Framework for Multi-Camera Vision Applications<\/a><\/p>\n<\/li>\n

    83. \n

      FM-S14 | FTL<\/a><\/p>\n<\/li>\n

    84. \n

      20220111 FPGA standup — YouTube<\/a><\/p>\n<\/li>\n

    85. \n

      Using FPGA I\/O Optimization to Design PCBs More Cost Effectively | Siemens Digital Industries Software<\/a><\/p>\n<\/li>\n

    86. \n

      Promwad Advances Industrial Switch Design With Microchip SoC<\/a><\/p>\n<\/li>\n

    87. \n

      supratimdas\/NoobsCpu-8bit: A simple 8bit CPU.<\/a><\/p>\n<\/li>\n

    88. \n

      Image Recognition for Industrial Inspection using Deep Learning on FPGAs & SoCs | LinkedIn<\/a><\/p>\n<\/li>\n

    89. \n

      Introduction of XC series chip in FPGA Embedded | ABNewswire<\/a><\/p>\n<\/li>\n

    90. \n

      Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US) — Marketing EDA<\/a><\/p>\n<\/li>\n

    91. \n

      Industry\u2019s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance — 2022-01-13 — Newsroom — Company — Aldec<\/a><\/p>\n<\/li>\n<\/ol>\n<\/div>\n<\/div>\n<\/div>\n

      <\/div>\n


      \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438       https:\/\/habr.com\/ru\/articles\/646903\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

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      \u0420\u0435\u0431\u044f\u0442\u0430 \u0438\u0437\u00a0FPGA \u043a\u043e\u043c\u0443\u043d\u0438\u0442\u0438<\/a>\u00a0\u043a\u0430\u0436\u0434\u044b\u0439 \u0434\u0435\u043d\u044c \u0434\u0435\u043b\u0430\u044e\u0442\u00a0\u043d\u0435\u0431\u043e\u043b\u044c\u0448\u0443\u044e \u043f\u043e\u0434\u0431\u043e\u0440\u043a\u0443 \u043d\u043e\u0432\u043e\u0441\u0442\u0435\u0439<\/a>\u00a0\u0438\u0437 \u043c\u0438\u0440\u0430 FPGA \u0438 \u0440\u0435\u0448\u0438\u043b\u0438 \u043f\u043e\u0434\u0435\u043b\u0438\u0442\u044c\u0441\u044f \u0435\u044e \u0441 \u0447\u0438\u0442\u0430\u0442\u0435\u043b\u044f\u043c\u0438 \u0445\u0430\u0431\u0430 FPGA.\u00a0\u0412\u043d\u0438\u043c\u0430\u043d\u0438\u0435: \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u044b \u043f\u043e\u0432\u0442\u043e\u0440\u044b!<\/strong><\/p>\n

      HABR FPGA weekly<\/figcaption><\/figure>\n

      \u0421\u0432\u0435\u0436\u0438\u0435 \u043e\u0442\u0435\u0447\u0435\u0441\u0442\u0432\u0435\u043d\u043d\u044b\u0435 \u0441\u0442\u0430\u0442\u044c\u0438<\/h2>\n
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        \u041e\u0441\u043d\u043e\u0432\u044b \u0441\u0442\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u043d\u043e\u0433\u043e \u0430\u043d\u0430\u043b\u0438\u0437\u0430. \u0427\u0430\u0441\u0442\u044c 2.1: System Synchronous Input Delay Constraint<\/a>.<\/p>\n<\/li>\n

      2. \n

        \u0418\u0433\u0440\u0430 «Create FPGA content»<\/a><\/p>\n<\/li>\n

      3. \n

        \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u0430\u0437\u043e\u0432\u044b\u0445 \u043a\u043e\u043c\u043f\u043e\u043d\u0435\u043d\u0442\u043e\u0432 \u0426\u041e\u0421: \u041a\u0418\u0425 \u0444\u0438\u043b\u044c\u0442\u0440<\/a><\/p>\n<\/li>\n

      4. \n

        \u0422\u0435\u0445\u043d\u043e\u043b\u043e\u0433\u0438\u044f \u0432\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u044b\u0445 FPGA (eFPGA): \u043f\u0440\u043e\u0448\u043b\u043e\u0435 \u043d\u0430\u0441\u0442\u043e\u044f\u0449\u0435\u0435 \u0438 \u0431\u0443\u0434\u0443\u0449\u0435\u0435<\/a><\/p>\n<\/li>\n

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        FIFO \u0434\u043b\u044f \u0441\u0430\u043c\u044b\u0445 \u043c\u0430\u043b\u0435\u043d\u044c\u043a\u0438\u0445 (\u0432\u043c\u0435\u0441\u0442\u0435 \u0441 \u0432\u043e\u043f\u0440\u043e\u0441\u0430\u043c\u0438 \u043d\u0430 \u0438\u043d\u0442\u0435\u0440\u0432\u044c\u044e)<\/a><\/p>\n<\/li>\n

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      7. \n

        \u041d\u0430\u0432\u043e\u0434\u0438\u043c \u043a\u0440\u0430\u0441\u043e\u0442\u0443 \u0432 \u043a\u043e\u0434\u0435 \u0434\u043b\u044f \u041f\u041b\u0418\u0421 Lattice, \u043f\u043e\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u043e\u043c \u043d\u0430 \u0431\u0430\u0437\u0435 \u043f\u0430\u043a\u0435\u0442\u0430 LiteX<\/a><\/p>\n<\/li>\n<\/ol>\n

        \u041e\u0441\u0442\u0430\u043b\u044c\u043d\u043e\u0435 \u0430\u043d\u0433\u043b\u043e\u044f\u0437\u044b\u0447\u043d\u043e\u0435<\/h2>\n
          \n
        1. \n

          CFU Playground: Full-Stack Open-Source Framework for Tiny Machine Learning (tinyML) Acceleration on FPGAs<\/a><\/p>\n<\/li>\n

        2. \n

          Semtech Speeds Development of Digital Receiver FPGAs and ASICs — MATLAB & Simulink<\/a><\/p>\n<\/li>\n

        3. \n

          Scaling Suricata Performance to 100 Gbps with Napatech SmartNICs<\/a><\/p>\n<\/li>\n

        4. \n

          Enclustra FPGA Solutions | Mercury+ XU6 | Xilinx Zynq UltraScale+ MPSoC Module | System-on-Chip (SoC) Module | System-on-Module (SOM) | ZU2CG | ZU2EG | ZU3EG | ZU4CG | ZU4EV | ZU5EV<\/a><\/p>\n<\/li>\n

        5. \n

          Building a SoC with Litex. \u2013 controlpaths.<\/a><\/p>\n<\/li>\n

        6. \n

          Antmicro \u00b7 Open source keystroke injector implementation on the Fomu FPGA board<\/a><\/p>\n<\/li>\n

        7. \n

          MicroZed Chronicles: Versal Part Two \u2013 Device Architecture<\/a><\/p>\n<\/li>\n

        8. \n

          An FPGA Based Multi-Sensor Atmospheric Testing Device for Confined Spaces | IEEE Conference Publication | IEEE Xplore<\/a><\/p>\n<\/li>\n

        9. \n

          Utilizing Fine Line PCBs with High Density BGAs | Signal Integrity Journal<\/a><\/p>\n<\/li>\n

        10. \n

          3x n2disk Performance Increase for Intel PAC<\/a><\/p>\n<\/li>\n

        11. \n

          Imagination and Andes jointly validate GPU with RISC-V CPU IP<\/a><\/p>\n<\/li>\n

        12. \n

          PMIC Solutions<\/a><\/p>\n<\/li>\n

        13. \n

          tinyML Talks webcast: FFConv: An FPGA-based Accelerator for Fast Convolution Layers in Convolutional Neural Network<\/a><\/p>\n<\/li>\n

        14. \n

          Accelerate AI applications using VITIS AI on Xilinx ZynqMP UltraScale+ FPGA — Softnautics<\/a><\/p>\n<\/li>\n

        15. \n

          Lattice Propel System Design Environment<\/a><\/p>\n<\/li>\n

        16. \n

          HAFLANG — Hardware Acceleration of Functional Languages<\/a><\/p>\n<\/li>\n

        17. \n

          Electronics | Free Full-Text | Novel FPGA-Based Visual Stimulation Method for Eye Movement Analysis | HTML<\/a><\/p>\n<\/li>\n

        18. \n

          Working with Block Diagram\/Schematic Files — Verilog Development Tutorial p.3 — YouTube<\/a><\/p>\n<\/li>\n

        19. \n

          Migration from Xilinx Spartan-6 FPGA — Sandeepani<\/a><\/p>\n<\/li>\n

        20. \n

          FPGA opensource Ecosystem | LinkedIn<\/a><\/p>\n<\/li>\n

        21. \n

          Powerful Test & Measurement up to 100G Line Rate<\/a><\/p>\n<\/li>\n

        22. \n

          What is ASIC — FPGA — SoC? | Explanation, Differences & Applications — YouTube<\/a><\/p>\n<\/li>\n

        23. \n

          Open-Source Oscilloscope Demo Video — YouTube<\/a><\/p>\n<\/li>\n

        24. \n

          RDMA RoCE v2 IP by Grovf | How is it Unique? | by Astghik Nalchajyan | grovf | Jan, 2022 | Medium<\/a><\/p>\n<\/li>\n

        25. \n

          Robotics<\/a><\/p>\n<\/li>\n

        26. \n

          Enclustra FPGA Solutions | Mercury+ XU6 | Xilinx Zynq UltraScale+ MPSoC Module | System-on-Chip (SoC) Module | System-on-Module (SOM) | ZU2CG | ZU2EG | ZU3EG | ZU4CG | ZU4EV | ZU5EV<\/a><\/p>\n<\/li>\n

        27. \n

          FPGA technology and Supply Chain Cyber Security — cyrene<\/a><\/p>\n<\/li>\n

        28. \n

          TH53\/TH53L FPGA Crypto Mining Boards ETH Mining Demo — YouTube<\/a><\/p>\n<\/li>\n

        29. \n

          Campera-ES Utility Library on GitHub! | LinkedIn<\/a><\/p>\n<\/li>\n

        30. \n

          System on modules | TOPIC Embedded Systems<\/a><\/p>\n<\/li>\n

        31. \n

          WebTech Janvier ENG<\/a><\/p>\n<\/li>\n

        32. \n

          HandsOn Training — FPGA Security Bootcamp<\/a><\/p>\n<\/li>\n

        33. \n

          DSP basic — FIR filter + UVM — FPGA-Systems<\/a><\/p>\n<\/li>\n

        34. \n

          Event Lobby (EVENT: 3549953)<\/a><\/p>\n<\/li>\n

        35. \n

          FFT development on an FPGA — Simulation Design Flow using Vivado Software and Zynq Processor. — YouTube<\/a><\/p>\n<\/li>\n

        36. \n

          VHDL VERIFICATION \u2013 Mehmet Burak Aykenar<\/a><\/p>\n<\/li>\n

        37. \n

          Mercury ACAP eBook Final<\/a><\/p>\n<\/li>\n

        38. \n

          fpga-operator 2.7.4 \u00b7 inaccel\/inaccel<\/a><\/p>\n<\/li>\n

        39. \n

          Embedded Processor Market 2021-26: Share, Scope, Growth, Demand And Forecast | LinkedIn<\/a><\/p>\n<\/li>\n

        40. \n

          FAST Project<\/a><\/p>\n<\/li>\n

        41. \n

          Spartan-6 Replacement using Microchip<\/a><\/p>\n<\/li>\n

        42. \n

          028 — Standalone Simulation in Vivado (2) | RTL Audio Lab<\/a><\/p>\n<\/li>\n

        43. \n

          Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals — CNX Software<\/a><\/p>\n<\/li>\n

        44. \n

          Events — Company — Aldec<\/a><\/p>\n<\/li>\n

        45. \n

          Campera-ES Utility Library on GitHub! | LinkedIn<\/a><\/p>\n<\/li>\n

        46. \n

          Introduction to FPGA Part 10 — Metastability and Clock Domain Crossing | Digi-Key Electronics — YouTube<\/a><\/p>\n<\/li>\n

        47. \n

          xDNN: Inference for Deep Convolutional Neural Networks | ACM Transactions on Reconfigurable Technology and Systems<\/a><\/p>\n<\/li>\n

        48. \n

          Mouser Electronics Signs Global Distribution Deal with Liquid Instruments, Offers Moku FPGA-Based Testing Platforms<\/a><\/p>\n<\/li>\n

        49. \n

          Scaling Suricata Performance to 100 Gbps with Napatech SmartNICs<\/a><\/p>\n<\/li>\n

        50. \n

          DAC 2021 — Embedded FPGA IP from Menta — SemiWiki<\/a><\/p>\n<\/li>\n

        51. \n

          Home | SiliconCompiler<\/a><\/p>\n<\/li>\n

        52. \n

          Getting started \u2014 TerosHDL 2.0.1 documentation<\/a><\/p>\n<\/li>\n

        53. \n

          tinyML Talks webcast: FFConv: An FPGA-based Accelerator for Fast Convolution Layers in Convolutional Neural Network<\/a><\/p>\n<\/li>\n

        54. \n

          Synective Labs & Chalmers Launch FPGA Project Course — Recab<\/a><\/p>\n<\/li>\n

        55. \n

          Entropy | Free Full-Text | Design and Test of an Integrated Random Number Generator with All-Digital Entropy Source<\/a><\/p>\n<\/li>\n

        56. \n

          Speed up your R&D processes with Red Pitaya<\/a><\/p>\n<\/li>\n

        57. \n

          Microcontroller in FPGA? This is how to do it … | Step by Step Tutorial | Adam Taylor — YouTube<\/a><\/p>\n<\/li>\n

        58. \n

          Tang Nano 9K FPGA board can emulate PicoRV32 RISC-V soft-core with all peripherals — CNX Software<\/a><\/p>\n<\/li>\n

        59. \n

          Issue 14: Accelerated Verification of Block-Based FPGA Designs | Blue Pearl Software Inc.<\/a><\/p>\n<\/li>\n

        60. \n

          Industrial Robotics System Veo FreeMove* Using Intel FPGAs<\/a><\/p>\n<\/li>\n

        61. \n

          SAFE VPN10G-PCIe | sitehop<\/a><\/p>\n<\/li>\n

        62. \n

          Get Your Code Future-Ready with FREE Technical Webinars<\/a><\/p>\n<\/li>\n

        63. \n

          Intel\u00ae FPGA Technical Training<\/a><\/p>\n<\/li>\n

        64. \n

          Efinix, Inc. | Titanium Ti60 F225 Development Kit<\/a>UVM kit<\/a><\/p>\n<\/li>\n

        65. \n

          tinyML Talks: CFU Playground: Customize Your ML Processor for Your Specific TinyML Model — YouTube<\/a><\/p>\n<\/li>\n

        66. \n

          Prototype and Adjust a Deep Learning Network on FPGA Video — MATLAB & Simulink<\/a><\/p>\n<\/li>\n

        67. \n

          Xilinx Technologies for New Space \/ Space 2.0<\/a><\/p>\n<\/li>\n

        68. \n

          filtering with FPGA using object oriented design principles in VHDL — YouTube<\/a><\/p>\n<\/li>\n

        69. \n

          SystemVerilog Test Bench Transaction Class #verilog #uvm #semiconductor #vlsi #systemverilog — YouTube<\/a><\/p>\n<\/li>\n

        70. \n

          LiFi #2 — Behavioral Modules — Blog — Summer of FPGA — element14 Community<\/a><\/p>\n<\/li>\n

        71. \n

          FPGA Mining vs ASIC Mining: What Is More Profitable? | LetsExchange.io<\/a><\/p>\n<\/li>\n

        72. \n

          Rapixo CL Pro | Camera Link Frame Grabbers | Matrox Imaging<\/a><\/p>\n<\/li>\n

        73. \n

          A Tunable Parameter, High Linearity Time-to-Digital Converter Implemented in 28-nm FPGA | IEEE Journals & Magazine | IEEE Xplore<\/a><\/p>\n<\/li>\n

        74. \n

          Course Schedule | Microsemi<\/a><\/p>\n<\/li>\n

        75. \n

          Simulating and downloading a PIC circuit to Xilinx FPGA boards using TINACloud — YouTube<\/a><\/p>\n<\/li>\n

        76. \n

          AXI4-FULL AXI4-LITE and UART INTERFACE SIMULATION in MODELSIM with UVVM LIBRARY \u2013 Mehmet Burak Aykenar<\/a><\/p>\n<\/li>\n

        77. \n

          Efinix Demonstration of Using Titanium FPGAs with Quantum Acceleration to Optimize Edge AI Performance while Reducing Time to Market — Edge AI and Vision Alliance<\/a><\/p>\n<\/li>\n

        78. \n

          Lattice, Lenovo technology integration will usher in new era of smart PC\u2019s \u2013 PCR<\/a><\/p>\n<\/li>\n

        79. \n

          Programming Your First FPGA — Verilog Development Tutorial p.2 — YouTube<\/a><\/p>\n<\/li>\n

        80. \n

          FPGA — Developing new Hardware |\u00a0Concept Reply<\/a><\/p>\n<\/li>\n

        81. \n

          Google, Purdue & Harvard U\u2019s Open-Source Framework for TinyML Achieves up to 75x Speedups on FPGAs | Synced<\/a><\/p>\n<\/li>\n

        82. \n

          Xylon releases a new version of its MPSoC IP Framework for Multi-Camera Vision Applications<\/a><\/p>\n<\/li>\n

        83. \n

          FM-S14 | FTL<\/a><\/p>\n<\/li>\n

        84. \n

          20220111 FPGA standup — YouTube<\/a><\/p>\n<\/li>\n

        85. \n

          Using FPGA I\/O Optimization to Design PCBs More Cost Effectively | Siemens Digital Industries Software<\/a><\/p>\n<\/li>\n

        86. \n

          Promwad Advances Industrial Switch Design With Microchip SoC<\/a><\/p>\n<\/li>\n

        87. \n

          supratimdas\/NoobsCpu-8bit: A simple 8bit CPU.<\/a><\/p>\n<\/li>\n

        88. \n

          Image Recognition for Industrial Inspection using Deep Learning on FPGAs & SoCs | LinkedIn<\/a><\/p>\n<\/li>\n

        89. \n

          Introduction of XC series chip in FPGA Embedded | ABNewswire<\/a><\/p>\n<\/li>\n

        90. \n

          Verification of PCIe-based FPGA Designs Requiring DO-254 Compliance (US) — Marketing EDA<\/a><\/p>\n<\/li>\n

        91. \n

          Industry\u2019s First use of TLM for the At-Speed Verification of a PCIe-Based Avionics Design Requiring DO-254 Compliance — 2022-01-13 — Newsroom — Company — Aldec<\/a><\/p>\n<\/li>\n<\/ol>\n<\/div>\n<\/div>\n<\/div>\n

          <\/div>\n


          \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438           https:\/\/habr.com\/ru\/articles\/646903\/<\/a>
          <\/br><\/br><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-381488","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/381488","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=381488"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/381488\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=381488"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=381488"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=381488"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}