{"id":392971,"date":"2024-06-29T10:43:32","date_gmt":"2024-06-29T10:43:32","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=392971"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=392971","title":{"rendered":"High-level pipelining in TL-Verilog, RISC-V from Imagination, formal tools and open-source EDA on ChipEXPO in Moscow<\/span>"},"content":{"rendered":"
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This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https:\/\/eventswallet.com\/en\/events\/282\/<\/a><\/p>\n

The whole program is here<\/a> <\/p>\n

The English-speaking presentations and tutorials include:<\/p>\n

September 14<\/p>\n

11.15-11.50. The state of the open source chip design union. Edmund Humenberger, CEO and co-founder of Symbiotic EDA (Austria), an evangelist of the open design flows.<\/p>\n

12.00-13.20. Formal verification of the AXI bus interface logic connecting the system-on-chip (SoC) components. Presented by Dr. Dan Gisselquist from Zipcpu.com \/ Gisselquist Technology, USA.<\/p>\n

Dr. Dan Gisselquist is the owner and founder of Gisselquist Technology, LLC, a services based microbusiness focused digital electronic design and formal verification. He is best known today as the author of the ZipCPU blog, and for its focus on formal methods. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering from the US Air Force Institute of Technology.<\/p>\n

September 15<\/p>\n

11.15-11.50. A high-level TL-Verilog methodology allows designing a pipeline easier and with fewer bugs. Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.<\/p>\n

September 16.<\/p>\n

11:15-11:50. Introducing the «IUP» \u2013 The Imagination University Programme \u2013 including using an open-source fully-verified industrial processor core with RISC-V architecture to teach Computer Architecture and System-on-Chip (SoC) design.<\/p>\n

Robert Owen. Principal Consultant: Worldwide University Programme, Imagination Technologies, UK.<\/p>\n

The IUP provides best-in-class materials for under-graduate and post-grad education in Computer Science, Computer and Electronic Engineering on the topics of Mobil Graphics, Computer Architecture and SoC Design.<\/p>\n

In development currently is a new course about EdgeAI its principles and practices (release end’21).<\/p>\n

Robert Owen has been working in this field since 1994 and is known in Russia for the Texas Instruments’ DSP University Programme, and then subsequently for the MIPSfpga and Connected MCU Lab activities.<\/p>\n

12.00-15.00. Building RISC-V using TL-Verilog.<\/p>\n

During this workshop, the students will learn how to build a microprocessor core using TL-Verilog, a new high-level hardware description language. Unlike regular Verilog that forces a designer to define a pipeline explicitly, with all the details of pipeline control logic, TL-Verilog supports a methodology of pipelining automation that results in better designer productivity, code readability, and fewer bugs. The workshop includes online labs in the Makerchip.com environment, using example code for a microprocessor core that implements a subset of RISC-V architecture. In one lab, the students add forwarding and indirect branches to the core’s pipeline. In another lab, they use a WARP-V code generator to build a cluster with many RISC-V cores.<\/p>\n

Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.<\/p>\n

15.00-15.15. RVfpga-SoC — Introduction to System-on-Chip, «SoC» Design with a real CPU core and running the Zephyr RTOS. Presented by Zubair Kakakhel of AZKY Limited, UK, on behalf of Imagination Technologies.<\/p>\n

Zubair was a member of the MIPS team and is an experienced HW-SW Co-design Engineer, with a deep understanding of the interaction between hardware implementation and running operating systems. He defined and co-wrote RVfpga-SoC for the Imagination University Programme which was released to Educators in July 2021.<\/p>\n<\/div>\n<\/div>\n<\/div>\n

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<\/p>\n
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\u0422\u043e\u043b\u044c\u043a\u043e \u0437\u0430\u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0435 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u0438 \u043c\u043e\u0433\u0443\u0442 \u0443\u0447\u0430\u0441\u0442\u0432\u043e\u0432\u0430\u0442\u044c \u0432 \u043e\u043f\u0440\u043e\u0441\u0435. \u0412\u043e\u0439\u0434\u0438\u0442\u0435<\/a>, \u043f\u043e\u0436\u0430\u043b\u0443\u0439\u0441\u0442\u0430.<\/span><\/div>\n<\/div>\n<\/div>\n

<\/p>\n

What are your areas of interest?<\/div>\n
<\/p>\n
\n
50% <\/span>The algorithms of Electronic Design Automation (EDA)<\/span>2<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
50% <\/span>Register Transfer Level (RTL) Design<\/span>2<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
50% <\/span>RTL Design Verification (DV)<\/span>2<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
100% <\/span>CPU microarchitecture<\/span>4<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
25% <\/span>ASIC Physical Design<\/span>1<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
75% <\/span>FPGA Design<\/span>3<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
75% <\/span>Improving my technical English<\/span>3<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n

<\/div>\n

\u041f\u0440\u043e\u0433\u043e\u043b\u043e\u0441\u043e\u0432\u0430\u043b\u0438 4 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044f. \u0412\u043e\u0437\u0434\u0435\u0440\u0436\u0430\u043b\u0441\u044f 1 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c. <\/div>\n

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<\/div>\n

\u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438 https:\/\/habr.com\/ru\/articles\/577978\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"

<\/div>\n
\n
\n
\n
\n
<\/figcaption><\/figure>\n

This year ChipEXPO conference in Moscow invited several Western speakers to present in English the emerging technologies in high-level HDLs, formal verification, open-source EDA and using industrual RISC-V cores for education. You can join these presentations on September 14-16 for free using this link (you may need to use google translate from Russian to go through the registration) https:\/\/eventswallet.com\/en\/events\/282\/<\/a><\/p>\n

The whole program is here<\/a> <\/p>\n

The English-speaking presentations and tutorials include:<\/p>\n

September 14<\/p>\n

11.15-11.50. The state of the open source chip design union. Edmund Humenberger, CEO and co-founder of Symbiotic EDA (Austria), an evangelist of the open design flows.<\/p>\n

12.00-13.20. Formal verification of the AXI bus interface logic connecting the system-on-chip (SoC) components. Presented by Dr. Dan Gisselquist from Zipcpu.com \/ Gisselquist Technology, USA.<\/p>\n

Dr. Dan Gisselquist is the owner and founder of Gisselquist Technology, LLC, a services based microbusiness focused digital electronic design and formal verification. He is best known today as the author of the ZipCPU blog, and for its focus on formal methods. Dr. Gisselquist has an M.D. in Computer Engineering and a Ph.D. in Electrical Engineering from the US Air Force Institute of Technology.<\/p>\n

September 15<\/p>\n

11.15-11.50. A high-level TL-Verilog methodology allows designing a pipeline easier and with fewer bugs. Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.<\/p>\n

September 16.<\/p>\n

11:15-11:50. Introducing the «IUP» \u2013 The Imagination University Programme \u2013 including using an open-source fully-verified industrial processor core with RISC-V architecture to teach Computer Architecture and System-on-Chip (SoC) design.<\/p>\n

Robert Owen. Principal Consultant: Worldwide University Programme, Imagination Technologies, UK.<\/p>\n

The IUP provides best-in-class materials for under-graduate and post-grad education in Computer Science, Computer and Electronic Engineering on the topics of Mobil Graphics, Computer Architecture and SoC Design.<\/p>\n

In development currently is a new course about EdgeAI its principles and practices (release end’21).<\/p>\n

Robert Owen has been working in this field since 1994 and is known in Russia for the Texas Instruments’ DSP University Programme, and then subsequently for the MIPSfpga and Connected MCU Lab activities.<\/p>\n

12.00-15.00. Building RISC-V using TL-Verilog.<\/p>\n

During this workshop, the students will learn how to build a microprocessor core using TL-Verilog, a new high-level hardware description language. Unlike regular Verilog that forces a designer to define a pipeline explicitly, with all the details of pipeline control logic, TL-Verilog supports a methodology of pipelining automation that results in better designer productivity, code readability, and fewer bugs. The workshop includes online labs in the Makerchip.com environment, using example code for a microprocessor core that implements a subset of RISC-V architecture. In one lab, the students add forwarding and indirect branches to the core’s pipeline. In another lab, they use a WARP-V code generator to build a cluster with many RISC-V cores.<\/p>\n

Steve Hoover, the founder of a startup Redwood EDA (USA), a creator of Makerchip.com and TL-Verilog platforms.<\/p>\n

15.00-15.15. RVfpga-SoC — Introduction to System-on-Chip, «SoC» Design with a real CPU core and running the Zephyr RTOS. Presented by Zubair Kakakhel of AZKY Limited, UK, on behalf of Imagination Technologies.<\/p>\n

Zubair was a member of the MIPS team and is an experienced HW-SW Co-design Engineer, with a deep understanding of the interaction between hardware implementation and running operating systems. He defined and co-wrote RVfpga-SoC for the Imagination University Programme which was released to Educators in July 2021.<\/p>\n<\/div>\n<\/div>\n<\/div>\n

<\/div>\n

<\/p>\n

<\/p>\n
\n
<\/p>\n
<\/p>\n
\u0422\u043e\u043b\u044c\u043a\u043e \u0437\u0430\u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0435 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u0438 \u043c\u043e\u0433\u0443\u0442 \u0443\u0447\u0430\u0441\u0442\u0432\u043e\u0432\u0430\u0442\u044c \u0432 \u043e\u043f\u0440\u043e\u0441\u0435. \u0412\u043e\u0439\u0434\u0438\u0442\u0435<\/a>, \u043f\u043e\u0436\u0430\u043b\u0443\u0439\u0441\u0442\u0430.<\/span><\/div>\n<\/div>\n<\/div>\n

<\/p>\n

What are your areas of interest?<\/div>\n
<\/p>\n
\n
50% <\/span>The algorithms of Electronic Design Automation (EDA)<\/span>2<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
50% <\/span>Register Transfer Level (RTL) Design<\/span>2<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
50% <\/span>RTL Design Verification (DV)<\/span>2<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
100% <\/span>CPU microarchitecture<\/span>4<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
25% <\/span>ASIC Physical Design<\/span>1<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
75% <\/span>FPGA Design<\/span>3<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n
\n
75% <\/span>Improving my technical English<\/span>3<\/span><\/div>\n
\n
<\/div>\n<\/div>\n<\/div>\n

<\/div>\n

\u041f\u0440\u043e\u0433\u043e\u043b\u043e\u0441\u043e\u0432\u0430\u043b\u0438 4 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044f. \u0412\u043e\u0437\u0434\u0435\u0440\u0436\u0430\u043b\u0441\u044f 1 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c. <\/div>\n

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<\/div>\n

\u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438 https:\/\/habr.com\/ru\/articles\/577978\/<\/a>
<\/br><\/br><\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-392971","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/392971","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=392971"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/392971\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=392971"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=392971"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=392971"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}