{"id":445884,"date":"2025-01-23T09:00:23","date_gmt":"2025-01-23T09:00:23","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=445884"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=445884","title":{"rendered":"The State of Caravel: the First Look [\u041c\u0443\u0447\u0435\u043d\u0438\u044f \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0438 \u0447\u0438\u043f\u043e\u0432 \u0438\u0437-\u0437\u0430 \u0414\u043e\u043a\u0435\u0440\u0430 \u0438 \u041f\u0438\u0442\u043e\u043d\u0430]<\/span>"},"content":{"rendered":"
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A text on the current state of Open-source ASIC design tools. Includes side discussions of the upcoming hackathons in Mexico and Armenia, Docker and Python, Static Timing Analysis and RISC-V, Siberian shamans and treacherous swamps in Belarus.<\/p>\n

The State of Caravel: the First Look<\/h2>\n

Yuri Panchul, 2025.01.22<\/p>\n

This text is a mix of my thoughts on using Caravel and Open Lane together with a report on my first attempt to do the following:<\/p>\n

    \n
  1. \n

    Setup on 5 platforms: three Linux distributions, Windows and MacOS.<\/p>\n<\/li>\n

  2. \n

    Running RTL-to-GDSII flow for eFabless examples.<\/p>\n<\/li>\n

  3. \n

    Running RTL and gate-level simulation for eFabless examples.<\/p>\n<\/li>\n

  4. \n

    Working with chipIgnite demo \/ evaluation \/ development board.<\/p>\n<\/li>\n

  5. \n

    Planning for the next steps: seminars with ASIC open-source tools in Mexico and Armenia.<\/p>\n<\/li>\n<\/ol>\n

    Let\u2019s start by defining a specific area where Caravel can be useful.<\/p>\n

    1. Caravel as a tool to train balancing microarchitecture, area and timing<\/h3>\n

    Before joining an electronic company, a student who aims to become an RTL engineer \u2013 should be trained in developing pipelined designs. Not just a traditional 5-stage pipelined CPU, but pipelined data processing used in networking chips, GPUs and ML accelerators.<\/p>\n

    Such training requires doing a lot of exercises using a Verilog simulator to learn the tricks of maximizing bandwidth. However, learning microarchitecture without developing intuition about static timing analysis does not make sense: the students have to synthesize their designs to make sure the pipeline does not break the timing.<\/p>\n

    This is usually done in FPGA labs, however FPGA timing and utilization are different from ASICs, so here is another option: using eFabless Caravel infrastructure on the top of the Open Lane ASIC RTL-to-GDSII toolchain.<\/p>\n

    2. The Usage Scenario<\/h3>\n

    The presumed usage scenario is:<\/p>\n

      \n
    1. \n

      We get a group of students who do Verilog simulation exercises using systemverilog-homework exercises and FPGA labs using basics-graphics-music (BGM) repository.<\/p>\n<\/li>\n

    2. \n

      At some point, the students create their own designs using the BGM framework that isolates the students from FPGA vendor-specific details. Once a student\u2019s design works on an FPGA board, the student can transfer his board-independent modules into a modified Caravel infrastructure.<\/p>\n<\/li>\n

    3. \n

      The group can pack 15-30 designs into one Caravel or Caravel-Mini, depending on the required area and the costs. Glue logic, together with a housekeeping RISC-V core, can activate only one design at a time.<\/p>\n<\/li>\n

    4. \n

      Alternatively, instead of making individual designs, the student team can work on a larger project, such as a mid-range CPU core with caches and MMU. In this way, the students can learn how to cooperate in a setting similar to an industrial team.<\/p>\n<\/li>\n

    5. \n

      While working on a Caravel-based project, a student may re-engineer his pipelines to meet area and timing budgets. Eventually, the whole group will do a tapeout and get their chip manufactured in a few months.<\/p>\n<\/li>\n<\/ol>\n

      3. The Alternatives<\/h3>\n

      The alternative to Open Lane is to use Synopsys or Cadence licenses, but they are not available to everybody.<\/p>\n

      The alternative to the Caravel harness is to use TinyTapeout. While Tiny Tapeout is web-based and is easier from the installation point of view, it offers less area and fewer GPIO pins for each project. TinyTapeout also does not have an easy option to connect the design to a RISC-V housekeeping core available in Caravel. Cost-wise, TinyTapeout is more affordable for an individual student: $50 per tile of ~1000 ASIC standard cells, up to 16 tiles per project, plus a $200 development board. However, TinyTapeout infrastructure does not allow a group of students to build a larger project.<\/p>\n

      4. The Evaluation<\/h3>\n

      Let\u2019s evaluate how robust the combination of Caravel and Open Lane is to start such training.<\/p>\n

      4.1. Step 1. The capacity estimation<\/h4>\n

      Caravel-Mini is four times smaller than full Caravel and is less expensive, $3.5K versus $10K. Since Tiny Tapeout uses Caravel Infrastructure and has 512 tiles, we can roughly estimate that full Caravel accommodates ~512K standard cells and Caravel-Mini accommodates ~128K standard cells. This makes Caravel ~2.5 times more cost-efficient area-wise than TinyTapeout, and Caravel-Mini ~1.8 times more cost-efficient area-wise than TinyTapeout. Which is expected, this is similar to the difference in wholesale versus retail.<\/p>\n

      Based on a rough estimation of 1:10 D-flip-flop and logic gates ratio in a typical ASIC design and a knowledge of industrial MIPS CPU cores in the past, we can guess that Caravel can accommodate a mid-range industrial CPU core such as MIPS 24K used in WiFi routers and capable of running Linux. Caravel-Mini can probably accommodate only microcontroller cores such as various MIPS 4K or Cortex M derivatives and their RISC-V equivalents. TinyTapeout, with its limits up to 16 tiles or ~16K standard cells, can be used only for simplified educational CPU cores such as schoolRISCV.<\/p>\n

      4.2. Step 2. Generating the baseline projects from the templates<\/h4>\n

      This step is straightforward. I generated two GitHub repos from eFabless templates:<\/p>\n