{"id":452884,"date":"2025-03-23T15:14:06","date_gmt":"2025-03-23T15:14:06","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=452884"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=452884","title":{"rendered":"<span>Chisel, \u043f\u0435\u0440\u0432\u044b\u0439 \u0432\u0437\u0433\u043b\u044f\u0434 RTL-\u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0430<\/span>"},"content":{"rendered":"<div><!--[--><!--]--><\/div>\n<div id=\"post-content-body\">\n<div>\n<div class=\"article-formatted-body article-formatted-body article-formatted-body_version-2\">\n<div xmlns=\"http:\/\/www.w3.org\/1999\/xhtml\">\n<p>\u041d\u0435\u0434\u0430\u0432\u043d\u043e \u0432\u043e\u0437\u043d\u0438\u043a\u043b\u0430 \u043f\u043e\u0442\u0440\u0435\u0431\u043d\u043e\u0441\u0442\u044c \u0432 \u0431\u044b\u0441\u0442\u0440\u043e\u043c \u043f\u043e\u0433\u0440\u0443\u0436\u0435\u043d\u0438\u0438 \u0432 \u044f\u0437\u044b\u043a <a href=\"https:\/\/en.wikipedia.org\/wiki\/Chisel_(programming_language)\" rel=\"noopener noreferrer nofollow\">Chisel<\/a>. \u0427\u0442\u043e\u0431\u044b \u043f\u043e\u043f\u0440\u043e\u0431\u043e\u0432\u0430\u0442\u044c \u043d\u043e\u0432\u044b\u0439 \u044f\u0437\u044b\u043a, \u043d\u0435 \u0445\u043e\u0442\u0435\u043b\u043e\u0441\u044c \u043f\u0438\u0441\u0430\u0442\u044c \u0441\u0447\u0435\u0442\u0447\u0438\u043a \u0438\u043b\u0438 \u0441\u0443\u043c\u043c\u0430\u0442\u043e\u0440, \u0430 \u0447\u0442\u043e-\u0442\u043e \u043f\u0440\u0438\u0431\u043b\u0438\u0436\u0435\u043d\u043d\u043e\u0435 \u043a \u0440\u0430\u0431\u043e\u0447\u0438\u043c \u043c\u043e\u043c\u0435\u043d\u0442\u0430\u043c. \u0418 \u0442\u0430\u043a, \u0441\u0444\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u043c \u0437\u0430\u0434\u0430\u043d\u0438\u0435 \u043d\u0430 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u043c\u044b\u0439 \u0431\u043b\u043e\u043a:<\/p>\n<ul>\n<li>\n<p>\u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445 &#8212; AXI-Stream;<\/p>\n<\/li>\n<li>\n<p>\u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445 &#8212; AXI-Stream;<\/p>\n<\/li>\n<li>\n<p>\u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u044b\u0439 \u0440\u0430\u0437\u043c\u0435\u0440 \u043e\u0431\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 &#8212; 1024 \u0431\u0430\u0439\u0442\u0430;<\/p>\n<\/li>\n<li>\n<p>\u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0435\u0435 \u0441\u043b\u043e\u0432\u043e \u043f\u0430\u043a\u0435\u0442\u0430 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b \u043e\u0442 \u043f\u0430\u043a\u0435\u0442\u0430, \u043f\u043e\u0441\u0447\u0438\u0442\u0430\u043d\u043d\u043e\u0435 \u043f\u043e \u0430\u043b\u0433\u043e\u0440\u0438\u0442\u043c\u0443 crc8;<\/p>\n<\/li>\n<li>\n<p>\u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u0432\u044b\u043f\u043e\u043b\u043d\u0438\u0442\u044c \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0443 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0415\u0441\u043b\u0438 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0430\u044f \u0441\u0443\u043c\u043c\u0430 \u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u0430, \u043f\u0435\u0440\u0435\u0434\u0430\u0442\u044c \u043f\u0430\u043a\u0435\u0442 \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445, \u0438\u043d\u0430\u0447\u0435, \u0443\u0434\u0430\u043b\u0438\u0442\u044c \u043f\u0430\u043a\u0435\u0442.<\/p>\n<\/li>\n<\/ul>\n<h2>\u0421\u043e\u0434\u0435\u0440\u0436\u0430\u043d\u0438\u0435<\/h2>\n<p><a href=\"#1\" rel=\"noopener noreferrer nofollow\">1 \u041e\u0431\u0449\u0430\u044f \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f<\/a><\/p>\n<p><a href=\"#2\" rel=\"noopener noreferrer nofollow\">2 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 SystemVerilog<\/a><\/p>\n<p><a href=\"#3\" rel=\"noopener noreferrer nofollow\">3 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f<\/a><\/p>\n<p><a href=\"#4\" rel=\"noopener noreferrer nofollow\">4 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 Chisel<\/a><\/p>\n<p><a href=\"#5\" rel=\"noopener noreferrer nofollow\">5 \u0412\u044b\u0432\u043e\u0434\u044b<\/a><\/p>\n<p><a class=\"anchor\" name=\"1\" id=\"1\"><\/a><\/p>\n<h2>1 \u041e\u0431\u0449\u0430\u044f \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f<\/h2>\n<p>\u0410\u043b\u0433\u043e\u0440\u0438\u0442\u043c \u0440\u0430\u0431\u043e\u0442\u044b \u0431\u043b\u043e\u043a\u0430 \u0431\u0443\u0434\u0435\u0442 \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u043c:<\/p>\n<ol>\n<li>\n<p>\u041f\u0440\u0438\u0435\u043c \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445, \u043f\u043e\u0434\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b, \u0437\u0430\u043f\u0438\u0441\u044c \u043f\u0430\u043a\u0435\u0442\u0430 \u0432 FIFO. \u041f\u0440\u0438\u0435\u043c \u043f\u0430\u043a\u0435\u0442\u0430 \u0437\u0430\u043a\u0430\u043d\u0447\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u043f\u0440\u0438 \u043f\u043e\u0441\u0442\u0443\u043f\u043b\u0435\u043d\u0438\u0438 \u043f\u0440\u0438\u0437\u043d\u0430\u043a\u0430 \u043a\u043e\u043d\u0446\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 (tlast = 1, \u043a\u043e\u0433\u0434\u0430 \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d\u044b \u0441\u0438\u0433\u043d\u0430\u043b\u044b tvalid = 1 \u0438 tready = 1). \u041f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u0430\u043d\u0430\u043b\u0438\u0437\u0430 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b.<\/p>\n<\/li>\n<li>\n<p>\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0415\u0441\u043b\u0438 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0430\u044f \u0441\u0443\u043c\u043c\u0430 \u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u0430 (\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b \u0440\u0430\u0432\u043d\u043e 0), \u0442\u043e \u043f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 FIFO \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445. \u0418\u043d\u0430\u0447\u0435, \u043f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u0443\u0434\u0430\u043b\u0435\u043d\u0438\u044f \u043f\u0430\u043a\u0435\u0442\u0430.<\/p>\n<\/li>\n<li>\n<p>\u0423\u0434\u0430\u043b\u0435\u043d\u0438\u0435 \u043f\u0430\u043a\u0435\u0442\u0430. \u0412\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442\u0441\u044f \u0441\u0431\u0440\u043e\u0441 FIFO, \u043f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445.<\/p>\n<\/li>\n<li>\n<p>\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 FIFO \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445. \u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0437\u0430\u043a\u0430\u043d\u0447\u0438\u0432\u0430\u0435\u0442\u0441\u044f, \u043a\u043e\u0433\u0434\u0430 \u0431\u0443\u0434\u0435\u0442 \u0432\u044b\u0434\u0430\u043d \u043a\u043e\u043d\u0435\u0446 \u043f\u0430\u043a\u0435\u0442\u0430 (tlast = 1, \u043a\u043e\u0433\u0434\u0430 \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d\u044b \u0441\u0438\u0433\u043d\u0430\u043b\u044b tvalid = 1 \u0438 tready = 1). \u041f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445<\/p>\n<\/li>\n<\/ol>\n<p>\u0410\u043b\u0433\u043e\u0440\u0438\u0442\u043c \u043d\u0435 \u043e\u0441\u043e\u0431\u043e \u0441\u043b\u043e\u0436\u043d\u044b\u0439, \u0447\u0442\u043e\u0431\u044b \u043f\u0440\u043e\u0441\u0442\u043e \u043f\u043e\u0449\u0443\u043f\u0430\u0442\u044c \u043d\u043e\u0432\u044b\u0439 \u044f\u0437\u044b\u043a.<\/p>\n<p><a class=\"anchor\" name=\"2\" id=\"2\"><\/a><\/p>\n<h2>2 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 SystemVerilog<\/h2>\n<p>\u0421\u043d\u0430\u0447\u0430\u043b\u0430 \u0431\u0443\u0434\u0435\u0442 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0430 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043d\u0430 SystemVerilog, \u0447\u0442\u043e\u0431\u044b \u043d\u0430 \u044d\u0442\u043e\u0439 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043e\u043f\u0440\u043e\u0431\u043e\u0432\u0430\u0442\u044c \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0435 \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u0435, \u0430 \u043f\u043e\u0442\u043e\u043c \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u044d\u0442\u043e\u0433\u043e \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f \u0432\u0435\u0440\u0438\u0444\u0438\u0446\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044e \u043d\u0430 Chisel.<\/p>\n<p>\u0414\u043b\u044f \u043d\u0430\u0447\u0430\u043b\u0430 \u043f\u043e\u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f \u0431\u043b\u043e\u043a \u0434\u043b\u044f \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u043f\u0430\u043a\u0435\u0442\u0430. \u0411\u0443\u0434\u0435\u043c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c FIFO, \u043a\u043e\u0434 \u043f\u0440\u043e\u0441\u0442\u043e\u0433\u043e FIFO \u043f\u0440\u0438\u0432\u0435\u0434\u0435\u043d \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/src\/sync_fifo.sv\" rel=\"noopener noreferrer nofollow\">sync_fifo.sv<\/a>)<\/p>\n<details class=\"spoiler\">\n<summary>sync_fifo<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">`default_nettype none  module sync_fifo #(     parameter int FIFO_DEPTH            = 8,     parameter int DATA_WIDTH            = 32 )(     input  wire logic                   CLK_I,     input  wire logic                   RST_I,      input  wire logic                   WR_EN_I,     input  wire logic [DATA_WIDTH-1:0]  WR_DATA_I,     output var  logic                   FULL_O,      input  wire logic                   RD_EN_I,     output var  logic [DATA_WIDTH-1:0]  RD_DATA_O,     output var  logic                   EMPTY_O );  localparam int ADDR_WIDTH = $clog2(FIFO_DEPTH);  logic [ADDR_WIDTH:0]    wr_ptr; logic [ADDR_WIDTH:0]    rd_ptr; logic [DATA_WIDTH-1:0]  fifo_cell [FIFO_DEPTH-1:0];  always_comb begin : pc_full_o     FULL_O = (  (wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &amp;&amp;                 (wr_ptr[ADDR_WIDTH - 1:0] == rd_ptr[ADDR_WIDTH - 1:0]) ) ? 1'b1 : 1'b0; end : pc_full_o  always_comb begin : pc_empty_o     EMPTY_O = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0; end : pc_empty_o  always_ff @(posedge CLK_I) begin : ps_wr_ptr     if (RST_I) begin         wr_ptr &lt;= '0;     end     else begin         if (FULL_O == 1'b0 &amp;&amp; WR_EN_I == 1'b1) begin             wr_ptr &lt;= wr_ptr + 1'b1;         end     end end : ps_wr_ptr  always_ff @(posedge CLK_I) begin : ps_rd_ptr     if (RST_I) begin         rd_ptr &lt;= '0;     end     else begin         if (EMPTY_O == 1'b0 &amp;&amp; RD_EN_I == 1'b1) begin             rd_ptr &lt;= rd_ptr + 1'b1;         end     end end : ps_rd_ptr  always_ff @(posedge CLK_I) begin : ps_fifo_cell     if (FULL_O == 1'b0 &amp;&amp; WR_EN_I == 1'b1) begin         fifo_cell[wr_ptr[ADDR_WIDTH-1:0]] &lt;= WR_DATA_I;     end end : ps_fifo_cell  always_comb begin : pc_rd_data_o     RD_DATA_O = fifo_cell[rd_ptr[ADDR_WIDTH-1:0]]; end : pc_rd_data_o  endmodule  `resetall<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u0414\u0432\u0430 \u0443\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044f, \u043d\u0430 \u0447\u0442\u0435\u043d\u0438\u0435 \u0438 \u043d\u0430 \u0437\u0430\u043f\u0438\u0441\u044c, \u043c\u0430\u0441\u0441\u0438\u0432 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432.<\/p>\n<p>\u0414\u0430\u043b\u0435\u0435, \u043f\u043e\u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f \u0431\u043b\u043e\u043a \u0434\u043b\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0412\u043e\u0437\u044c\u043c\u0435\u043c \u043f\u043e \u043f\u0435\u0440\u0432\u043e\u0439 \u0441\u0441\u044b\u043b\u043a\u0435 \u0432 \u0433\u0443\u0433\u043b\u0435. \u041a\u043e\u0434 \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/src\/calc_crc.v\" rel=\"noopener noreferrer nofollow\">calc_crc.v<\/a>)<\/p>\n<details class=\"spoiler\">\n<summary>calc_crc<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">\/\/ vim: ts=4 sw=4 expandtab  \/\/ THIS IS GENERATED VERILOG CODE. \/\/ https:\/\/bues.ch\/h\/crcgen \/\/  \/\/ This code is Public Domain. \/\/ Permission to use, copy, modify, and\/or distribute this software for any \/\/ purpose with or without fee is hereby granted. \/\/  \/\/ THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES \/\/ WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF \/\/ MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY \/\/ SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER \/\/ RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, \/\/ NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE \/\/ USE OR PERFORMANCE OF THIS SOFTWARE.  `ifndef CALC_CRC_V_ `define CALC_CRC_V_  \/\/ CRC polynomial coefficients: x^8 + x^2 + x + 1 \/\/                              0x7 (hex) \/\/ CRC width:                   8 bits \/\/ CRC shift direction:         left (big endian) \/\/ Input word width:            8 bits  module calc_crc (     input [7:0] CRC_I,     input [7:0] DATA_I,     output [7:0] CRC_O );     assign CRC_O[0] = CRC_I[0] ^ CRC_I[6] ^ CRC_I[7] ^ DATA_I[0] ^ DATA_I[6] ^ DATA_I[7];     assign CRC_O[1] = CRC_I[0] ^ CRC_I[1] ^ CRC_I[6] ^ DATA_I[0] ^ DATA_I[1] ^ DATA_I[6];     assign CRC_O[2] = CRC_I[0] ^ CRC_I[1] ^ CRC_I[2] ^ CRC_I[6] ^ DATA_I[0] ^ DATA_I[1] ^ DATA_I[2] ^ DATA_I[6];     assign CRC_O[3] = CRC_I[1] ^ CRC_I[2] ^ CRC_I[3] ^ CRC_I[7] ^ DATA_I[1] ^ DATA_I[2] ^ DATA_I[3] ^ DATA_I[7];     assign CRC_O[4] = CRC_I[2] ^ CRC_I[3] ^ CRC_I[4] ^ DATA_I[2] ^ DATA_I[3] ^ DATA_I[4];     assign CRC_O[5] = CRC_I[3] ^ CRC_I[4] ^ CRC_I[5] ^ DATA_I[3] ^ DATA_I[4] ^ DATA_I[5];     assign CRC_O[6] = CRC_I[4] ^ CRC_I[5] ^ CRC_I[6] ^ DATA_I[4] ^ DATA_I[5] ^ DATA_I[6];     assign CRC_O[7] = CRC_I[5] ^ CRC_I[6] ^ CRC_I[7] ^ DATA_I[5] ^ DATA_I[6] ^ DATA_I[7]; endmodule  `endif \/\/ CALC_CRC_V_<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u041e\u043f\u0438\u0448\u0435\u043c \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0449\u0438\u0439 \u0430\u0432\u0442\u043e\u043c\u0430\u0442. \u041e\u0431\u044a\u044f\u0432\u043b\u0435\u043d\u0438\u0435 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u044b\u0445 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0439:<\/p>\n<pre><code class=\"vhdl\">enum logic [1:0] {ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND} checker_st;<\/code><\/pre>\n<p>\u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0449\u0435\u0433\u043e \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0430:<\/p>\n<pre><code class=\"vhdl\">always_ff @(posedge CLK_I) begin : ps_checker_st     if (RST_I) begin         checker_st &lt;= ST_RECEIVE;     end     else begin         case (checker_st)             ST_RECEIVE : begin                 if (packet_received) begin                     checker_st &lt;= ST_CHECK;                 end             end             ST_CHECK : begin                 if (crc_in == '0) begin                     checker_st &lt;= ST_SEND;                 end                 else begin                     checker_st &lt;= ST_RESET;                 end             end             ST_RESET : begin                 checker_st &lt;= ST_RECEIVE;             end             ST_SEND : begin                 if (packet_sended) begin                     checker_st &lt;= ST_RECEIVE;                 end             end         endcase     end end : ps_checker_st<\/code><\/pre>\n<p>\u041f\u0440\u0438\u0437\u043d\u0430\u043a\u0438 \u043e\u043a\u043e\u043d\u0447\u0430\u043d\u0438\u044f \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438 \u043e\u043a\u043e\u043d\u0447\u0430\u043d\u0438\u044f \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u043f\u0430\u043a\u0435\u0442\u0430:<\/p>\n<pre><code class=\"vhdl\">always_comb begin : pc_packet_received     packet_received = AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready &amp; AXIS_SLV_IF.tlast; end : pc_packet_received  always_comb begin : pc_packet_sended     packet_sended = AXIS_MST_IF.tvalid &amp; AXIS_MST_IF.tready &amp; AXIS_MST_IF.tlast; end : pc_packet_sended<\/code><\/pre>\n<p>\u041f\u043e\u0434\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b:<\/p>\n<pre><code class=\"vhdl\">always_ff @(posedge CLK_I) begin : ps_crc_in     if (RST_I) begin         crc_in &lt;= '1;     end     else begin         if (AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready) begin             crc_in &lt;= crc_out;         end         else if (checker_st == ST_CHECK) begin             crc_in &lt;= '1;         end     end end : ps_crc_in  calc_crc u_calc_crc(     .CRC_I  (crc_in),     .DATA_I (AXIS_SLV_IF.tdata),     .CRC_O  (crc_out) );<\/code><\/pre>\n<p>\u0421\u0431\u0440\u043e\u0441 FIFO \u0432 \u0441\u043b\u0443\u0447\u0430\u0435 \u043d\u0435\u0441\u043e\u0432\u043f\u0430\u0434\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b:<\/p>\n<pre><code class=\"vhdl\">always_ff @(posedge CLK_I) begin : ps_fifo_rst     if (RST_I) begin         fifo_rst &lt;= 1'b1;     end     else begin         fifo_rst &lt;= (checker_st == ST_RESET) ? 1'b1 : 1'b0;     end end : ps_fifo_rst<\/code><\/pre>\n<p>\u0414\u043b\u044f \u0443\u0434\u043e\u0431\u0441\u0442\u0432\u0430 \u0437\u0430\u043f\u0438\u0441\u0438\/\u0447\u0442\u0435\u043d\u0438\u0435 \u0432\/\u0438\u0437 FIFO \u043e\u0431\u044a\u044f\u0432\u0438\u043c \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u0443 \u0438 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u044b\u0435 \u0441\u0438\u0433\u043d\u0430\u043b\u044b:<\/p>\n<pre><code class=\"vhdl\"> localparam int AXIS_DW = $bits(AXIS_SLV_IF.tdata);  enum logic [1:0] {ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND} checker_st;  typedef struct packed {     logic               tlast;     logic [AXIS_DW-1:0] tdata; } fifo_data_t;  fifo_data_t fifo_data_w; logic       fifo_write; logic       fifo_empty; logic       fifo_read; fifo_data_t fifo_data_r;<\/code><\/pre>\n<p>\u0417\u0430\u043f\u0438\u0441\u044c \u0434\u0430\u043d\u043d\u044b\u0445 \u0432 FIFO:<\/p>\n<pre><code class=\"vhdl\">always_comb begin : pc_fifo_data_w     fifo_data_w.tdata = AXIS_SLV_IF.tdata;     fifo_data_w.tlast = AXIS_SLV_IF.tlast; end : pc_fifo_data_w  always_comb begin : pc_fifo_write     fifo_write = AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready; end : pc_fifo_write<\/code><\/pre>\n<p>\u0427\u0442\u0435\u043d\u0438\u0435 \u0438\u0437 FIFO \u0438 \u0432\u044b\u0434\u0430\u0447\u0430 \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445:<\/p>\n<pre><code class=\"vhdl\">always_comb begin : pc_fifo_read     fifo_read = (checker_st == ST_SEND &amp;&amp; AXIS_MST_IF.tready == 1'b1) ? 1'b1 : 1'b0; end : pc_fifo_read  always_comb begin : pc_axis_mst_if_tvalid     AXIS_MST_IF.tvalid = (checker_st == ST_SEND &amp;&amp; fifo_empty == 1'b0) ? 1'b1 : 1'b0; end : pc_axis_mst_if_tvalid  always_comb begin : pc_axis_mst_if_out     AXIS_MST_IF.tdata = (AXIS_MST_IF.tvalid) ? fifo_data_r.tdata : 'x;     AXIS_MST_IF.tlast = (AXIS_MST_IF.tvalid) ? fifo_data_r.tlast : 'x; end : pc_axis_mst_if_out<\/code><\/pre>\n<p>\u0418\u0442\u043e\u0433\u043e\u0432\u044b\u0439 \u0431\u043b\u043e\u043a, \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/src\/axis_crc_checker.sv\" rel=\"noopener noreferrer nofollow\">axis_crc_checker.sv)<\/a>:<\/p>\n<details class=\"spoiler\">\n<summary>axis_crc_checker<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">`default_nettype none  module axis_crc_checker (     input wire logic    CLK_I,     input wire logic    RST_I,      AXIS_Bus.slave      AXIS_SLV_IF,     AXIS_Bus.master     AXIS_MST_IF );  localparam int AXIS_DW = $bits(AXIS_SLV_IF.tdata);  enum logic [1:0] {ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND} checker_st;  typedef struct packed {     logic               tlast;     logic [AXIS_DW-1:0] tdata; } fifo_data_t;  logic       packet_received; logic       packet_sended; logic [7:0] crc_in; logic [7:0] crc_out; logic       fifo_rst; fifo_data_t fifo_data_w; logic       fifo_write; logic       fifo_empty; logic       fifo_read; fifo_data_t fifo_data_r;  always_comb begin : pc_packet_received     packet_received = AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready &amp; AXIS_SLV_IF.tlast; end : pc_packet_received  always_comb begin : pc_packet_sended     packet_sended = AXIS_MST_IF.tvalid &amp; AXIS_MST_IF.tready &amp; AXIS_MST_IF.tlast; end : pc_packet_sended  always_ff @(posedge CLK_I) begin : ps_checker_st     if (RST_I) begin         checker_st &lt;= ST_RECEIVE;     end     else begin         case (checker_st)             ST_RECEIVE : begin                 if (packet_received) begin                     checker_st &lt;= ST_CHECK;                 end             end             ST_CHECK : begin                 if (crc_in == '0) begin                     checker_st &lt;= ST_SEND;                 end                 else begin                     checker_st &lt;= ST_RESET;                 end             end             ST_RESET : begin                 checker_st &lt;= ST_RECEIVE;             end             ST_SEND : begin                 if (packet_sended) begin                     checker_st &lt;= ST_RECEIVE;                 end             end         endcase     end end : ps_checker_st  always_ff @(posedge CLK_I) begin : ps_axis_slv_if_tready     if (RST_I) begin         AXIS_SLV_IF.tready &lt;= 1'b0;     end     else begin         if (packet_received == 1'b1) begin             AXIS_SLV_IF.tready &lt;= 1'b0;         end         else if (checker_st == ST_RECEIVE) begin             AXIS_SLV_IF.tready &lt;= 1'b1;         end     end end : ps_axis_slv_if_tready  always_ff @(posedge CLK_I) begin : ps_crc_in     if (RST_I) begin         crc_in &lt;= '1;     end     else begin         if (AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready) begin             crc_in &lt;= crc_out;         end         else if (checker_st == ST_CHECK) begin             crc_in &lt;= '1;         end     end end : ps_crc_in  calc_crc u_calc_crc(     .CRC_I  (crc_in),     .DATA_I (AXIS_SLV_IF.tdata),     .CRC_O  (crc_out) );  always_ff @(posedge CLK_I) begin : ps_fifo_rst     if (RST_I) begin         fifo_rst &lt;= 1'b1;     end     else begin         fifo_rst &lt;= (checker_st == ST_RESET) ? 1'b1 : 1'b0;     end end : ps_fifo_rst  always_comb begin : pc_fifo_data_w     fifo_data_w.tdata = AXIS_SLV_IF.tdata;     fifo_data_w.tlast = AXIS_SLV_IF.tlast; end : pc_fifo_data_w  always_comb begin : pc_fifo_write     fifo_write = AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready; end : pc_fifo_write  sync_fifo #(     .FIFO_DEPTH (1024),     .DATA_WIDTH ($bits(fifo_data_t)) ) u_sync_fifo (     .CLK_I      (CLK_I),     .RST_I      (fifo_rst),     .WR_EN_I    (fifo_write),     .WR_DATA_I  (fifo_data_w),     .FULL_O     (),     .RD_EN_I    (fifo_read),     .RD_DATA_O  (fifo_data_r),     .EMPTY_O    (fifo_empty) );  always_comb begin : pc_fifo_read     fifo_read = (checker_st == ST_SEND &amp;&amp; AXIS_MST_IF.tready == 1'b1) ? 1'b1 : 1'b0; end : pc_fifo_read  always_comb begin : pc_axis_mst_if_tvalid     AXIS_MST_IF.tvalid = (checker_st == ST_SEND &amp;&amp; fifo_empty == 1'b0) ? 1'b1 : 1'b0; end : pc_axis_mst_if_tvalid  always_comb begin : pc_axis_mst_if_out     AXIS_MST_IF.tdata = (AXIS_MST_IF.tvalid) ? fifo_data_r.tdata : 'x;     AXIS_MST_IF.tlast = (AXIS_MST_IF.tvalid) ? fifo_data_r.tlast : 'x; end : pc_axis_mst_if_out  endmodule  `resetall<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p><a class=\"anchor\" name=\"3\" id=\"3\"><\/a><\/p>\n<h2>3 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f<\/h2>\n<p>\u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f \u0431\u0443\u0434\u0435\u0442 \u0431\u0430\u0437\u0438\u0440\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u043d\u0430 \u0442\u043e\u043c \u0436\u0435 \u043f\u0440\u0438\u043d\u0446\u0438\u043f\u0435, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u0431\u044b\u043b \u043e\u043f\u0438\u0441\u0430\u043d \u043c\u043d\u043e\u0439 \u0432 \u0441\u0442\u0430\u0442\u044c\u0435 <a href=\"https:\/\/habr.com\/ru\/articles\/835030\/\" rel=\"noopener noreferrer nofollow\">\u0422\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u0446\u0435\u043b\u043e\u0447\u0438\u0441\u043b\u0435\u043d\u043d\u043e\u0433\u043e \u0441\u0443\u043c\u043c\u0430\u0442\u043e\u0440\u0430 \u0441 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430\u043c\u0438 AXI-Stream \u043d\u0430 SystemVerilog<\/a><\/p>\n<p>\u0422\u0440\u0430\u043d\u0437\u0430\u043a\u0446\u0438\u044f \u0434\u043b\u044f \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 \u0432 \u0431\u043b\u043e\u043a \u0444\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c: \u0444\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u0431\u0443\u0444\u0435\u0440 \u0441\u043b\u0443\u0447\u0430\u0439\u043d\u043e\u0433\u043e \u0440\u0430\u0437\u043c\u0435\u0440\u0430, \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u043c\u043e\u0435 \u0431\u0443\u0444\u0435\u0440\u0430 \u0437\u0430\u043f\u043e\u043b\u043d\u044f\u0435\u0442\u0441\u044f \u0441\u043b\u0443\u0447\u0430\u0439\u043d\u044b\u043c\u0438 \u0434\u0430\u043d\u043d\u044b\u043c\u0438, \u0432 \u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0435\u0435 \u0441\u043b\u043e\u0432\u043e \u0431\u0443\u0444\u0435\u0440\u0430 \u043f\u043e\u043c\u0435\u0449\u0430\u0435\u0442\u0441\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u043d\u043e\u0435 \u043e\u0442 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u043c\u043e\u0433\u043e \u0431\u0443\u0444\u0435\u0440\u0430 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0418\u043d\u043e\u0433\u0434\u0430 \u0444\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043f\u0430\u043a\u0435\u0442, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u0431\u0443\u0434\u0435\u0442 \u0441\u043e\u0434\u0435\u0440\u0436\u0430\u0442\u044c \u043d\u0435\u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u0443\u044e \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0443\u044e \u0441\u0443\u043c\u043c\u0443, \u0434\u043b\u044f \u044d\u0442\u043e\u0433\u043e \u0432 \u0441\u043b\u0443\u0447\u0430\u0439\u043d\u043e\u0435 \u043c\u0435\u0441\u0442\u043e \u0432 \u043f\u0430\u043a\u0435\u0442\u0435 \u0437\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441\u043b\u0443\u0447\u0430\u0439\u043d\u043e\u0435 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435. \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/tb\/transaction_cls_pkg.sv\" rel=\"noopener noreferrer nofollow\">transaction_cls_pkg.sv<\/a>):<\/p>\n<details class=\"spoiler\">\n<summary>transaction_cls_pkg<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">`ifndef TRANSACTION_CLS_PKG__SV `define TRANSACTION_CLS_PKG__SV  package transaction_cls_pkg;      import test_param_pkg::*;      class transaction_cls;          localparam int MIN_PACK_SIZE = 10;         localparam int MAX_PACK_SIZE = 1024;          rand bit [$clog2(MAX_PACK_SIZE)-1:0] pack_size;         rand bit bad_pack;          constraint c_transaction {             pack_size inside {[MIN_PACK_SIZE : MAX_PACK_SIZE]};         }          logic [DATA_WIDTH-1:0] data_buf [];         logic [DATA_WIDTH-1:0] crc_field;          function void post_randomize ();             int select_index;             data_buf = new[pack_size];              crc_field = '1;             for (int i = 0; i &lt; data_buf.size() - 1; i++) begin                 data_buf[i] = $urandom_range(0, 2**DATA_WIDTH - 1);                 crc_field = calc_crc(.CRC_I(crc_field), .DATA_I(data_buf[i]));             end             data_buf[data_buf.size() - 1] = crc_field;              if (bad_pack === 1'b1) begin                 select_index = $urandom_range(0, data_buf.size());                 data_buf[select_index] = $urandom_range(0, 2**DATA_WIDTH - 1);             end          endfunction : post_randomize      endclass : transaction_cls  endpackage : transaction_cls_pkg  `endif \/\/TRANSACTION_CLS_PKG__SV<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0442\u0440\u0430\u043d\u0437\u0430\u043a\u0446\u0438\u0438 \u0432 \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u043c \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u0438 \u0432\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442\u0441\u044f \u0432 \u0431\u043b\u043e\u043a\u0435 scoreboard. \u041f\u0440\u0438\u043d\u0438\u043c\u0430\u0435\u0442\u0441\u044f \u0431\u0443\u0444\u0435\u0440 \u0441 \u0434\u0430\u043d\u043d\u044b\u043c\u0438, \u043f\u0440\u043e\u0432\u0435\u0440\u044f\u0435\u0442\u0441\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0430\u044f \u0441\u0443\u043c\u043c\u0430 \u043e\u0442 \u0431\u0443\u0444\u0435\u0440\u0430, \u0435\u0441\u043b\u0438 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0430\u044f \u0441\u0443\u043c\u043c\u0430 \u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u0430 (\u0440\u0430\u0432\u043d\u0430 0) \u0442\u043e \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u043c\u043e\u0435 \u0431\u0443\u0444\u0435\u0440\u0430 \u043a\u043e\u043f\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u0432 \u0432\u044b\u0445\u043e\u0434\u043d\u0443\u044e \u0442\u0440\u0430\u043d\u0437\u0430\u043a\u0446\u0438\u044e \u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u0438\u0437 scoreboard. \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c  \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/tb\/scoreboard_cls_pkg.sv\" rel=\"noopener noreferrer nofollow\">scoreboard_cls_pkg.sv)<\/a><\/p>\n<details class=\"spoiler\">\n<summary>scoreboard_cls_pkg<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">`ifndef SCOREBOARD_CLS_PKG__SV `define SCOREBOARD_CLS_PKG__SV  package scoreboard_cls_pkg;      import transaction_cls_pkg::*;     import test_param_pkg::*;      class scoreboard_cls;          mailbox #(transaction_cls)  mbx_agt2scb, mbx_scb2chk;         transaction_cls             input_transaction, output_transaction;         int                         cnt_good;         int                         cnt_bad;          function new (             input mailbox #(transaction_cls) mbx_agt2scb, mbx_scb2chk         );             this.mbx_agt2scb = mbx_agt2scb;             this.mbx_scb2chk = mbx_scb2chk;             cnt_good = 0;             cnt_bad = 0;         endfunction : new          task run (             input int count         );             logic [DATA_WIDTH-1:0] crc;              repeat (count) begin                 mbx_agt2scb.get(input_transaction);                 crc = '1;                  foreach (input_transaction.data_buf[i]) begin                     crc = calc_crc(.CRC_I(crc), .DATA_I(input_transaction.data_buf[i]));                 end                  if (crc === '0) begin                     output_transaction = new;                     output_transaction.data_buf = input_transaction.data_buf;                     mbx_scb2chk.put(output_transaction);                     cnt_good++;                 end                 else begin                     cnt_bad++;                 end             end         endtask : run      endclass : scoreboard_cls  endpackage : scoreboard_cls_pkg  `endif \/\/SCOREBOARD_CLS_PKG__SV<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u0417\u0430\u043f\u0443\u0441\u043a\u0430\u0435\u043c \u0442\u0435\u0441\u0442 \u0432 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0435, \u043f\u043e\u043b\u0443\u0447\u0430\u0435\u043c \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442:<\/p>\n<pre><code class=\"bash\"># ------------------------------------------------------------ #                    TEST PARAMS #                    TEST SYSTEM VERILOG SOURCES # Simulation run with default random seed # ------------------------------------------------------------ # [ENV] Run count = 1447 # [ENV] Socreboard good packet =  691, scoreboard bad packet =  756 # &gt;&gt;&gt;&gt;&gt; SUCCESS<\/code><\/pre>\n<p><a class=\"anchor\" name=\"4\" id=\"4\"><\/a><\/p>\n<h2>4 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 Chisel<\/h2>\n<p>\u0411\u044b\u0441\u0442\u0440\u044b\u0439 \u043f\u043e\u0438\u0441\u043a \u043f\u0440\u0438\u0432\u0435\u043b \u043d\u0430 \u0441\u0430\u0439\u0442 <a href=\"http:\/\/www.chisel-lang.org\/\" rel=\"noopener noreferrer nofollow\">chisel-lang.org<\/a>, \u0433\u0434\u0435 \u0435\u0441\u0442\u044c \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u044b\u0435 \u0441\u0441\u044b\u043b\u043a\u0438 \u043d\u0430 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044e \u0438 \u043f\u0440\u0438\u043c\u0435\u0440\u044b.<\/p>\n<p>\u0421\u0430\u0439\u0442 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u0442\u0430\u043a\u0438 \u0445\u043e\u0440\u043e\u0448\u043e \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u0438\u0440\u043e\u0432\u0430\u043d \u0438 \u0431\u044b\u0441\u0442\u0440\u043e \u0431\u044b\u043b\u0430 \u043d\u0430\u0439\u0434\u0435\u043d\u0430 \u0440\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0443\u0435\u043c\u0430\u044f \u043a\u043d\u0438\u0433\u0430 \u0434\u043b\u044f \u043d\u0430\u0447\u0430\u043b\u0430 &#8212; <a href=\"http:\/\/www.imm.dtu.dk\/~masca\/chisel-book.html\" rel=\"noopener noreferrer nofollow\">Digital Design with Chisel<\/a>. \u041a\u043d\u0438\u0433\u0430 \u043d\u0430\u043f\u0438\u0441\u0430\u043d\u0430 \u0445\u043e\u0440\u043e\u0448\u043e, \u0441 \u043f\u0440\u0438\u043c\u0435\u0440\u0430\u043c\u0438. \u0422\u0430\u043a\u0436\u0435 \u0432 \u043a\u043d\u0438\u0433\u0435 \u0435\u0441\u0442\u044c \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 <a href=\"https:\/\/github.com\/freechipsproject\/chisel-cheatsheet\/\" rel=\"noopener noreferrer nofollow\">Cheatsheet<\/a> \u0441 \u043a\u0440\u0430\u0442\u043a\u0438\u043c \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u0435\u043c \u043e\u0441\u043d\u043e\u0432\u043d\u044b\u0445 \u043a\u043e\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0439 \u0438 \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 <a href=\"https:\/\/github.com\/schoeberl\/chisel-empty\" rel=\"noopener noreferrer nofollow\">\u0440\u0435\u043f\u043e\u0437\u0438\u0442\u043e\u0440\u0438\u0439<\/a>, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0432 \u043a\u0430\u0447\u0435\u0441\u0442\u0432\u0435 \u043f\u0440\u0438\u043c\u0435\u0440\u0430.<\/p>\n<p>\u0418 \u0442\u0430\u043a, \u0434\u043b\u044f \u043d\u0430\u0447\u0430\u043b\u0430 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u0442\u044c FIFO \u0434\u043b\u044f \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u043f\u0430\u043a\u0435\u0442\u043e\u0432. \u0422\u0430\u043a \u043a\u0430\u043a, Chisel \u044d\u0442\u043e \u044f\u0437\u044b\u043a \u0441 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u043e\u0439 \u041e\u041e\u041f, \u0442\u043e \u0432\u0441\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u043c\u044b\u0435 \u043c\u043e\u0434\u0443\u043b\u0438 \u0434\u043e\u043b\u0436\u043d\u044b \u0440\u0430\u0441\u0448\u0438\u0440\u044f\u0442\u044c \u043a\u043b\u0430\u0441\u0441 <em>Module<\/em>. \u0412\u0445\u043e\u0434\u043d\u044b\u0435 \u0438 \u0432\u044b\u0445\u043e\u0434\u043d\u044b\u0435 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u044b \u043e\u0431\u043e\u0440\u0430\u0447\u0438\u0432\u0430\u044e\u0442\u0441\u044f \u0432 \u0432\u044b\u0437\u043e\u0432 <em>IO<\/em>.<\/p>\n<p>\u0420\u0430\u0441\u0448\u0438\u0440\u0438\u043c \u043a\u043b\u0430\u0441\u0441 <em>Bundle<\/em> \u0434\u043b\u044f \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u044f 2 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u0432: \u0434\u043b\u044f \u0437\u0430\u043f\u0438\u0441\u0438 \u0438 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f:<\/p>\n<pre><code class=\"scala\">class WriterIO (DataWidth: Int) extends Bundle {   val WriteEn   = Input(Bool())   val WriteData = Input(UInt(DataWidth.W))   val Full      = Output(Bool()) }  class ReaderIO (DataWidth: Int) extends Bundle {   val ReadEn   = Input(Bool())   val ReadData = Output(UInt(DataWidth.W))   val Empty   = Output(Bool()) }<\/code><\/pre>\n<p>\u0413\u0434\u0435 <em>Input\/Output<\/em> \u0437\u0430\u0434\u0430\u044e\u0442 \u043d\u0430\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u0435 \u0441\u0438\u0433\u043d\u0430\u043b\u043e\u0432 \u0434\u043b\u044f \u043c\u043e\u0434\u0443\u043b\u044f. <em>Bool<\/em> \u043e\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u0442 \u0441\u0438\u0433\u043d\u0430\u043b \u0448\u0438\u0440\u0438\u043d\u043e\u0439 1 \u0431\u0438\u0442, <em>UInt(DataWidth.W)) <\/em>\u043e\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u0442 \u0441\u0438\u0433\u043d\u0430\u043b \u0448\u0438\u0440\u0438\u043d\u043e\u0439 DataWidth \u0431\u0438\u0442, \u0437\u0430\u0434\u0430\u0432\u0430\u0435\u043c\u044b\u0439 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u043c \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430.<\/p>\n<p>\u0422\u043e\u0433\u0434\u0430, \u043e\u0431\u044a\u044f\u0432\u043b\u0435\u043d\u0438\u0435 \u043c\u043e\u0434\u0443\u043b\u044f \u0441 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430\u043c\u0438 \u0431\u0443\u0434\u0435\u0442 \u0432\u044b\u0433\u043b\u044f\u0434\u0435\u0442\u044c \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c:<\/p>\n<pre><code class=\"scala\">class SyncFifo (DataWidth: Int, FifoDepth: Int) extends Module {   val io = IO(new Bundle {     val Writer = new WriterIO(DataWidth)     val Reader = new ReaderIO(DataWidth)   } )<\/code><\/pre>\n<p>\u0423 \u043c\u043e\u0434\u0443\u043b\u044f \u0435\u0441\u0442\u044c 2 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u0430: DataWidth &#8212; \u0448\u0438\u0440\u0438\u043d\u0430 \u0437\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u043c\u044b\u0445 \u0434\u0430\u043d\u043d\u044b\u0445, FifoDepth &#8212; \u0433\u043b\u0443\u0431\u0438\u043d\u0430 FIFO. \u0421\u0438\u043d\u0445\u0440\u043e\u0441\u0438\u0433\u043d\u0430\u043b \u0438 \u0441\u0438\u0433\u043d\u0430\u043b \u0441\u0431\u0440\u043e\u0441\u0430 \u043e\u0431\u044a\u044f\u0432\u043b\u044f\u0442\u044c \u043d\u0435 \u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f, \u043e\u043d\u0438 \u0431\u0443\u0434\u0443\u0442 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u044b \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u0438.<\/p>\n<p>\u0414\u0430\u043b\u044c\u0448\u0435 \u043d\u0430\u0441 \u043f\u043e\u0434\u0436\u0438\u0434\u0430\u0435\u0442 \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u0435 \u043e\u0442\u043b\u0438\u0447\u0438\u0435 \u043e\u0442 \u044f\u0437\u044b\u043a\u0430 SystemVerilog: \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0435 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u0432.<\/p>\n<pre><code class=\"vhdl\">localparam int ADDR_WIDTH = $clog2(DEPTH);<\/code><\/pre>\n<pre><code class=\"scala\">val ADDR_WIDTH = unsignedBitLength(depth);<\/code><\/pre>\n<p>\u0415\u0441\u043b\u0438 \u0433\u043b\u0443\u0431\u0438\u043d\u0430 FIFO \u0440\u0430\u0432\u043d\u0430 8 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u0430\u043c, \u0442\u043e \u0432\u044b\u0437\u043e\u0432 <em>$clog2 <\/em>\u0432\u0435\u0440\u043d\u0435\u0442 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 3, \u0442\u043e \u0435\u0441\u0442\u044c \u043d\u0443\u0436\u043d\u043e 3 \u0431\u0438\u0442\u0430 \u0447\u0442\u043e\u0431\u044b \u0437\u0430\u043a\u043e\u0434\u0438\u0440\u043e\u0432\u0430\u0442\u044c 8 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0439. \u0412\u044b\u0437\u043e\u0432 <em>unsignedBitLength<\/em> \u043e\u0442 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f 8 \u0432\u0435\u0440\u043d\u0435\u0442 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 4. \u041d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u043f\u043e\u043c\u043d\u0438\u0442\u044c \u043e\u0431 \u044d\u0442\u043e\u043c.<\/p>\n<p>\u0421\u043e\u0437\u0434\u0430\u0435\u043c \u0443\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u0438 \u0434\u043b\u044f \u0437\u0430\u043f\u0438\u0441\u0438 \u0438 \u0447\u0442\u0435\u043d\u0438\u044f:<\/p>\n<pre><code class=\"scala\">val WritePtr = RegInit(0.U((ADDR_WIDTH).W)) val ReadPtr = RegInit(0.U((ADDR_WIDTH).W))<\/code><\/pre>\n<p>\u0417\u0434\u0435\u0441\u044c \u0432\u043e\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043b\u0438\u0441\u044c \u043e\u0431\u044a\u0435\u043a\u0442\u043e\u043c <em>RegInit<\/em>. \u041e\u043d \u0441\u043e\u0437\u0434\u0430\u0435\u0442 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0441 \u043d\u0430\u0447\u0430\u043b\u044c\u043d\u044b\u043c \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435\u043c 0 (\u043a\u043e\u0442\u043e\u0440\u043e\u0435 \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u043f\u043e \u0441\u0438\u0433\u043d\u0430\u043b\u0443 \u0441\u0431\u0440\u043e\u0441\u0430) \u0438 \u0448\u0438\u0440\u0438\u043d\u043e\u0439 ADDR_WIDTH \u0431\u0438\u0442.<\/p>\n<p>\u0421\u0444\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u043c \u043f\u0440\u0438\u0437\u043d\u0430\u043a\u0438 full \u0438 empty:<\/p>\n<pre><code class=\"scala\">io.Writer.Full  := (  (WritePtr(ADDR_WIDTH - 1) =\/= ReadPtr(ADDR_WIDTH - 1)) &amp;&amp;                        (WritePtr(ADDR_WIDTH - 2, 0) === ReadPtr(ADDR_WIDTH - 2, 0))) io.Reader.Empty := (WritePtr === ReadPtr)<\/code><\/pre>\n<p>\u0412 \u0446\u0435\u043b\u043e\u043c \u0432\u0441\u0435 \u043f\u043e\u0445\u043e\u0436\u0435, \u043f\u043e\u043c\u0435\u043d\u044f\u043b\u0441\u044f \u0441\u0438\u043d\u0442\u0430\u043a\u0441\u0438\u0441 \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0438 \u043d\u0430 \u0440\u0430\u0432\u0435\u043d\u0441\u0442\u0432\u043e\/\u043d\u0435\u0440\u0430\u0432\u0435\u043d\u0441\u0442\u0432\u043e \u0438 \u043f\u0440\u0438 \u043e\u0431\u0440\u0430\u0449\u0435\u043d\u0438\u0438 \u043a \u0432\u043d\u0435\u0448\u043d\u0438\u043c \u043f\u043e\u0440\u0442\u0430\u043c \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u0443\u043a\u0430\u0437\u044b\u0432\u0430\u0442\u044c \u0438\u0435\u0440\u0430\u0440\u0445\u0438\u0447\u0435\u0441\u043a\u0438\u0439 \u043f\u0443\u0442\u044c \u0447\u0435\u0440\u0435\u0437 \u0442\u043e\u0447\u043a\u0443.<\/p>\n<p>\u0421\u043e\u0437\u0434\u0430\u0435\u043c \u043c\u0430\u0441\u0441\u0438\u0432 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432, \u0432 \u043a\u043e\u0442\u043e\u0440\u044b\u0445 \u0431\u0443\u0434\u0435\u043c \u0445\u0440\u0430\u043d\u0438\u0442\u044c \u0434\u0430\u043d\u043d\u044b\u0435:<\/p>\n<pre><code class=\"scala\">val FifoCell = Reg(Vec((FifoDepth), UInt(DataWidth.W)))<\/code><\/pre>\n<p>\u0417\u0434\u0435\u0441\u044c \u0432\u043e\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043b\u0438\u0441\u044c \u043e\u0431\u044a\u0435\u043a\u0442\u043e\u043c <em>Reg<\/em> &#8212; \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0431\u0435\u0437 \u043d\u0430\u0447\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f. \u0422\u0430\u043a\u0438\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u0438\u0442\u044c FifoDepth \u0448\u0442\u0443\u043a, \u0434\u043b\u044f \u044d\u0442\u043e\u0433\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442\u0441\u044f \u0432\u044b\u0437\u043e\u0432 <em>Vec<\/em>. \u0420\u0430\u0437\u043c\u0435\u0440 \u043a\u0430\u0436\u0434\u043e\u0433\u043e \u0438\u0437 FifoDepth \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0434\u043e\u043b\u0436\u0435\u043d \u0431\u044b\u0442\u044c DataWidth \u0431\u0438\u0442.<\/p>\n<p>\u041f\u043e\u043b\u043d\u0430\u044f \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043b\u0435\u043d\u0430 \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/chisel-empty\/blob\/master\/src\/main\/scala\/fifo_pkg\/FifoPkg.scala\" rel=\"noopener noreferrer nofollow\">FifoPkg.scala<\/a>):<\/p>\n<details class=\"spoiler\">\n<summary>FifoPkg<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"scala\">package fifo_pkg  import chisel3._ import chisel3.util._  class WriterIO (DataWidth: Int) extends Bundle {   val WriteEn   = Input(Bool())   val WriteData = Input(UInt(DataWidth.W))   val Full      = Output(Bool()) }  class ReaderIO (DataWidth: Int) extends Bundle {   val ReadEn   = Input(Bool())   val ReadData = Output(UInt(DataWidth.W))   val Empty   = Output(Bool()) }  class SyncFifo (DataWidth: Int, FifoDepth: Int) extends Module {   val io = IO(new Bundle {     val Writer = new WriterIO(DataWidth)     val Reader = new ReaderIO(DataWidth)   } )    val ADDR_WIDTH = unsignedBitLength(FifoDepth);    val WritePtr = RegInit(0.U((ADDR_WIDTH).W))   val ReadPtr = RegInit(0.U((ADDR_WIDTH).W))   val FifoCell = Reg(Vec((FifoDepth), UInt(DataWidth.W)))    io.Writer.Full  := (  (WritePtr(ADDR_WIDTH - 1) =\/= ReadPtr(ADDR_WIDTH - 1)) &amp;&amp;                          (WritePtr(ADDR_WIDTH - 2, 0) === ReadPtr(ADDR_WIDTH - 2, 0)))   io.Reader.Empty := (WritePtr === ReadPtr)      when (io.Writer.Full === 0.U &amp;&amp; io.Writer.WriteEn === 1.U) {     WritePtr := WritePtr + 1.U   }    when (io.Reader.Empty === 0.U &amp;&amp; io.Reader.ReadEn === 1.U) {     ReadPtr := ReadPtr + 1.U   }      when (io.Writer.Full === 0.U &amp;&amp; io.Writer.WriteEn === 1.U) {     FifoCell(WritePtr(ADDR_WIDTH - 2, 0)) := io.Writer.WriteData;   }    io.Reader.ReadData := FifoCell(ReadPtr(ADDR_WIDTH - 2, 0)) }<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u0411\u043b\u043e\u043a \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c\u0441\u044f \u0442\u043e\u0442 \u0436\u0435, \u0447\u0442\u043e \u0438 \u0432 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043d\u0430 SystemVerilog, \u0442\u0430\u043a \u043a\u0430\u043a Chisel \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0430\u0442\u044c \u0432\u043d\u0435\u0448\u043d\u0438\u0435 \u0431\u043b\u043e\u043a\u0438 \u043a\u0430\u043a blackbox:<\/p>\n<pre><code class=\"scala\">class calc_crc extends HasBlackBoxResource {   val io = IO (new Bundle {     val CRC_I   = Input(UInt(8.W))     val DATA_I  = Input(UInt(8.W))     val CRC_O   = Output(UInt(8.W))   } )   addResource(\"calc_crc.v\") }<\/code><\/pre>\n<p>\u0414\u043b\u044f \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 AXI-Stream \u0432 Chisel \u0435\u0441\u0442\u044c \u043a\u043b\u0430\u0441\u0441 <em>DecoupledIO<\/em>, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0441\u0438\u0433\u043d\u0430\u043b\u044b valid \u0438 ready, \u0430 \u0442\u0430\u043a\u0436\u0435 \u043f\u043e\u043b\u0435 bits \u0434\u043b\u044f \u0434\u0430\u043d\u043d\u044b\u0445.<\/p>\n<p>\u0420\u0430\u0441\u0448\u0438\u0440\u0438\u043c \u043a\u043b\u0430\u0441\u0441 <em>Bundle<\/em>, \u0434\u043e\u0431\u0430\u0432\u0438\u0432 \u0432 \u043d\u0435\u0433\u043e \u0441\u0438\u0433\u043d\u0430\u043b Tdata (\u0448\u0438\u0440\u0438\u043d\u043e\u0439 8 \u0431\u0438\u0442) \u0438 \u0441\u0438\u0433\u043d\u0430\u043b Tast (\u0448\u0438\u0440\u0438\u043d\u043e\u0439 1 \u0431\u0438\u0442):<\/p>\n<pre><code class=\"scala\">class AxisBus extends Bundle {   val Tlast = Bool()       val Tdata = UInt(8.W) }<\/code><\/pre>\n<p>\u0422\u043e\u0433\u0434\u0430, \u043e\u0431\u044a\u044f\u0432\u043b\u0435\u043d\u0438\u0435 \u043c\u043e\u0434\u0443\u043b\u044f \u0431\u0443\u0434\u0435\u0442 \u0432\u044b\u0433\u043b\u044f\u0434\u0435\u0442\u044c \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c:<\/p>\n<pre><code class=\"scala\">class AxisCrcChecker extends Module {    val io = IO(new Bundle {                     val AxisSlv = Flipped(new DecoupledIO(new AxisBus))     val AxisMst = new DecoupledIO(new AxisBus)   } ) <\/code><\/pre>\n<p>\u041f\u043e \u0443\u043c\u043e\u043b\u0447\u0430\u043d\u0438\u044e, \u043f\u0440\u0438 \u0434\u043e\u0431\u0430\u0432\u043b\u0435\u043d\u0438\u0438 \u043a\u043b\u0430\u0441\u0441\u0430 <em>DecoupledIO<\/em>, \u043c\u043e\u0434\u0443\u043b\u044c \u0441\u0447\u0438\u0442\u044b\u0432\u0430\u0435\u0442 \u0435\u0433\u043e \u0432\u044b\u0445\u043e\u0434\u043d\u044b\u043c \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u043c, \u0442\u043e \u0435\u0441\u0442\u044c ready \u0432\u0445\u043e\u0434, valid \u0432\u044b\u0445\u043e\u0434. \u0427\u0442\u043e\u0431\u044b \u0441\u0434\u0435\u043b\u0430\u0442\u044c \u0435\u0433\u043e \u0432\u0445\u043e\u0434\u043d\u044b\u043c \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u043c (ready \u0432\u044b\u0445\u043e\u0434, valid \u0432\u0445\u043e\u0434) \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u0434\u043e\u0431\u0430\u0432\u0438\u0442\u044c \u0432\u044b\u0437\u043e\u0432 <em>Flipped<\/em>.<\/p>\n<p>\u041e\u0431\u044a\u044f\u0432\u043b\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0435\u0447\u043d\u043e\u0433\u043e \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0430 \u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f:<\/p>\n<pre><code class=\"scala\">  object State extends ChiselEnum {     val ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND = Value   }   import State._   val CheckerStReg = RegInit(ST_RECEIVE)      switch (CheckerStReg) {     is (ST_RECEIVE) {       when (PacketReceived === 1.U) {         CheckerStReg := ST_CHECK       }     }     is (ST_CHECK) {       when (CrcInReg === 0.U) {         CheckerStReg := ST_SEND       }       .otherwise {         CheckerStReg := ST_RESET       }     }     is (ST_RESET) {       CheckerStReg := ST_RECEIVE     }     is (ST_SEND) {       when (RacketSended === 1.U) {         CheckerStReg := ST_RECEIVE       }     }   }<\/code><\/pre>\n<p>\u0421\u043e\u0437\u0434\u0430\u0435\u0442\u0441\u044f \u043d\u043e\u0432\u044b\u0439 \u0442\u0438\u043f, \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e <em>RegInit<\/em> \u0441\u043e\u0437\u0434\u0430\u0435\u0442\u0441\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0441\u043e \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435\u043c \u043f\u043e\u0441\u043b\u0435 \u0441\u0431\u0440\u043e\u0441\u0430 ST_RECEIVE.<\/p>\n<p>\u041f\u0440\u0438\u0437\u043d\u0430\u043a\u0438 \u043e\u043a\u043e\u043d\u0447\u0430\u043d\u0438\u044f \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438 \u043e\u043a\u043e\u043d\u0447\u0430\u043d\u0438\u044f \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u043f\u0430\u043a\u0435\u0442\u0430:<\/p>\n<pre><code class=\"scala\">val PacketReceived  = Wire(Bool()) val RacketSended    = Wire(Bool())  PacketReceived := io.AxisSlv.valid &amp; io.AxisSlv.ready &amp; io.AxisSlv.bits.Tlast  RacketSended := io.AxisMst.valid &amp; io.AxisMst.ready &amp; io.AxisMst.bits.Tlastt<\/code><\/pre>\n<p>\u041f\u043e\u0434\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b:<\/p>\n<pre><code class=\"scala\">val CrcInReg        = RegInit(\"hFF\".U(8.W)) val CrcOut          = Wire(UInt(8.W))  when (io.AxisSlv.valid &amp; io.AxisSlv.ready) {   CrcInReg := CrcOut } .elsewhen (CheckerStReg === ST_CHECK) {   CrcInReg := \"hFF\".U }  val u_calc_crc = Module(new calc_crc())  u_calc_crc.io.CRC_I   := CrcInReg u_calc_crc.io.DATA_I  := io.AxisSlv.bits.Tdata CrcOut                := u_calc_crc.io.CRC_O<\/code><\/pre>\n<p>\u0417\u0434\u0435\u0441\u044c, \u0440\u0435\u0433\u0438\u0441\u0442\u0440 CrcInReg \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435\u043c 0xFF \u043f\u043e\u0441\u043b\u0435 \u0441\u0438\u0433\u043d\u0430\u043b\u0430 \u0441\u0431\u0440\u043e\u0441\u0430, CrcOut \u043f\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043b\u044f\u0435\u0442 \u0441\u043e\u0431\u043e\u0439 \u0448\u0438\u043d\u0443 \u0434\u043b\u044f \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442\u0430 \u0438\u0437 \u043c\u043e\u0434\u0443\u043b\u044f \u043f\u043e\u0434\u0441\u0447\u0435\u0442\u0430 crc. \u0412\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442\u0441\u044f \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043a\u0430 \u043c\u043e\u0434\u0443\u043b\u044f \u043f\u043e\u0434\u0441\u0447\u0435\u0442\u0430 crc \u0438 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u0441\u0438\u0433\u043d\u0430\u043b\u043e\u0432 \u043a \u0435\u0433\u043e \u043f\u043e\u0440\u0442\u0430\u043c.<\/p>\n<p>\u0421\u0431\u0440\u043e\u0441 FIFO \u0432 \u0441\u043b\u0443\u0447\u0430\u0435 \u043d\u0435\u0441\u043e\u0432\u043f\u0430\u0434\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b:<\/p>\n<pre><code class=\"scala\">val FifoRstReg      = RegInit(1.U(1.W))  FifoRstReg := (CheckerStReg === ST_RESET)  val u_sync_fifo = Module(new SyncFifo(9, 1024))    u_sync_fifo.reset := (FifoRstReg === 1.U)<\/code><\/pre>\n<p>\u0420\u0435\u0433\u0438\u0441\u0442\u0440 FifoRstReg \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u0432 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 1 \u043f\u0440\u0438 \u0441\u0438\u0433\u043d\u0430\u043b\u0435 \u0441\u0431\u0440\u043e\u0441\u0430 \u0438\u043b\u0438 \u043f\u0440\u0438 \u043d\u0430\u0445\u043e\u0436\u0434\u0435\u043d\u0438\u0438 \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0449\u0435\u0433\u043e \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0430 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0438 ST_RESET. \u0412\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442\u0441\u044f \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043a \u043d\u0435\u044f\u0432\u043d\u043e\u043c\u0443 \u0441\u0438\u0433\u043d\u0430\u043b\u0443 \u0441\u0431\u0440\u043e\u0441\u0430 \u0443 \u043c\u043e\u0434\u0443\u043b\u044f u_sync_fifo.<\/p>\n<p>\u0412 Chisel \u0435\u0441\u0442\u044c \u0434\u0432\u0435 \u043a\u043e\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438, \u043a\u043e\u0442\u043e\u0440\u044b\u0435 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0433\u0440\u0443\u043f\u043f\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0441\u0438\u0433\u043d\u0430\u043b\u044b: <em>Bundle<\/em> \u0438 <em>Vec<\/em>. <em>Bundle<\/em> \u0433\u0440\u0443\u043f\u043f\u0438\u0440\u0443\u0435\u0442 \u0441\u0438\u0433\u043d\u0430\u043b\u044b \u0440\u0430\u0437\u043d\u044b\u0445 \u0442\u0438\u043f\u043e\u0432 \u043a\u0430\u043a \u0438\u043c\u0435\u043d\u043e\u0432\u0430\u043d\u043d\u044b\u0435 \u043f\u043e\u043b\u044f. <em>Vec<\/em> \u043f\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043b\u044f\u0435\u0442 \u0441\u043e\u0431\u043e\u0439 \u0438\u043d\u0434\u0435\u043a\u0441\u0438\u0440\u0443\u0435\u043c\u044b\u0439 \u043d\u0430\u0431\u043e\u0440 \u0441\u0438\u0433\u043d\u0430\u043b\u043e\u0432 \u043e\u0434\u043d\u043e\u0433\u043e \u0442\u0438\u043f\u0430. <em>Vec<\/em> \u043d\u0435 \u043f\u043e\u0434\u0445\u043e\u0434\u0438\u0442, \u0442\u0430\u043a \u043a\u0430\u043a \u0441\u0438\u0433\u043d\u0430\u043b\u044b \u0440\u0430\u0437\u043d\u043e\u0433\u043e \u0442\u0438\u043f\u0430: 8 \u0431\u0438\u0442 \u0434\u0430\u043d\u043d\u044b\u0445 \u0438 1 \u0431\u0438\u0442 \u043f\u0440\u0438\u0437\u043d\u0430\u043a\u0430 last. \u0422\u0430\u043a\u0436\u0435, \u0437\u0430\u043f\u0440\u0435\u0449\u0430\u0435\u0442\u0441\u044f \u0437\u0430\u043f\u043e\u043b\u043d\u0435\u043d\u0438\u0435 \u043c\u0430\u0441\u0441\u0438\u0432\u0430 \u0431\u0438\u0442 \u0441 \u043f\u0440\u044f\u043c\u044b\u043c \u0443\u043a\u0430\u0437\u0430\u043d\u0438\u0435\u043c \u0438\u043d\u0434\u0435\u043a\u0441\u0430. \u041f\u0440\u0438\u043c\u0435\u0440 \u0438\u0437 \u043a\u043d\u0438\u0433\u0438, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u043f\u0440\u0438\u0432\u0435\u0434\u0435\u0442 \u043a \u043e\u0448\u0438\u0431\u043a\u0435:<\/p>\n<pre><code class=\"scala\">val assignWord = Wire(UInt(16.W)) assignWord(7, 0) := lowByte assignWord(15, 8) := highByte<\/code><\/pre>\n<p>\u0412 \u043a\u043d\u0438\u0433\u0435 \u043f\u0440\u0435\u0434\u043b\u0430\u0433\u0430\u0435\u0442\u0441\u044f \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0435\u0435 \u0440\u0435\u0448\u0435\u043d\u0438\u0435 \u043f\u0440\u043e\u0431\u043b\u0435\u043c\u044b: \u0441\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u0434\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0439 \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u044b \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 <em>Bundle<\/em>:<\/p>\n<pre><code class=\"scala\">val assignWord = Wire(UInt(16.W)) class Split extends Bundle {   val high = UInt(8.W)   val low = UInt(8.W) }  val split = Wire(new Split()) split.low := lowByte split.high := highByte assignWord := split.asUInt()<\/code><\/pre>\n<p>\u0412 \u043a\u043d\u0438\u0433\u0435 \u043e\u0448\u0438\u0431\u043a\u0430 \u0432 \u043a\u043e\u0434\u0435, \u0442\u0430\u043a \u043a\u0430\u043a \u0442\u0430\u043a\u043e\u0439 \u043f\u0440\u0438\u043c\u0435\u0440 \u043f\u0440\u0438\u0432\u043e\u0434\u0438\u0442 \u043a \u043e\u0448\u0438\u0431\u043a\u0435 \u043f\u0440\u0438 \u0442\u0440\u0430\u043d\u0441\u043b\u044f\u0446\u0438\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430. \u0423 .asUInt \u043d\u0435 \u0434\u043e\u043b\u0436\u043d\u043e \u0431\u044b\u0442\u044c \u0441\u043a\u043e\u0431\u043e\u043a \u0432 \u044d\u0442\u043e\u043c \u0441\u043b\u0443\u0447\u0430\u0435.<\/p>\n<p>\u0411\u044b\u043b \u043d\u0430\u043f\u0438\u0441\u0430\u043d \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u0439 \u043a\u043e\u0434:<\/p>\n<pre><code class=\"scala\">class FifoDataT extends Bundle {   val Last = UInt(1.W)   val Data = UInt(8.W) }  val FifoDataW = Wire(new FifoDataT()) val Rifo_data_r = Wire(new FifoDataT())  FifoDataW.data := io.AxisSlv.bits.Tdata FifoDataW.last := io.AxisSlv.bits.Tlast  u_sync_fifo.io.Writer.WriteData := FifoDataW.asUInt fifo_data_r := u_sync_fifo.io.reader.rd_data; <\/code><\/pre>\n<p>\u0418 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0430 \u043e\u0448\u0438\u0431\u043a\u0430 \u043f\u0440\u0438 \u043f\u043e\u043f\u044b\u0442\u043a\u0435 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0438\u0442\u044c \u043f\u043e\u0440\u0442 \u043f\u0440\u043e\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0445 \u0434\u0430\u043d\u043d\u044b\u0445 \u0438\u0437 FIFO \u043a \u044d\u043a\u0437\u0435\u043c\u043f\u043b\u044f\u0440\u0443 \u0441\u043e\u0437\u0434\u0430\u043d\u043d\u043e\u0433\u043e \u043a\u043b\u0430\u0441\u0441\u0430:<\/p>\n<pre><code class=\"scala\">error] chisel3.package$ChiselException: Connection between sink (AxisCrcChecker.fifo_data_r: Wire[FifoDataT]) and source (SyncFifo.io.reader.rd_data: IO[UInt&lt;9&gt;]) failed @: Sink (FifoDataT) and Source (UInt&lt;9&gt;) have different types. [error]         at ... () [error]         at eht_frame_filter_pkg.AxisCrcChecker.&lt;init&gt;(AxisCrcChecker.scala:116) [error]         at eht_frame_filter_pkg.AxisCrcCheckerMain$.$anonfun$new$46(AxisCrcChecker.scala:124) [error]         at ... () [error]         at ... (Stack trace trimmed to user code only. Rerun with --full-stacktrace to see the full stack trace) [error] stack trace is suppressed; run last Compile \/ run for the full output [error] (Compile \/ run) chisel3.package$ChiselException: Connection between sink (AxisCrcChecker.fifo_data_r: Wire[FifoDataT]) and source (SyncFifo.io.reader.rd_data: IO[UInt&lt;9&gt;]) failed @: Sink (FifoDataT) and Source (UInt&lt;9&gt;) have different types. <\/code><\/pre>\n<p>\u041f\u043e\u043d\u044f\u0442\u043d\u043e, \u0447\u0442\u043e \u0442\u0438\u043f\u044b \u043d\u0435 \u0441\u043e\u0432\u043f\u0430\u0434\u0430\u044e\u0442, \u043d\u043e \u0447\u0442\u043e \u0441 \u044d\u0442\u0438\u043c \u0434\u0435\u043b\u0430\u0442\u044c &#8212; \u043d\u0435 \u043f\u043e\u043d\u044f\u0442\u043d\u043e. \u0412 \u0438\u0442\u043e\u0433\u043e \u043f\u0435\u0440\u0435\u043f\u0438\u0448\u0435\u043c \u043f\u043e \u0441\u0442\u0430\u0440\u0438\u043d\u043a\u0435:<\/p>\n<pre><code class=\"scala\">u_sync_fifo.io.Writer.WriteData := io.AxisSlv.bits.Tlast ## io.AxisSlv.bits.Tdata u_sync_fifo.io.Writer.WriteEn := io.AxisSlv.valid &amp; io.AxisSlv.ready  u_sync_fifo.io.Reader.ReadEn := (CheckerStReg === ST_SEND &amp;&amp; io.AxisMst.ready === 1.U)   io.AxisMst.valid := (CheckerStReg === ST_SEND &amp;&amp; u_sync_fifo.io.Reader.Empty === 0.U)  io.AxisMst.bits.Tdata := u_sync_fifo.io.Reader.ReadData(7, 0) io.AxisMst.bits.Tlast := u_sync_fifo.io.Reader.ReadData(8)<\/code><\/pre>\n<p>\u0417\u0434\u0435\u0441\u044c, \u043e\u043f\u0435\u0440\u0430\u043d\u0434 ## \u044d\u0442\u043e \u043a\u043e\u043d\u043a\u0430\u0442\u0435\u043d\u0430\u0446\u0438\u044f \u0448\u0438\u043d, \u0430\u043d\u0430\u043b\u043e\u0433 {} \u0432 SystemVerilog.<\/p>\n<p>\u041a\u043e\u0434 \u0438\u0442\u043e\u0433\u043e\u0432\u044b\u0439 \u043c\u043e\u0434\u0443\u043b\u044f \u043f\u0440\u0438\u0432\u0435\u0434\u0435\u043d \u043d\u0438\u0436\u0435 \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/chisel-empty\/blob\/master\/src\/main\/scala\/axis_crc_ckecker_pkg\/AxisCrcChecker.scala\" rel=\"noopener noreferrer nofollow\">AxisCrcChecker.scala<\/a>)<\/p>\n<details class=\"spoiler\">\n<summary>AxisCrcChecker<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"scala\">package eht_frame_filter_pkg  import chisel3._ import chisel3.util._  import fifo_pkg._  class calc_crc extends HasBlackBoxResource {   val io = IO (new Bundle {     val CRC_I   = Input(UInt(8.W))     val DATA_I  = Input(UInt(8.W))     val CRC_O   = Output(UInt(8.W))   } )   addResource(\"calc_crc.v\") }  class AxisBus extends Bundle {   val Tlast = Bool()       val Tdata = UInt(8.W) }  class AxisCrcChecker extends Module {    val io = IO(new Bundle {                     val AxisSlv = Flipped(new DecoupledIO(new AxisBus))     val AxisMst = new DecoupledIO(new AxisBus)   } )     val PacketReceived  = Wire(Bool())   val RacketSended    = Wire(Bool())   val CrcInReg        = RegInit(\"hFF\".U(8.W))   val CrcOut          = Wire(UInt(8.W))   val FifoRstReg      = RegInit(1.U(1.W))    object State extends ChiselEnum {     val ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND = Value   }   import State._   val CheckerStReg = RegInit(ST_RECEIVE)    PacketReceived := io.AxisSlv.valid &amp; io.AxisSlv.ready &amp; io.AxisSlv.bits.Tlast    RacketSended := io.AxisMst.valid &amp; io.AxisMst.ready &amp; io.AxisMst.bits.Tlast      switch (CheckerStReg) {     is (ST_RECEIVE) {       when (PacketReceived === 1.U) {         CheckerStReg := ST_CHECK       }     }     is (ST_CHECK) {       when (CrcInReg === 0.U) {         CheckerStReg := ST_SEND       }       .otherwise {         CheckerStReg := ST_RESET       }     }     is (ST_RESET) {       CheckerStReg := ST_RECEIVE     }     is (ST_SEND) {       when (RacketSended === 1.U) {         CheckerStReg := ST_RECEIVE       }     }   }    val AxisSlvTready = RegInit(0.U(1.W))   when (PacketReceived === 1.U) {     AxisSlvTready := 0.U   }   .elsewhen (CheckerStReg === ST_RECEIVE) {     AxisSlvTready := 1.U   }    io.AxisSlv.ready := AxisSlvTready    when (io.AxisSlv.valid &amp; io.AxisSlv.ready) {     CrcInReg := CrcOut   }   .elsewhen (CheckerStReg === ST_CHECK) {     CrcInReg := \"hFF\".U   }    val u_calc_crc = Module(new calc_crc())    u_calc_crc.io.CRC_I   := CrcInReg   u_calc_crc.io.DATA_I  := io.AxisSlv.bits.Tdata   CrcOut                := u_calc_crc.io.CRC_O    FifoRstReg := (CheckerStReg === ST_RESET)    val u_sync_fifo = Module(new SyncFifo(9, 1024))      u_sync_fifo.reset := (FifoRstReg === 1.U)    u_sync_fifo.io.Writer.WriteData := io.AxisSlv.bits.Tlast ## io.AxisSlv.bits.Tdata   u_sync_fifo.io.Writer.WriteEn := io.AxisSlv.valid &amp; io.AxisSlv.ready    u_sync_fifo.io.Reader.ReadEn := (CheckerStReg === ST_SEND &amp;&amp; io.AxisMst.ready === 1.U)     io.AxisMst.valid := (CheckerStReg === ST_SEND &amp;&amp; u_sync_fifo.io.Reader.Empty === 0.U)    io.AxisMst.bits.Tdata := u_sync_fifo.io.Reader.ReadData(7, 0)   io.AxisMst.bits.Tlast := u_sync_fifo.io.Reader.ReadData(8) }  object AxisCrcCheckerMain extends App {   println(\"Generating the hardware\")   emitVerilog(new AxisCrcChecker(), Array(\"--target-dir\", \"generated\")) }<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u0417\u0430\u043f\u0443\u0441\u0442\u0438\u0432 \u0442\u0440\u0430\u043d\u0441\u043b\u044f\u0446\u0438\u044e, \u0431\u0443\u0434\u0435\u0442 \u043f\u043e\u043b\u0443\u0447\u0435\u043d \u0444\u0430\u0439\u043b <a href=\"https:\/\/github.com\/Finnetrib\/chisel-empty\/blob\/master\/generated\/AxisCrcChecker.v\" rel=\"noopener noreferrer nofollow\">AxisCrcChecker.v<\/a>, \u0441\u043e\u0434\u0435\u0440\u0436\u0430\u0449\u0438\u0439 \u043a\u043e\u0434 \u043d\u0430 verilog. \u0412 \u0446\u0435\u043b\u043e\u043c, \u0444\u0430\u0439\u043b \u0438\u043c\u0435\u0435\u0442 \u0447\u0438\u0442\u0430\u0435\u043c\u044b\u0439 \u0432\u0438\u0434, \u043a\u0430\u0436\u0434\u044b\u0439 \u043e\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0439 \u043c\u043e\u0434\u0443\u043b\u044c \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 Chisel \u043f\u0440\u0435\u0434\u0441\u0442\u0430\u0432\u043b\u044f\u0435\u0442 \u0441\u043e\u0431\u043e\u0439 \u043e\u0434\u0438\u043d always \u0431\u043b\u043e\u043a.<\/p>\n<p>\u0417\u0430\u043f\u0443\u0441\u0442\u0438\u0432 \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u0440\u0430\u043d\u0435\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u043d\u043e\u0433\u043e \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0443 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u043d\u043e\u0433\u043e \u0444\u0430\u0439\u043b\u0430, \u0443\u0432\u0438\u0434\u0438\u043c \u0442\u0430\u043a\u043e\u0439 \u0436\u0435 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442:<\/p>\n<pre><code class=\"bash\"># ------------------------------------------------------------ #                    TEST PARAMS #                    TEST CHISEL SOURCES # Simulation run with default random seed # ------------------------------------------------------------ # [ENV] Run count = 1447 # [ENV] Socreboard good packet =  691, scoreboard bad packet =  756 # &gt;&gt;&gt;&gt;&gt; SUCCESS<\/code><\/pre>\n<p>\u0417\u043d\u0430\u0447\u0438\u0442 \u043c\u043e\u0434\u0443\u043b\u044c, \u043d\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0439 \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 Chisel \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d \u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u043e.<\/p>\n<p><a class=\"anchor\" name=\"5\" id=\"5\"><\/a><\/p>\n<h2>5 \u0412\u044b\u0432\u043e\u0434\u044b<\/h2>\n<p>\u0421\u0443\u0431\u044a\u0435\u043a\u0442\u0438\u0432\u043d\u043e\u0435 \u043c\u043d\u0435\u043d\u0438\u0435 \u0442\u0430\u043a\u043e\u0432\u043e:<\/p>\n<ol>\n<li>\n<p>\u0421\u043c\u0435\u043d\u0430 \u044f\u0437\u044b\u043a\u0430 \u0432\u044b\u0437\u044b\u0432\u0430\u0435\u0442 \u043b\u043e\u043c\u043a\u0443, \u043f\u043e\u043d\u0430\u0447\u0430\u043b\u0443 \u0432\u0441\u0435\u0433\u0434\u0430 \u0431\u0443\u0434\u0435\u0442 \u0441\u043e\u043f\u0440\u043e\u0442\u0438\u0432\u043b\u0435\u043d\u0438\u0435 \u043d\u043e\u0432\u043e\u043c\u0443, \u044d\u0442\u043e \u043d\u043e\u0440\u043c\u0430\u043b\u044c\u043d\u043e.<\/p>\n<\/li>\n<li>\n<p>\u041d\u0435 \u043f\u043e\u043d\u0440\u0430\u0432\u0438\u043b\u0430\u0441\u044c \u0432 Chisel \u0440\u0430\u0431\u043e\u0442\u0430 \u0441\u043e \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u0430\u043c\u0438 \u0434\u0430\u043d\u043d\u044b\u0445. \u041f\u043e \u0440\u0430\u0431\u043e\u0442\u0435 \u0447\u0430\u0441\u0442\u043e \u043f\u0440\u0438\u0445\u043e\u0434\u0438\u0442\u0441\u044f \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u044b\u0432\u0430\u0442\u044c \u0440\u0430\u0437\u0431\u043e\u0440 \u043a\u0430\u043a\u0438\u0445-\u0442\u043e \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440 \u0434\u0430\u043d\u043d\u044b\u0445, struct \u0438 union \u0432 SystemVerilog \u0441 \u044d\u0442\u0438\u043c \u043f\u043e\u043c\u043e\u0433\u0430\u044e\u0442. <\/p>\n<\/li>\n<li>\n<p>\u041d\u0435 \u043f\u043e\u043d\u0440\u0430\u0432\u0438\u043b\u043e\u0441\u044c, \u0447\u0442\u043e \u0432 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442\u0435 \u0442\u0440\u0430\u043d\u0441\u043b\u044f\u0446\u0438\u0438 \u0432 verilog, \u0432\u0441\u0435 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u043c\u043e\u0435 \u0444\u0430\u0439\u043b\u0430 \u0440\u0430\u0437\u043c\u0435\u0449\u0430\u0435\u0442\u0441\u044f \u0432 \u043e\u0434\u043d\u043e\u043c always \u0431\u043b\u043e\u043a\u0435, \u0438 \u0441\u0438\u0433\u043d\u0430\u043b\u044b \u0443 \u043a\u043e\u0442\u043e\u0440\u044b\u0445 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442\u0441\u044f \u0441\u0438\u0433\u043d\u0430\u043b \u0441\u0431\u0440\u043e\u0441\u0430, \u0438 \u0441\u0438\u0433\u043d\u0430\u043b\u044b \u0443 \u043a\u043e\u0442\u043e\u0440\u044b\u0445 \u043d\u0435 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442\u0441\u044f \u0441\u0438\u0433\u043d\u0430\u043b \u0441\u0431\u0440\u043e\u0441\u0430. <\/p>\n<\/li>\n<li>\n<p>\u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0441\u0442\u0440\u043e\u043a \u0432 \u0431\u043b\u043e\u043a\u0435 \u043d\u0430 Chisel \u043c\u0435\u043d\u044c\u0448\u0435, \u0447\u0435\u043c \u0432 \u0431\u043b\u043e\u043a\u0435 \u043d\u0430 SystemVerilog.<\/p>\n<\/li>\n<li>\n<p>\u0412 \u043e\u0431\u0449\u0435\u043c, \u043c\u043e\u0439 \u0432\u044b\u0431\u043e\u0440 \u043d\u0430 \u0442\u0435\u043a\u0443\u0449\u0438\u0439 \u043c\u043e\u043c\u0435\u043d\u0442 &#8212; SystemVerilog.<\/p>\n<\/li>\n<\/ol>\n<\/div>\n<\/div>\n<\/div>\n<p><!----><!----><\/div>\n<p><!----><!----><br \/> \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438 <a href=\"https:\/\/habr.com\/ru\/articles\/891966\/\"> https:\/\/habr.com\/ru\/articles\/891966\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<div><!--[--><!--]--><\/div>\n<div id=\"post-content-body\">\n<div>\n<div class=\"article-formatted-body article-formatted-body article-formatted-body_version-2\">\n<div xmlns=\"http:\/\/www.w3.org\/1999\/xhtml\">\n<p>\u041d\u0435\u0434\u0430\u0432\u043d\u043e \u0432\u043e\u0437\u043d\u0438\u043a\u043b\u0430 \u043f\u043e\u0442\u0440\u0435\u0431\u043d\u043e\u0441\u0442\u044c \u0432 \u0431\u044b\u0441\u0442\u0440\u043e\u043c \u043f\u043e\u0433\u0440\u0443\u0436\u0435\u043d\u0438\u0438 \u0432 \u044f\u0437\u044b\u043a <a href=\"https:\/\/en.wikipedia.org\/wiki\/Chisel_(programming_language)\" rel=\"noopener noreferrer nofollow\">Chisel<\/a>. \u0427\u0442\u043e\u0431\u044b \u043f\u043e\u043f\u0440\u043e\u0431\u043e\u0432\u0430\u0442\u044c \u043d\u043e\u0432\u044b\u0439 \u044f\u0437\u044b\u043a, \u043d\u0435 \u0445\u043e\u0442\u0435\u043b\u043e\u0441\u044c \u043f\u0438\u0441\u0430\u0442\u044c \u0441\u0447\u0435\u0442\u0447\u0438\u043a \u0438\u043b\u0438 \u0441\u0443\u043c\u043c\u0430\u0442\u043e\u0440, \u0430 \u0447\u0442\u043e-\u0442\u043e \u043f\u0440\u0438\u0431\u043b\u0438\u0436\u0435\u043d\u043d\u043e\u0435 \u043a \u0440\u0430\u0431\u043e\u0447\u0438\u043c \u043c\u043e\u043c\u0435\u043d\u0442\u0430\u043c. \u0418 \u0442\u0430\u043a, \u0441\u0444\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u043c \u0437\u0430\u0434\u0430\u043d\u0438\u0435 \u043d\u0430 \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u043c\u044b\u0439 \u0431\u043b\u043e\u043a:<\/p>\n<ul>\n<li>\n<p>\u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445 &#8212; AXI-Stream;<\/p>\n<\/li>\n<li>\n<p>\u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445 &#8212; AXI-Stream;<\/p>\n<\/li>\n<li>\n<p>\u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u044b\u0439 \u0440\u0430\u0437\u043c\u0435\u0440 \u043e\u0431\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u043c\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 &#8212; 1024 \u0431\u0430\u0439\u0442\u0430;<\/p>\n<\/li>\n<li>\n<p>\u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0435\u0435 \u0441\u043b\u043e\u0432\u043e \u043f\u0430\u043a\u0435\u0442\u0430 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b \u043e\u0442 \u043f\u0430\u043a\u0435\u0442\u0430, \u043f\u043e\u0441\u0447\u0438\u0442\u0430\u043d\u043d\u043e\u0435 \u043f\u043e \u0430\u043b\u0433\u043e\u0440\u0438\u0442\u043c\u0443 crc8;<\/p>\n<\/li>\n<li>\n<p>\u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e \u0432\u044b\u043f\u043e\u043b\u043d\u0438\u0442\u044c \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0443 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0415\u0441\u043b\u0438 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0430\u044f \u0441\u0443\u043c\u043c\u0430 \u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u0430, \u043f\u0435\u0440\u0435\u0434\u0430\u0442\u044c \u043f\u0430\u043a\u0435\u0442 \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445, \u0438\u043d\u0430\u0447\u0435, \u0443\u0434\u0430\u043b\u0438\u0442\u044c \u043f\u0430\u043a\u0435\u0442.<\/p>\n<\/li>\n<\/ul>\n<h2>\u0421\u043e\u0434\u0435\u0440\u0436\u0430\u043d\u0438\u0435<\/h2>\n<p><a href=\"#1\" rel=\"noopener noreferrer nofollow\">1 \u041e\u0431\u0449\u0430\u044f \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f<\/a><\/p>\n<p><a href=\"#2\" rel=\"noopener noreferrer nofollow\">2 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 SystemVerilog<\/a><\/p>\n<p><a href=\"#3\" rel=\"noopener noreferrer nofollow\">3 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f<\/a><\/p>\n<p><a href=\"#4\" rel=\"noopener noreferrer nofollow\">4 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 Chisel<\/a><\/p>\n<p><a href=\"#5\" rel=\"noopener noreferrer nofollow\">5 \u0412\u044b\u0432\u043e\u0434\u044b<\/a><\/p>\n<p><a class=\"anchor\" name=\"1\" id=\"1\"><\/a><\/p>\n<h2>1 \u041e\u0431\u0449\u0430\u044f \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f<\/h2>\n<p>\u0410\u043b\u0433\u043e\u0440\u0438\u0442\u043c \u0440\u0430\u0431\u043e\u0442\u044b \u0431\u043b\u043e\u043a\u0430 \u0431\u0443\u0434\u0435\u0442 \u0441\u043b\u0435\u0434\u0443\u044e\u0449\u0438\u043c:<\/p>\n<ol>\n<li>\n<p>\u041f\u0440\u0438\u0435\u043c \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445, \u043f\u043e\u0434\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b, \u0437\u0430\u043f\u0438\u0441\u044c \u043f\u0430\u043a\u0435\u0442\u0430 \u0432 FIFO. \u041f\u0440\u0438\u0435\u043c \u043f\u0430\u043a\u0435\u0442\u0430 \u0437\u0430\u043a\u0430\u043d\u0447\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u043f\u0440\u0438 \u043f\u043e\u0441\u0442\u0443\u043f\u043b\u0435\u043d\u0438\u0438 \u043f\u0440\u0438\u0437\u043d\u0430\u043a\u0430 \u043a\u043e\u043d\u0446\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 (tlast = 1, \u043a\u043e\u0433\u0434\u0430 \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d\u044b \u0441\u0438\u0433\u043d\u0430\u043b\u044b tvalid = 1 \u0438 tready = 1). \u041f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u0430\u043d\u0430\u043b\u0438\u0437\u0430 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b.<\/p>\n<\/li>\n<li>\n<p>\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0415\u0441\u043b\u0438 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u0430\u044f \u0441\u0443\u043c\u043c\u0430 \u043a\u043e\u0440\u0440\u0435\u043a\u0442\u043d\u0430 (\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b \u0440\u0430\u0432\u043d\u043e 0), \u0442\u043e \u043f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 FIFO \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445. \u0418\u043d\u0430\u0447\u0435, \u043f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u0443\u0434\u0430\u043b\u0435\u043d\u0438\u044f \u043f\u0430\u043a\u0435\u0442\u0430.<\/p>\n<\/li>\n<li>\n<p>\u0423\u0434\u0430\u043b\u0435\u043d\u0438\u0435 \u043f\u0430\u043a\u0435\u0442\u0430. \u0412\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442\u0441\u044f \u0441\u0431\u0440\u043e\u0441 FIFO, \u043f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445.<\/p>\n<\/li>\n<li>\n<p>\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 FIFO \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445. \u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0437\u0430\u043a\u0430\u043d\u0447\u0438\u0432\u0430\u0435\u0442\u0441\u044f, \u043a\u043e\u0433\u0434\u0430 \u0431\u0443\u0434\u0435\u0442 \u0432\u044b\u0434\u0430\u043d \u043a\u043e\u043d\u0435\u0446 \u043f\u0430\u043a\u0435\u0442\u0430 (tlast = 1, \u043a\u043e\u0433\u0434\u0430 \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d\u044b \u0441\u0438\u0433\u043d\u0430\u043b\u044b tvalid = 1 \u0438 tready = 1). \u041f\u0435\u0440\u0435\u0445\u043e\u0434 \u0432 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u0430 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u0438\u044f \u0434\u0430\u043d\u043d\u044b\u0445<\/p>\n<\/li>\n<\/ol>\n<p>\u0410\u043b\u0433\u043e\u0440\u0438\u0442\u043c \u043d\u0435 \u043e\u0441\u043e\u0431\u043e \u0441\u043b\u043e\u0436\u043d\u044b\u0439, \u0447\u0442\u043e\u0431\u044b \u043f\u0440\u043e\u0441\u0442\u043e \u043f\u043e\u0449\u0443\u043f\u0430\u0442\u044c \u043d\u043e\u0432\u044b\u0439 \u044f\u0437\u044b\u043a.<\/p>\n<p><a class=\"anchor\" name=\"2\" id=\"2\"><\/a><\/p>\n<h2>2 \u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0431\u043b\u043e\u043a\u0430 \u043d\u0430 SystemVerilog<\/h2>\n<p>\u0421\u043d\u0430\u0447\u0430\u043b\u0430 \u0431\u0443\u0434\u0435\u0442 \u0432\u044b\u043f\u043e\u043b\u043d\u0435\u043d\u0430 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043d\u0430 SystemVerilog, \u0447\u0442\u043e\u0431\u044b \u043d\u0430 \u044d\u0442\u043e\u0439 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043e\u043f\u0440\u043e\u0431\u043e\u0432\u0430\u0442\u044c \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0435 \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u0435, \u0430 \u043f\u043e\u0442\u043e\u043c \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u044d\u0442\u043e\u0433\u043e \u0442\u0435\u0441\u0442\u043e\u0432\u043e\u0433\u043e \u043e\u043a\u0440\u0443\u0436\u0435\u043d\u0438\u044f \u0432\u0435\u0440\u0438\u0444\u0438\u0446\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044e \u043d\u0430 Chisel.<\/p>\n<p>\u0414\u043b\u044f \u043d\u0430\u0447\u0430\u043b\u0430 \u043f\u043e\u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f \u0431\u043b\u043e\u043a \u0434\u043b\u044f \u0445\u0440\u0430\u043d\u0435\u043d\u0438\u044f \u043f\u0430\u043a\u0435\u0442\u0430. \u0411\u0443\u0434\u0435\u043c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c FIFO, \u043a\u043e\u0434 \u043f\u0440\u043e\u0441\u0442\u043e\u0433\u043e FIFO \u043f\u0440\u0438\u0432\u0435\u0434\u0435\u043d \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/src\/sync_fifo.sv\" rel=\"noopener noreferrer nofollow\">sync_fifo.sv<\/a>)<\/p>\n<details class=\"spoiler\">\n<summary>sync_fifo<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">`default_nettype none  module sync_fifo #(     parameter int FIFO_DEPTH            = 8,     parameter int DATA_WIDTH            = 32 )(     input  wire logic                   CLK_I,     input  wire logic                   RST_I,      input  wire logic                   WR_EN_I,     input  wire logic [DATA_WIDTH-1:0]  WR_DATA_I,     output var  logic                   FULL_O,      input  wire logic                   RD_EN_I,     output var  logic [DATA_WIDTH-1:0]  RD_DATA_O,     output var  logic                   EMPTY_O );  localparam int ADDR_WIDTH = $clog2(FIFO_DEPTH);  logic [ADDR_WIDTH:0]    wr_ptr; logic [ADDR_WIDTH:0]    rd_ptr; logic [DATA_WIDTH-1:0]  fifo_cell [FIFO_DEPTH-1:0];  always_comb begin : pc_full_o     FULL_O = (  (wr_ptr[ADDR_WIDTH] != rd_ptr[ADDR_WIDTH]) &amp;&amp;                 (wr_ptr[ADDR_WIDTH - 1:0] == rd_ptr[ADDR_WIDTH - 1:0]) ) ? 1'b1 : 1'b0; end : pc_full_o  always_comb begin : pc_empty_o     EMPTY_O = (wr_ptr == rd_ptr) ? 1'b1 : 1'b0; end : pc_empty_o  always_ff @(posedge CLK_I) begin : ps_wr_ptr     if (RST_I) begin         wr_ptr &lt;= '0;     end     else begin         if (FULL_O == 1'b0 &amp;&amp; WR_EN_I == 1'b1) begin             wr_ptr &lt;= wr_ptr + 1'b1;         end     end end : ps_wr_ptr  always_ff @(posedge CLK_I) begin : ps_rd_ptr     if (RST_I) begin         rd_ptr &lt;= '0;     end     else begin         if (EMPTY_O == 1'b0 &amp;&amp; RD_EN_I == 1'b1) begin             rd_ptr &lt;= rd_ptr + 1'b1;         end     end end : ps_rd_ptr  always_ff @(posedge CLK_I) begin : ps_fifo_cell     if (FULL_O == 1'b0 &amp;&amp; WR_EN_I == 1'b1) begin         fifo_cell[wr_ptr[ADDR_WIDTH-1:0]] &lt;= WR_DATA_I;     end end : ps_fifo_cell  always_comb begin : pc_rd_data_o     RD_DATA_O = fifo_cell[rd_ptr[ADDR_WIDTH-1:0]]; end : pc_rd_data_o  endmodule  `resetall<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u0414\u0432\u0430 \u0443\u043a\u0430\u0437\u0430\u0442\u0435\u043b\u044f, \u043d\u0430 \u0447\u0442\u0435\u043d\u0438\u0435 \u0438 \u043d\u0430 \u0437\u0430\u043f\u0438\u0441\u044c, \u043c\u0430\u0441\u0441\u0438\u0432 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432.<\/p>\n<p>\u0414\u0430\u043b\u0435\u0435, \u043f\u043e\u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f \u0431\u043b\u043e\u043a \u0434\u043b\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b. \u0412\u043e\u0437\u044c\u043c\u0435\u043c \u043f\u043e \u043f\u0435\u0440\u0432\u043e\u0439 \u0441\u0441\u044b\u043b\u043a\u0435 \u0432 \u0433\u0443\u0433\u043b\u0435. \u041a\u043e\u0434 \u043d\u0438\u0436\u0435 \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/src\/calc_crc.v\" rel=\"noopener noreferrer nofollow\">calc_crc.v<\/a>)<\/p>\n<details class=\"spoiler\">\n<summary>calc_crc<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">\/\/ vim: ts=4 sw=4 expandtab  \/\/ THIS IS GENERATED VERILOG CODE. \/\/ https:\/\/bues.ch\/h\/crcgen \/\/  \/\/ This code is Public Domain. \/\/ Permission to use, copy, modify, and\/or distribute this software for any \/\/ purpose with or without fee is hereby granted. \/\/  \/\/ THE SOFTWARE IS PROVIDED \"AS IS\" AND THE AUTHOR DISCLAIMS ALL WARRANTIES \/\/ WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF \/\/ MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY \/\/ SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES WHATSOEVER \/\/ RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN ACTION OF CONTRACT, \/\/ NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF OR IN CONNECTION WITH THE \/\/ USE OR PERFORMANCE OF THIS SOFTWARE.  `ifndef CALC_CRC_V_ `define CALC_CRC_V_  \/\/ CRC polynomial coefficients: x^8 + x^2 + x + 1 \/\/                              0x7 (hex) \/\/ CRC width:                   8 bits \/\/ CRC shift direction:         left (big endian) \/\/ Input word width:            8 bits  module calc_crc (     input [7:0] CRC_I,     input [7:0] DATA_I,     output [7:0] CRC_O );     assign CRC_O[0] = CRC_I[0] ^ CRC_I[6] ^ CRC_I[7] ^ DATA_I[0] ^ DATA_I[6] ^ DATA_I[7];     assign CRC_O[1] = CRC_I[0] ^ CRC_I[1] ^ CRC_I[6] ^ DATA_I[0] ^ DATA_I[1] ^ DATA_I[6];     assign CRC_O[2] = CRC_I[0] ^ CRC_I[1] ^ CRC_I[2] ^ CRC_I[6] ^ DATA_I[0] ^ DATA_I[1] ^ DATA_I[2] ^ DATA_I[6];     assign CRC_O[3] = CRC_I[1] ^ CRC_I[2] ^ CRC_I[3] ^ CRC_I[7] ^ DATA_I[1] ^ DATA_I[2] ^ DATA_I[3] ^ DATA_I[7];     assign CRC_O[4] = CRC_I[2] ^ CRC_I[3] ^ CRC_I[4] ^ DATA_I[2] ^ DATA_I[3] ^ DATA_I[4];     assign CRC_O[5] = CRC_I[3] ^ CRC_I[4] ^ CRC_I[5] ^ DATA_I[3] ^ DATA_I[4] ^ DATA_I[5];     assign CRC_O[6] = CRC_I[4] ^ CRC_I[5] ^ CRC_I[6] ^ DATA_I[4] ^ DATA_I[5] ^ DATA_I[6];     assign CRC_O[7] = CRC_I[5] ^ CRC_I[6] ^ CRC_I[7] ^ DATA_I[5] ^ DATA_I[6] ^ DATA_I[7]; endmodule  `endif \/\/ CALC_CRC_V_<\/code><\/pre>\n<\/p>\n<\/div>\n<\/details>\n<p>\u041e\u043f\u0438\u0448\u0435\u043c \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0449\u0438\u0439 \u0430\u0432\u0442\u043e\u043c\u0430\u0442. \u041e\u0431\u044a\u044f\u0432\u043b\u0435\u043d\u0438\u0435 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u044b\u0445 \u0441\u043e\u0441\u0442\u043e\u044f\u043d\u0438\u0439:<\/p>\n<pre><code class=\"vhdl\">enum logic [1:0] {ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND} checker_st;<\/code><\/pre>\n<p>\u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u044f\u044e\u0449\u0435\u0433\u043e \u0430\u0432\u0442\u043e\u043c\u0430\u0442\u0430:<\/p>\n<pre><code class=\"vhdl\">always_ff @(posedge CLK_I) begin : ps_checker_st     if (RST_I) begin         checker_st &lt;= ST_RECEIVE;     end     else begin         case (checker_st)             ST_RECEIVE : begin                 if (packet_received) begin                     checker_st &lt;= ST_CHECK;                 end             end             ST_CHECK : begin                 if (crc_in == '0) begin                     checker_st &lt;= ST_SEND;                 end                 else begin                     checker_st &lt;= ST_RESET;                 end             end             ST_RESET : begin                 checker_st &lt;= ST_RECEIVE;             end             ST_SEND : begin                 if (packet_sended) begin                     checker_st &lt;= ST_RECEIVE;                 end             end         endcase     end end : ps_checker_st<\/code><\/pre>\n<p>\u041f\u0440\u0438\u0437\u043d\u0430\u043a\u0438 \u043e\u043a\u043e\u043d\u0447\u0430\u043d\u0438\u044f \u043f\u0440\u0438\u0435\u043c\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438 \u043e\u043a\u043e\u043d\u0447\u0430\u043d\u0438\u044f \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u043f\u0430\u043a\u0435\u0442\u0430:<\/p>\n<pre><code class=\"vhdl\">always_comb begin : pc_packet_received     packet_received = AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready &amp; AXIS_SLV_IF.tlast; end : pc_packet_received  always_comb begin : pc_packet_sended     packet_sended = AXIS_MST_IF.tvalid &amp; AXIS_MST_IF.tready &amp; AXIS_MST_IF.tlast; end : pc_packet_sended<\/code><\/pre>\n<p>\u041f\u043e\u0434\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b:<\/p>\n<pre><code class=\"vhdl\">always_ff @(posedge CLK_I) begin : ps_crc_in     if (RST_I) begin         crc_in &lt;= '1;     end     else begin         if (AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready) begin             crc_in &lt;= crc_out;         end         else if (checker_st == ST_CHECK) begin             crc_in &lt;= '1;         end     end end : ps_crc_in  calc_crc u_calc_crc(     .CRC_I  (crc_in),     .DATA_I (AXIS_SLV_IF.tdata),     .CRC_O  (crc_out) );<\/code><\/pre>\n<p>\u0421\u0431\u0440\u043e\u0441 FIFO \u0432 \u0441\u043b\u0443\u0447\u0430\u0435 \u043d\u0435\u0441\u043e\u0432\u043f\u0430\u0434\u0435\u043d\u0438\u044f \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b:<\/p>\n<pre><code class=\"vhdl\">always_ff @(posedge CLK_I) begin : ps_fifo_rst     if (RST_I) begin         fifo_rst &lt;= 1'b1;     end     else begin         fifo_rst &lt;= (checker_st == ST_RESET) ? 1'b1 : 1'b0;     end end : ps_fifo_rst<\/code><\/pre>\n<p>\u0414\u043b\u044f \u0443\u0434\u043e\u0431\u0441\u0442\u0432\u0430 \u0437\u0430\u043f\u0438\u0441\u0438\/\u0447\u0442\u0435\u043d\u0438\u0435 \u0432\/\u0438\u0437 FIFO \u043e\u0431\u044a\u044f\u0432\u0438\u043c \u0441\u0442\u0440\u0443\u043a\u0442\u0443\u0440\u0443 \u0438 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u044b\u0435 \u0441\u0438\u0433\u043d\u0430\u043b\u044b:<\/p>\n<pre><code class=\"vhdl\"> localparam int AXIS_DW = $bits(AXIS_SLV_IF.tdata);  enum logic [1:0] {ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND} checker_st;  typedef struct packed {     logic               tlast;     logic [AXIS_DW-1:0] tdata; } fifo_data_t;  fifo_data_t fifo_data_w; logic       fifo_write; logic       fifo_empty; logic       fifo_read; fifo_data_t fifo_data_r;<\/code><\/pre>\n<p>\u0417\u0430\u043f\u0438\u0441\u044c \u0434\u0430\u043d\u043d\u044b\u0445 \u0432 FIFO:<\/p>\n<pre><code class=\"vhdl\">always_comb begin : pc_fifo_data_w     fifo_data_w.tdata = AXIS_SLV_IF.tdata;     fifo_data_w.tlast = AXIS_SLV_IF.tlast; end : pc_fifo_data_w  always_comb begin : pc_fifo_write     fifo_write = AXIS_SLV_IF.tvalid &amp; AXIS_SLV_IF.tready; end : pc_fifo_write<\/code><\/pre>\n<p>\u0427\u0442\u0435\u043d\u0438\u0435 \u0438\u0437 FIFO \u0438 \u0432\u044b\u0434\u0430\u0447\u0430 \u0432 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445:<\/p>\n<pre><code class=\"vhdl\">always_comb begin : pc_fifo_read     fifo_read = (checker_st == ST_SEND &amp;&amp; AXIS_MST_IF.tready == 1'b1) ? 1'b1 : 1'b0; end : pc_fifo_read  always_comb begin : pc_axis_mst_if_tvalid     AXIS_MST_IF.tvalid = (checker_st == ST_SEND &amp;&amp; fifo_empty == 1'b0) ? 1'b1 : 1'b0; end : pc_axis_mst_if_tvalid  always_comb begin : pc_axis_mst_if_out     AXIS_MST_IF.tdata = (AXIS_MST_IF.tvalid) ? fifo_data_r.tdata : 'x;     AXIS_MST_IF.tlast = (AXIS_MST_IF.tvalid) ? fifo_data_r.tlast : 'x; end : pc_axis_mst_if_out<\/code><\/pre>\n<p>\u0418\u0442\u043e\u0433\u043e\u0432\u044b\u0439 \u0431\u043b\u043e\u043a, \u043f\u043e\u0434 \u0441\u043f\u043e\u0439\u043b\u0435\u0440\u043e\u043c \u0438 \u043d\u0430 \u0433\u0438\u0442\u0445\u0430\u0431 (<a href=\"https:\/\/github.com\/Finnetrib\/axis_crc_checker\/blob\/main\/RTL\/src\/axis_crc_checker.sv\" rel=\"noopener noreferrer nofollow\">axis_crc_checker.sv)<\/a>:<\/p>\n<details class=\"spoiler\">\n<summary>axis_crc_checker<\/summary>\n<div class=\"spoiler__content\">\n<pre><code class=\"vhdl\">`default_nettype none  module axis_crc_checker (     input wire logic    CLK_I,     input wire logic    RST_I,      AXIS_Bus.slave      AXIS_SLV_IF,     AXIS_Bus.master     AXIS_MST_IF );  localparam int AXIS_DW = $bits(AXIS_SLV_IF.tdata);  enum logic [1:0] {ST_RECEIVE, ST_CHECK, ST_RESET, ST_SEND} checker_st;  typedef struct packed {     logic               tlast;     logic [AXIS_DW-1:0] tdata; } fifo_data_t;  logic       packet_received; logic       packet_sended; logic [7:0] crc_in; logic [7:0] crc_out; logic       fifo_rst; fifo_data_t fifo_data_w; logic       fifo_write; logic       fifo_empty; logic       fifo_read;<\/code><\/pre>\n<\/div>\n<\/details>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-452884","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/452884","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=452884"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/452884\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=452884"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=452884"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=452884"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}