{"id":463310,"date":"2025-06-13T15:00:56","date_gmt":"2025-06-13T15:00:56","guid":{"rendered":"http:\/\/savepearlharbor.com\/?p=463310"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=463310","title":{"rendered":"\u0420\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f ModBus RTU Slave \u043d\u0430 stm32<\/span>"},"content":{"rendered":"
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\u0412 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u043e\u0439 \u0420\u042d\u0410 \u0434\u043b\u044f \u043d\u0443\u0436\u0434 \u043f\u0440\u043e\u043c\u044b\u0448\u043b\u0435\u043d\u043d\u043e\u0433\u043e \u043a\u043e\u043c\u043f\u043b\u0435\u043a\u0441\u0430 \u0432\u0441\u0442\u0440\u0435\u0447\u0430\u044e\u0442\u0441\u044f \u0437\u0430\u0434\u0430\u0447\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b\u0430 ModBus RTU \u043d\u0430 \u041c\u041a. \u0412 \u0441\u0435\u0442\u0438 \u0435\u0441\u0442\u044c \u0433\u043e\u0442\u043e\u0432\u044b\u0435 \u0431\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a\u0438 \u043f\u043e\u0434 \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0440\u0435\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u0438. \u041d\u043e \u0447\u0430\u0441\u0442\u043e \u0437\u0430\u043a\u0430\u0437\u0447\u0438\u043a \u0432\u044b\u0431\u0438\u0440\u0430\u0435\u0442 \u041c\u041a \u0432 \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u043c\u043f\u043b\u0435\u043a\u0442\u0430\u0446\u0438\u0438, \u043a\u0443\u0434\u0430 \u043d\u0435 \u043e\u0441\u043e\u0431\u043e \u0438 \u043f\u043e\u0441\u0442\u0430\u0432\u0438\u0448\u044c \u0441\u0438\u0441\u0442\u0435\u043c\u0443 \u0440\u0435\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u0438. <\/p>\n

\u0421\u0442\u0430\u0442\u044c\u044f \u0431\u0443\u0434\u0435\u0442 \u043f\u043e\u043b\u0435\u0437\u043d\u0430 \u043a\u0430\u043a \u043d\u0430\u0447\u0438\u043d\u0430\u044e\u0449\u0438\u043c \u0442\u0430\u043a \u0438 \u0442\u0435\u043c \u043a\u0442\u043e \u0432 \u0442\u0435\u043c\u0435.<\/p>\n

\u0418 \u0442\u0430\u043a… \u0415\u0441\u0442\u044c stm32f103ret6 (\u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u0442\u044c \u043c\u043e\u0436\u043d\u043e \u0438 \u043d\u0430 \u0434\u0440\u0443\u0433\u043e\u043c \u043a\u0440\u0438\u0441\u0442\u0430\u043b\u043b\u0435), \u0441\u0440\u0435\u0434\u0430 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 STM32CubeIDE 1.12.0.<\/p>\n

\u0417\u0430\u0434\u0430\u0447\u0430: \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u0442\u044c slave \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u043e, \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u044c 9600, \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b modbus rtu.<\/p>\n

\u041e\u043f\u0438\u0441\u0430\u043d\u0438\u0435 \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b\u0430 \u043e\u0431\u043c\u0435\u043d\u0430 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u0445\u043e\u0440\u043e\u0448\u043e \u043e\u043f\u0438\u0441\u0430\u043d\u043e \u0432 \u0441\u0435\u0442\u0438, \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f \u043f\u0440\u0435\u0434\u043e\u0441\u0442\u0430\u0432\u043b\u0435\u043d\u0430 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u043f\u043e\u0434\u0440\u043e\u0431\u043d\u043e.<\/p>\n

\u0414\u043b\u044f \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043d\u0430 \u041c\u041a \u0431\u0443\u0434\u0435\u043c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c USART1, TIM6, \u0432\u044b\u0432\u043e\u0434 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430 PA8 \u0434\u043b\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u043f\u0440\u0438\u043c\u0435\u043c\/\u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u043b\u044f \u0444\u0438\u0437\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0434\u0440\u0430\u0439\u0432\u0435\u0440\u0430 RS-485.<\/p>\n

\u0422\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 — \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u043a\u0432\u0430\u0440\u0446\u0435\u0432\u044b\u0439 \u0440\u0435\u0437\u043e\u043d\u0430\u0442\u043e\u0440 \u043d\u0430 8 \u041c\u0413\u0446.<\/p>\n

1. \u0421\u043e\u0437\u0434\u0430\u0435\u043c \u043f\u0440\u043e\u0435\u043a\u0442 \u0432 STM32CubeIDE, \u0432\u044b\u0431\u0440\u0430\u0432 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0443\u044e\u0449\u0438\u0439 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440. \u0418\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f \u0435\u0441\u0442\u044c \u0432 \u0441\u0435\u0442\u0438. \u0417\u0430\u043e\u0441\u0442\u0440\u044f\u0442\u044c \u043d\u0430 \u044d\u0442\u043e\u043c \u0432\u043d\u0438\u043c\u0430\u043d\u0438\u0435 \u043d\u0435 \u0431\u0443\u0434\u0443. <\/p>\n

2. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u0440\u043e\u0435\u043a\u0442\u0430. <\/p>\n

\u0417\u0430\u043f\u0443\u0441\u043a\u0430\u043c \u0444\u0430\u0439\u043b *.ioc \u0438\u0437 Project Explorer. \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Project Manager=>Code Generator. \u0421\u0442\u0430\u0432\u0438\u043c \u0433\u0430\u043b\u043e\u0447\u043a\u0443 Generate peripheral initialization as a pair of ‘.c\/ .h’ files per peripheral. (\u0414\u043b\u044f \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0438 \u0431\u0443\u0434\u0443\u0442 \u0441\u043e\u0437\u0434\u0430\u043d\u044b \u043e\u0442\u0434\u0435\u043b\u044c\u043d\u044b\u0435 \u0444\u0430\u0439\u043b\u044b \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0435)<\/p>\n

\"\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430<\/p>\n
\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u0440\u043e\u0435\u043a\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n

3. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f.<\/p>\n

\u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => System Core =>RCC \u0438 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c High Speed Clock.<\/p>\n

\"\u0412\u043a\u043b\u044e\u0447\u0430\u0435\u043c<\/p>\n
\u0412\u043a\u043b\u044e\u0447\u0430\u0435\u043c HSE<\/figcaption><\/div>\n<\/figure>\n

\u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Clock Configuration \u0438 \u043d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u0441\u0438\u0441\u0442\u0435\u043c\u0443 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043a\u0430\u043a \u043d\u0430 \u0440\u0438\u0441\u0443\u043d\u043a\u0435.<\/p>\n

\"\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430<\/p>\n
\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f<\/figcaption><\/div>\n<\/figure>\n

3. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 USART.<\/p>\n

\u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => Connectivity =>USART1. \u0412\u043e \u0432\u043a\u043b\u0430\u0434\u043a\u0443 \u043d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u044b \u043c\u043e\u0434\u0443\u043b\u044f \u0438 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u0433\u043b\u043e\u0431\u0430\u043b\u044c\u043d\u043e\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f. <\/p>\n

\"\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430<\/p>\n
\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 USART<\/figcaption><\/div>\n<\/figure>\n

<\/p>\n

\"\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f<\/p>\n
\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f USART<\/figcaption><\/div>\n<\/figure>\n

4. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 TIM6. \u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u0440\u0430\u0437 \u0432 500 \u043c\u043a\u0441. <\/p>\n

\u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => Timers =>TIM6. \u0412\u043e \u0432\u043a\u043b\u0430\u0434\u043a\u0443 \u043d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u044b \u043c\u043e\u0434\u0443\u043b\u044f \u0438 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u0433\u043b\u043e\u0431\u0430\u043b\u044c\u043d\u043e\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f.<\/p>\n

\"\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430<\/p>\n
\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f<\/figcaption><\/div>\n<\/figure>\n
\"\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f<\/p>\n
\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u0442\u0430\u0439\u043c\u0435\u0440\u0430<\/figcaption><\/div>\n<\/figure>\n

5. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0432\u044b\u0432\u043e\u0434\u0430 re_de.<\/p>\n

\u041d\u0430 \u043f\u043e\u043b\u0435 Pinout Viev \u043a\u043b\u0438\u043a\u0430\u0435\u043c PA8 \u0438 \u0432\u044b\u0431\u0438\u0440\u0430\u0435\u043c \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0443\u044e\u0449\u0443\u044e \u0444\u0443\u043d\u043a\u0446\u0438\u044e \u043f\u043e\u0440\u0442\u0430 \u0432\u0432\u043e\u0434\u0430\/\u0432\u044b\u0432\u043e\u0434\u0430<\/p>\n

\"\u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435<\/p>\n
\u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u043e\u0440\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n

\u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => System Core =>GPIO \u0438 \u0434\u0435\u043b\u0430\u0435\u043c \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0443 \u043f\u043e\u0440\u0442\u0430.<\/p>\n

\"\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430<\/p>\n
\u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u043e\u0440\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n

6. \u0413\u0435\u043d\u0435\u0440\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u0430. <\/p>\n

\u041d\u0430 \u043f\u0430\u043d\u0435\u043b\u0438 \u0437\u0430\u0434\u0430\u0447 \u043a\u043b\u0438\u043a\u0430\u0435\u043c \u043a\u043d\u043e\u043f\u043a\u0443 Device Configuration Tool Code Generation.<\/p>\n

\"\u0413\u0435\u043d\u0435\u0440\u0430\u0446\u0438\u044f<\/p>\n
\u0413\u0435\u043d\u0435\u0440\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n

7. \u0421\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u0444\u0430\u0439\u043b\u043e\u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0430.<\/p>\n

\u0412 \u0432\u043a\u043b\u0430\u0434\u043a\u0435 Project Explorer =>Core \u0432\u043e \u0432\u043a\u043b\u0430\u0434\u043a\u0430\u0445 Inc \u0438 Srs \u0441\u043e\u0437\u0434\u0430\u0435\u043c \u0444\u0430\u0439\u043b\u044b cpu_init.* \u0438 mod_bus_rtu_1.*<\/p>\n

\u0412 \u0444\u0430\u0439\u043b\u0435 cpu_init — \u0434\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0430\u044f \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430<\/p>\n

\u0412 \u0444\u0430\u0439\u043b\u0435 mod_bus_rtu_1 — \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b\u0430.<\/p>\n

\"\u0421\u043e\u0437\u0434\u0430\u043d\u0438\u0435<\/p>\n
\u0421\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u0444\u0430\u0439\u043b\u043e\u0432<\/figcaption><\/div>\n<\/figure>\n

\u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0444\u0430\u0439\u043b main.c \u0438 \u0434\u043e\u0431\u0430\u0432\u043b\u044f\u0435\u043c \u0441\u043e\u0437\u0434\u0430\u043d\u043d\u044b\u0435 \u0444\u0430\u0439\u043b\u044b \u043f\u0440\u043e\u0435\u043a\u0442\u0430.<\/p>\n

\"\u041f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435<\/p>\n
\u041f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u0444\u0430\u0439\u043b\u043e\u0432<\/figcaption><\/div>\n<\/figure>\n

8. \u041d\u0430\u043f\u043e\u043b\u043d\u044f\u0435\u043c \u0444\u0430\u0439\u043b\u044b.<\/p>\n

cpu_init.h<\/p>\n

\/*  * cpu_init.h  *  *  Created on: Jun 5, 2025  *       *\/  #ifndef INC_CPU_INIT_H_ #define INC_CPU_INIT_H_  \/\/================================================================================================ \/\/\u041f\u0440\u043e\u0442\u043e\u0442\u0438\u043f\u044b \u0444\u0443\u043d\u0446\u0438\u0439 void init_cpu(void);    \/\/\u0418\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \/\/================================================================================================  #endif \/* INC_CPU_INIT_H_ *\/<\/code><\/pre>\n
cpu_init.\u0441<\/p>\n
#include \"main.h\" #include \"cpu_init.h\"   \/\/========================================================================================================================== \/\/\u0418\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 void init_cpu(void) { \/\/\u043e\u0442\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u043e\u0440\u0442\u043e\u0432 \u043e\u0442\u043b\u0430\u0434\u043a\u0438 (\u0434\u043b\u044f \u0444\u0443\u043d\u0446\u0438\u043e\u043d\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u043f\u0435 \u043f\u0435\u0440\u0435\u0444\u0438\u0440\u0438\u0438) AFIO -> MAPR |= AFIO_MAPR_SWJ_CFG_1; RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;   } \/\/========================================================================================================================== <\/code><\/pre>\n
mod_bus_rtu_1.h<\/p>\n
\/*  * mod_bus_rtu_1.h  *  *  Created on: 1 \u0430\u043f\u0440. 2025 \u0433.  *       *\/  #ifndef INC_MOD_BUS_RTU_1_H_ #define INC_MOD_BUS_RTU_1_H_   #include \"main.h\"    \/\/========================================================================================================================== #define    _modbus_1_rx_485      HAL_GPIO_WritePin(rs485_re_de_GPIO_Port, rs485_re_de_Pin, GPIO_PIN_RESET);      \/\/\u043f\u0440\u0438\u0435\u043c 485 #define    _modbus_1_tx_485      HAL_GPIO_WritePin(rs485_re_de_GPIO_Port, rs485_re_de_Pin, GPIO_PIN_SET);      \/\/\u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 485   #define   modbus_1_rx_buff_lens     256 #define   modbus_1_tx_buff_lens     256   #define   modbus_1_func_03_min_adr  1 #define   modbus_1_func_03_max_adr  200  #define   modbus_1_func_06_min_adr  100 #define   modbus_1_func_06_max_adr  200  #define   modbus_1_func_10_min_adr  100 #define   modbus_1_func_10_max_adr  200   #define modbus_adr 1    #define   lens_tx_buff                 1000 #define   lens_rx_buff                 1000  \/\/========================================================================================================   \/\/======================================================================================================== \/\/\u041a\u043e\u0434\u044b \u043e\u0448\u0438\u0431\u043e\u043a modbus rtu #defineillegal_function0x01     \/\/\u041d\u0435\u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0439 \u043d\u043e\u043c\u0435\u0440 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 #defineillegal_data_address0x02     \/\/\u041d\u0435\u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 #define     illegar_data0x03     \/\/\u041d\u0435\u043a\u043e\u0440\u0435\u043a\u0442\u043d\u044b\u0435 \u0434\u0430\u043d\u043d\u044b\u0435 #definefaile_device0x04 \/\/\u041d\u0435\u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u043c\u0430\u044f \u043e\u0448\u0438\u0431\u043a\u0430 #defineacknowledge0x05     \/\/\u0414\u0430\u043d\u043d\u044b\u0435 \u043d\u0435 \u0433\u043e\u0442\u043e\u0432\u044b #define     busy_device0x06 \/\/\u0421\u0438\u0441\u0442\u0435\u043c\u0430 \u0437\u0430\u043d\u044f\u0442\u0430 #define     nak_func0x07     \/\/\u0423\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u043e \u043d\u0435 \u043c\u043e\u0436\u0435\u0442 \u0432\u044b\u043f\u043e\u043b\u043d\u0438\u0442\u044c \u0444\u0443\u043d\u043a\u0446\u0438\u044e \/\/========================================================================================================        \/\/========================================================================================================================== \/\/======================================================================================================== #pragma pack(push,1) typedef struct {  volatile uint32_t        timer;  volatile uint16_t        count_tx;     \/\/\u043f\u0435\u0440\u0435\u043c\u0435\u043d\u043d\u0430\u044f \u0441\u0447\u0435\u0442\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 volatile uint16_t        lens_tx;      \/\/\u0434\u043b\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 volatile uint8_t         status_tx;    \/\/\u0444\u043b\u0430\u0433 \u0441\u0442\u0430\u0442\u0443\u0441\u0430, 0- \u043d\u0435\u0442 \u043e\u0442\u043f\u0440\u0430\u0443\u0438, 1- \u0438\u0434\u0435\u0442 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 volatile uint16_t        count_rx;     \/\/\u0441\u0447\u0435\u0442\u0441\u0438\u043a \u0441\u0447\u0435\u0442\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043f\u0440\u0438\u0435\u043c\u0430 volatile uint8_t         status_read;  \/\/0- \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043d\u0435 \u043f\u0440\u0438\u0448\u043b\u0430, 1- \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043f\u0440\u0438\u0448\u043b\u0430   uint8_t                  buff_tx[lens_tx_buff];  \/\/\u0431\u0443\u0444\u0435\u0440 \u043f\u0440\u0438\u0435\u043c\u0430 uint8_t                  buff_rx[lens_rx_buff];  \/\/\u0431\u0443\u0444\u0435\u0440 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438   } glob_modbus_1; extern glob_modbus_1 modbus_1; #pragma pack(pop) \/\/========================================================================================================       \/\/======================================================================================================== \/\/Holding \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b. typedef struct {    volatile uint16_t holding[256];           \/\/\u0425\u043e\u043b\u0434\u0438\u043d\u0433 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0434\u043b\u044f \u0440\u0430\u0431\u043e\u0442\u044b    volatile uint8_t  holding_status[256];    \/\/Status_registr  } glob_modbus_1_reg; extern glob_modbus_1_reg modbus_1_reg; \/\/========================================================================================================       \/\/========================================================================================================================== uint16_t crc_16(uint8_t *data, uint16_t data_len);   \/\/\u0424\u0443\u043d\u0446\u0438\u044f \u0440\u0430\u0441\u0447\u0435\u0442\u0430 CRC16 A001h \u043c\u0435\u043d\u044f\u044c\u0431 \u043c\u0435\u0441\u0442\u0430\u043c\u0438 \u043f\u0440\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0435 \u043d\u0435 \u043d\u0430\u0434\u043e   void  timer_mod_bus_1_rtu_isr(void);                   \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0443 void  usart_mod_bus_1_rtu_isr(void);                \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443 \u0434\u0430\u043d\u043d\u044b\u0445   void  rx_mod_bus_1_rtu(void);                          \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 void  tx_mod_bus_1_rtu();            \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0431\u0443\u0444\u0435\u0440\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438  void modbus_1_send_error(unsigned char adr, unsigned char function, unsigned char code_error); \/\/\u0412\u044b\u0434\u0430\u0447\u0430 \u043e\u0448\u0438\u0431\u043a\u0438 \u043c\u0430\u0441\u0442\u0435\u0440\u0443: \u0430\u0434\u0440\u0435\u0441\u0441, \u0444\u0443\u043d\u043a\u0446\u0438\u044f, \u043a\u043e\u0434 \u043e\u0448\u0438\u0431\u043a\u0438  void modbus_1_func_03(void);   \/\/\u0424\u0443\u043d\u0446\u0438\u044f 03 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_06(void);   \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f 06 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_10(void);   \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f 10 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430  \/\/==========================================================================================================================  #endif \/* INC_MOD_BUS_RTU_1_H_ *\/<\/code><\/pre>\n
mod_bus_rtu_1.c<\/p>\n
 #include \"mod_bus_rtu_1.h\" #include \"stm32f1xx_hal.h\"     \/\/====================================================================================================================== glob_modbus_1 modbus_1={0,0,0,0,0};  glob_modbus_1_reg modbus_1_reg; \/\/======================================================================================================================   \/\/========================================================================================== \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0443 void  timer_mod_bus_1_rtu_isr(void) {   if (modbus_1.timer > 0) modbus_1.timer--; if (modbus_1.timer == 1)   { modbus_1.status_read = 1;   }   } \/\/==========================================================================================     \/\/========================================================================================== \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443 \u0434\u0430\u043d\u043d\u044b\u0445 void  usart_mod_bus_1_rtu_isr(void) {  unsigned int StatusReg, temp_status; uint8_t temp;  StatusReg = USART1->SR; USART3->SR = 0;     \/\/---------------------------------------------------------------------- \/\/ \u0435\u0441\u0442\u044c \u0434\u0430\u043d\u043d\u044b\u0435 if ((StatusReg & USART_SR_RXNE)&& ~modbus_1.lens_tx) { \/* read interrupt         *\/  USART1->SR &= ~USART_SR_RXNE; modbus_1.buff_rx[modbus_1.count_rx] = USART1->DR; modbus_1.count_rx ++; modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11  } \/\/----------------------------------------------------------------------   \/\/----------------------------------------------------------------------         \/\/\u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043e\u0448\u0438\u0431\u043e\u043a  \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_PE))         {             temp_status = USART1->SR;         temp  = USART1->DR;         modbus_1.count_rx ++;         modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------               \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_FE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------          \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_NE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------          \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_ORE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------         \/\/----------------------------------------------------------------------       \/\/---------------------------------------------------------------------- \/\/ \u043f\u0435\u0440\u0434\u0430\u0447\u0430 \u0437\u0430\u043a\u043e\u043d\u0447\u0435\u043d\u0430 if ((StatusReg & USART_SR_TC)) {  USART1->SR &= ~USART_SR_TC; USART1->CR1 &= ~USART_CR1_TCIE; \/\/\u0432\u044b\u043a\u043b\u044e\u0447\u0438\u0442\u044c \u043a\u043e\u043d\u0435\u0446 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 _modbus_1_rx_485; \/\/ \u0440\u0435\u0436\u0438\u043c \u043f\u0440\u0438\u0435\u043c\u0430         USART1->CR1 |= USART_CR1_RE;         modbus_1.count_tx = 0;         modbus_1.status_tx = 0;  USART1->CR1 |= USART_CR1_RXNEIE; \/\/\u0420\u0430\u0437\u0440\u0435\u0448\u0435\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u0430  } \/\/---------------------------------------------------------------------- \/\/ \u043f\u0435\u0440\u0435\u0434\u0430\u044e\u0449\u0438\u0439 \u0431\u0443\u0444\u0435\u0440 \u043f\u0443\u0441\u0442 if ((StatusReg & USART_SR_TXE) && modbus_1.lens_tx) {  \/\/\u0435\u0441\u0442\u044c \u0435\u0449\u0435 \u0434\u0430\u043d\u043d\u044b\u0435 USART1->DR = modbus_1.buff_tx[modbus_1.count_tx]; modbus_1.count_tx ++; if (modbus_1.count_tx >= modbus_1.lens_tx)  {\/\/\u0432\u0441\u0435 \u043f\u0435\u0440\u0435\u0434\u0430\u043d\u043e, \u0436\u0434\u0435\u043c \u043a\u043e\u043d\u0446\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 modbus_1.lens_tx = 0; USART1->CR1 &= ~USART_SR_TXE; \/* disable TX IRQ if nothing to send  *\/ USART1->CR1 |= USART_CR1_TCIE; \/\/\u0432\u043a\u043b\u044e\u0447\u0438\u0442\u044c \u043a\u043e\u043d\u0435\u0446 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438   } }\/\/USART_SR_TXE    } \/\/==========================================================================================     \/\/========================================================================================== \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0431\u0443\u0444\u0435\u0440\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 void  tx_mod_bus_1_rtu() { uint8_t temp;  modbus_1.count_tx = 0;  if (!(USART1->SR & USART_SR_RXNE)) { \/* \u0435\u0441\u043b\u0438 USART_SR_IDLE == 1 \u043b\u0438\u043d\u0438\u044f \u0441\u0432\u043e\u0431\u043e\u0434\u043d\u0430       *\/   USART1->CR1 &= ~USART_CR1_RE;  _modbus_1_tx_485;  USART1->CR1 |= USART_SR_TXE; \/* enable TX interrupt     *\/  } else { temp = USART1->DR; modbus_1.lens_tx = 0; }    } \/\/==========================================================================================     \/\/============================================================================== \/\/\u0412\u044b\u0434\u0430\u0447\u0430 \u043e\u0448\u0438\u0431\u043a\u0438 \u043c\u0430\u0441\u0442\u0435\u0440\u0443: \u0430\u0434\u0440\u0435\u0441\u0441, \u0444\u0443\u043d\u043a\u0446\u0438\u044f, \u043a\u043e\u0434 \u043e\u0448\u0438\u0431\u043a\u0438 void modbus_1_send_error(unsigned char adr, unsigned char function, unsigned char code_error) {     volatile unsigned int crc;          modbus_1.buff_tx[0]=adr;           \/\/\u0410\u0434\u0440\u0435\u0441\u0441         modbus_1.buff_tx[1]=function|0x80;    \/\/\u0412\u043e\u0437\u0432\u0430\u0440\u0442 \u043a\u043e\u0434\u0430 \u0444\u0443\u043d\u043a\u0446\u0438\u0438         modbus_1.buff_tx[2]=code_error;    \/\/\u041a\u043e\u0434 \u043e\u0448\u0438\u0431\u043a\u0438 crc=crc_16(modbus_1.buff_tx,3);  \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC modbus_1.buff_tx[3]=(crc>>8);  \/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442 modbus_1.buff_tx[4]=crc;              \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442   modbus_1.lens_tx = 5; modbus_1.count_tx = 0;   tx_mod_bus_1_rtu(modbus_1.lens_tx);  } \/\/==============================================================================   \/\/========================================================================================== \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 void  rx_mod_bus_1_rtu(void) { if (modbus_1.status_read == 1) {      volatile uint16_t crc16;  volatile uint8_t  func_status, func_read;     \/\/\u0415\u0441\u043b\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043c\u0430\u043b\u0435\u043d\u044c\u043a\u043e\u0439 \u0434\u043b\u0438\u043d\u044b  if (modbus_1.count_rx <5) {goto end;}   \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0441\u0435\u0442\u0435\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430  if (modbus_adr != modbus_1.buff_rx[0]) {goto end;}    \/\/\u0420\u0430\u0441\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b  crc16=crc_16(modbus_1.buff_rx,(modbus_1.count_rx-2));   \/\/\u0421\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b if (crc16!=((modbus_1.buff_rx[modbus_1.count_rx-2]<<8)|(modbus_1.buff_rx[modbus_1.count_rx-1]))) {goto end; }    \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0444\u0443\u043d\u0446\u0438\u0438 func_read=modbus_1.buff_rx[1];          \/\/\/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0441\u0442\u0438 \u043a\u043e\u0434\u0430 \u0444\u0443\u043d\u043a\u0446\u0438\u0438      if ((func_read==0x03)||(func_read==0x06)||(func_read==0x10)||(func_read==0x04)) { func_status=1;  }  else { func_status=0;  }        \/\/\u0424\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043e\u0442\u0432\u0435\u0442\u0430 \u043f\u0440\u0438 \u043e\u0448\u0438\u0431\u043a\u0438 \u0444\u0443\u043d\u0446\u0438\u0438      if (func_status==0)         {      modbus_1_send_error(modbus_adr, func_read, illegal_function);           goto end;         }          if (func_read == 0x03) {  modbus_1_func_03(); }       if (func_read == 0x06) {  modbus_1_func_06(); }       if (func_read == 0x10) {  modbus_1_func_10(); }       end:    modbus_1.status_read=0;    modbus_1.count_rx=0;   }  } \/\/==========================================================================================    \/\/========================================================================================== \/\/\u0424\u0443\u043d\u0446\u0438\u044f 03 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_03(void) {  volatile uint8_t  bus_adr; volatile uint16_t start_reg_adr;           \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441  \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f volatile uint16_t number_reg;              \/\/\u0427\u0438\u0441\u043b\u043e \u043f\u0440\u043e\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 volatile uint16_t temp;     volatile unsigned char count=3;            \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 \u043f\u043e\u0441\u043b\u044b\u043a\u0435 volatile unsigned char len_mess=5;         \/\/\u0414\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 volatile unsigned int crc;   bus_adr = modbus_adr; \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430 start_reg_adr=(modbus_1.buff_rx[2]<<8)|modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430 number_reg=(modbus_1.buff_rx[4]<<8)|modbus_1.buff_rx[5];     \/\/\u0427\u0438\u0441\u043b\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432      \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434 \u0437\u0430 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0433\u043e \u0447\u0442\u0435\u043d\u0438\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432     if ((start_reg_adr < modbus_1_func_03_min_adr)||(start_reg_adr > (modbus_1_func_03_max_adr + number_reg)))       {      modbus_1_send_error(bus_adr, 0x03, illegal_data_address);     goto end;       }      \/\/\u0433\u043e\u0442\u043e\u0432\u0438\u043c \u043f\u043e\u0441\u044b\u043b\u043a\u0443 \u043a \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438      modbus_1.buff_tx[0] = bus_adr;              \/\/\u0410\u0434\u0440\u0435\u0441\u0441      modbus_1.buff_tx[1] = 0x03;           \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f      modbus_1.buff_tx[2] = (number_reg*2);    \/\/\u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0431\u0430\u0439\u0442 \u0432 \u043f\u043e\u0441\u044b\u043b\u043a\u0435 \u043c\u043b\u0430\u0434\u0448\u0438\u0439       \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432      temp = start_reg_adr;        while (number_reg--)      {      modbus_1.buff_tx[count] = (modbus_1_reg.holding[temp]>>8);    count++; len_mess++;      modbus_1.buff_tx[count] = ((modbus_1_reg.holding[temp]));    count++; len_mess++;      temp++;       }          \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC        crc = crc_16(modbus_1.buff_tx , count);       modbus_1.buff_tx[count] = (crc>>8); count++;\/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442       modbus_1.buff_tx[count] = crc;                       \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442         \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445       modbus_1.lens_tx = len_mess; modbus_1.count_tx = 0;       tx_mod_bus_1_rtu();     end: return;   } \/\/==========================================================================================    \/\/========================================================================================== void modbus_1_func_06(void) {  volatile uint8_t  bus_adr; volatile uint16_t start_reg_adr;           \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441  \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f  volatile uint16_t  data;   \/\/\u0417\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u043c\u0430\u044f \u0434\u0430\u0442\u0430  volatile unsigned char count=6;            \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 \u043f\u043e\u0441\u043b\u044b\u043a\u0435 volatile unsigned char len_mess=8;         \/\/\u0414\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 volatile unsigned int crc;   bus_adr = modbus_adr; \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430  start_reg_adr = (modbus_1.buff_rx[2]<<8) | modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430 data          = (modbus_1.buff_rx[4]<<8) | modbus_1.buff_rx[5];   \/\/\u0417\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u043c\u0430\u044f \u0434\u0430\u0442\u0430  \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434 \u0437\u0430 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0433\u043e \u0447\u0442\u0435\u043d\u0438\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 if ((start_reg_adr < modbus_1_func_06_min_adr)||(start_reg_adr > modbus_1_func_06_max_adr))  { modbus_1_send_error(bus_adr, 0x03, illegal_data_address);     goto end;  }       \/\/ modbus_1_reg.holding[start_reg_adr] = data; modbus_1_reg.holding_status[start_reg_adr] = 1;   \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043a\u043e\u043c\u0430\u043d\u0434\u044b  modbus_1.buff_tx[0] = bus_adr;               \/\/\u0410\u0434\u0440\u0435\u0441\u0441  modbus_1.buff_tx[1] = 0x06;          \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f  modbus_1.buff_tx[2] = (start_reg_adr)>>8;   \/\/\u0430\u0434\u0440\u0435\u0441\u0441  modbus_1.buff_tx[3] = (start_reg_adr);       \/\/\u0430\u0436\u0440\u0435\u0441\u0441  modbus_1.buff_tx[4] = (data)>>8;         \/\/\u0434\u0430\u043d\u043d\u044b\u0435  modbus_1.buff_tx[5] = (data);                \/\/\u0414\u0430\u043d\u043d\u044b\u0435  \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC crc = crc_16(modbus_1.buff_tx,count); modbus_1.buff_tx[count]=(crc>>8); \/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442 modbus_1.buff_tx[++count]=crc;            \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442        \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445 \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445 modbus_1.lens_tx = len_mess; modbus_1.count_tx = 0; tx_mod_bus_1_rtu(modbus_1.lens_tx);  end: return; } \/\/==========================================================================================   \/\/========================================================================================== void modbus_1_func_10(void) {        volatile uint8_t  bus_adr;    volatile uint16_t start_reg_adr;             \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441  \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f    volatile uint16_t number_reg;                \/\/\u0427\u0438\u0441\u043b\u043e \u043f\u0440\u043e\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432          volatile unsigned char count = 6;            \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 \u043f\u043e\u0441\u043b\u044b\u043a\u0435    volatile unsigned char len_mess = 8;         \/\/\u0414\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438    volatile unsigned int crc;    volatile uint16_t adr_data_buff;     volatile uint16_t count_reg = 0;             \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0437\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432     adr_data_buff = 7;                           \/\/ C \u0432\u043e\u0441\u044c\u043c\u043e\u0433\u043e \u0431\u0430\u0439\u0442\u0430 \u043d\u0430\u0447\u0438\u043d\u0430\u044e\u0442\u0441\u044f \u0434\u0430\u043d\u043d\u044b\u0435  \/\/   bus_adr = eeprom.modbus_adr;     \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430       bus_adr = modbus_adr; \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430    start_reg_adr=(modbus_1.buff_rx[2]<<8)|modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430    number_reg=(modbus_1.buff_rx[4]<<8)|modbus_1.buff_rx[5];     \/\/\u0427\u0438\u0441\u043b\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432     \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434 \u0437\u0430 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0433\u043e \u0447\u0442\u0435\u043d\u0438\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432    if ((start_reg_adr < modbus_1_func_10_min_adr)||(start_reg_adr > (modbus_1_func_10_max_adr + number_reg)))     {        modbus_1_send_error(bus_adr, 0x03, illegal_data_address);        goto end;     }      while (number_reg--)     {    modbus_1_reg.holding[start_reg_adr]=(modbus_1.buff_rx[adr_data_buff]<<8); adr_data_buff++;    modbus_1_reg.holding[start_reg_adr]+=modbus_1.buff_rx[adr_data_buff];     adr_data_buff++;    modbus_1_reg.holding_status[start_reg_adr] = 1;               start_reg_adr++;      count_reg++;     }      \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441    start_reg_adr=(modbus_1.buff_rx[2]<<8)|modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430     \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043a\u043e\u043c\u0430\u043d\u0434\u044b    modbus_1.buff_tx[0] = bus_adr;                   \/\/\u0410\u0434\u0440\u0435\u0441\u0441    modbus_1.buff_tx[1] = 0x10;                \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f    modbus_1.buff_tx[2] = (start_reg_adr)>>8;     \/\/\u0430\u0434\u0440\u0435\u0441\u0441    modbus_1.buff_tx[3] = (start_reg_adr);         \/\/\u0430\u0436\u0440\u0435\u0441\u0441    modbus_1.buff_tx[4] = (count_reg)>>8;         \/\/\u0427\u0438\u0441\u043b\u043e \u0437\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432    modbus_1.buff_tx[5] = (count_reg);               \/\/\u0427\u0438\u0441\u043b\u043e \u0437\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432    \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC   crc = crc_16(modbus_1.buff_tx,count);   modbus_1.buff_tx[count] = (crc>>8);     \/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442   modbus_1.buff_tx[++count] = crc;                \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442           \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445   \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445   modbus_1.lens_tx = len_mess; modbus_1.count_tx = 0;   tx_mod_bus_1_rtu(modbus_1.lens_tx);   end: return;  } \/\/==========================================================================================        \/\/========================================================================================== \/\/\u0424\u0443\u043d\u0446\u0438\u044f \u0440\u0430\u0441\u0447\u0435\u0442\u0430 CRC16 A001h \u043c\u0435\u043d\u044f\u044c\u0431 \u043c\u0435\u0441\u0442\u0430\u043c\u0438 \u043f\u0440\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0435 \u043d\u0435 \u043d\u0430\u0434\u043e uint16_t crc_16(uint8_t *data, uint16_t data_len) {    unsigned char uchCRCHi = 0xFF ;\/* \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u0441\u0442\u0430\u0440\u0448\u0435\u0433\u043e \u0431\u0430\u0439\u0442\u0430 CRC *\/    unsigned char uchCRCLo = 0xFF ;\/* \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043c\u043b\u0430\u0434\u0448\u0435\u0433\u043e \u0431\u0430\u0439\u0442\u0430 CRC *\/    unsigned char index;             \/\/\u0418\u043d\u0434\u0435\u043a\u0441 \u0434\u043b\u044f \u043e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u0438 \u0446\u0438\u043a\u043b\u0430     const unsigned char auchCRCHi[] = { 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40, 0x01, 0xC0, 0x80, 0x41, 0x01, 0xC0, 0x80, 0x41, 0x00, 0xC1, 0x81, 0x40 } ;   const char auchCRCLo[] = { 0x00, 0xC0, 0xC1, 0x01, 0xC3, 0x03, 0x02, 0xC2, 0xC6, 0x06, 0x07, 0xC7, 0x05, 0xC5, 0xC4, 0x04, 0xCC, 0x0C, 0x0D, 0xCD, 0x0F, 0xCF, 0xCE, 0x0E, 0x0A, 0xCA, 0xCB, 0x0B, 0xC9, 0x09, 0x08, 0xC8, 0xD8, 0x18, 0x19, 0xD9, 0x1B, 0xDB, 0xDA, 0x1A, 0x1E, 0xDE, 0xDF, 0x1F, 0xDD, 0x1D, 0x1C, 0xDC, 0x14, 0xD4, 0xD5, 0x15, 0xD7, 0x17, 0x16, 0xD6, 0xD2, 0x12, 0x13, 0xD3, 0x11, 0xD1, 0xD0, 0x10, 0xF0, 0x30, 0x31, 0xF1, 0x33, 0xF3, 0xF2, 0x32, 0x36, 0xF6, 0xF7, 0x37, 0xF5, 0x35, 0x34, 0xF4, 0x3C, 0xFC, 0xFD, 0x3D, 0xFF, 0x3F, 0x3E, 0xFE, 0xFA, 0x3A, 0x3B, 0xFB, 0x39, 0xF9, 0xF8, 0x38, 0x28, 0xE8, 0xE9, 0x29, 0xEB, 0x2B, 0x2A, 0xEA, 0xEE, 0x2E, 0x2F, 0xEF, 0x2D, 0xED, 0xEC, 0x2C, 0xE4, 0x24, 0x25, 0xE5, 0x27, 0xE7, 0xE6, 0x26, 0x22, 0xE2, 0xE3, 0x23, 0xE1, 0x21, 0x20, 0xE0, 0xA0, 0x60, 0x61, 0xA1, 0x63, 0xA3, 0xA2, 0x62, 0x66, 0xA6, 0xA7, 0x67, 0xA5, 0x65, 0x64, 0xA4, 0x6C, 0xAC, 0xAD, 0x6D, 0xAF, 0x6F, 0x6E, 0xAE, 0xAA, 0x6A, 0x6B, 0xAB, 0x69, 0xA9, 0xA8, 0x68, 0x78, 0xB8, 0xB9, 0x79, 0xBB, 0x7B, 0x7A, 0xBA, 0xBE, 0x7E, 0x7F, 0xBF, 0x7D, 0xBD, 0xBC, 0x7C, 0xB4, 0x74, 0x75, 0xB5, 0x77, 0xB7, 0xB6, 0x76, 0x72, 0xB2, 0xB3, 0x73, 0xB1, 0x71, 0x70, 0xB0, 0x50, 0x90, 0x91, 0x51, 0x93, 0x53, 0x52, 0x92, 0x96, 0x56, 0x57, 0x97, 0x55, 0x95, 0x94, 0x54, 0x9C, 0x5C, 0x5D, 0x9D, 0x5F, 0x9F, 0x9E, 0x5E, 0x5A, 0x9A, 0x9B, 0x5B, 0x99, 0x59, 0x58, 0x98, 0x88, 0x48, 0x49, 0x89, 0x4B, 0x8B, 0x8A, 0x4A, 0x4E, 0x8E, 0x8F, 0x4F, 0x8D, 0x4D, 0x4C, 0x8C, 0x44, 0x84, 0x85, 0x45, 0x87, 0x47, 0x46, 0x86, 0x82, 0x42, 0x43, 0x83, 0x41, 0x81, 0x80, 0x40 } ;        \/\/\u041e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u044f \u0446\u0438\u043a\u043b\u0430 \u0434\u043b\u044f \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u044f CRC      while (data_len--)\/* \u043f\u0440\u043e\u0434\u0432\u0438\u0436\u0435\u043d\u0438\u0435 \u043f\u043e \u0431\u0443\u0444\u0435\u0440\u0443 *\/       {     index   = uchCRCHi ^ *data++ ;\/* \u0432\u044b\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0435 CRC   *\/     uchCRCHi = uchCRCLo ^ auchCRCHi[index] ;     uchCRCLo = auchCRCLo[index] ;       }       return ((uchCRCHi << 8) | uchCRCLo); } \/\/========================================================================================== <\/code><\/pre>\n
\u041f\u0440\u043e\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u043c \u0444\u0443\u043d\u043a\u0446\u0438\u0438 \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0435<\/p>\n
\u0412 main.c<\/p>\n
\"\u0424\u0443\u043d\u043a\u0446\u0438\u044f<\/p>\n
\u0424\u0443\u043d\u043a\u0446\u0438\u044f \u0432 \u0444\u0430\u0439\u043b\u0435 main.c<\/figcaption><\/div>\n<\/figure>\n
    \n
  1. \n
    \u0414\u0435\u043b\u0430\u0435\u043c \u0437\u0430\u0434\u0435\u0440\u0436\u043a\u0443 \u043f\u043e \u0432\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u044e \u043f\u043e \u041c\u041a.<\/p>\n<\/li>\n
  2. \n
    init_cpu();  — \u0444\u0443\u043d\u043a\u0446\u0438\u044f \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438. \u0412 \u043d\u0435\u0439 \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u043d\u043e \u043e\u0442\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u044f \u043e\u0442\u043b\u0430\u0434\u0447\u0438\u043a\u0430, \u0434\u043b\u044f \u0444\u0443\u043d\u043a\u0446\u0438\u043e\u043d\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0438 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0438 (\u041f\u0440\u043e\u0431\u043b\u0435\u043c\u0430 \u0441 GPIO PB3,PB4 \u0438 PA15 \u043d\u0430 STM32 \u0432 STM32CubeIDE).<\/p>\n
    \/\/\u043e\u0442\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u043e\u0440\u0442\u043e\u0432 \u043e\u0442\u043b\u0430\u0434\u043a\u0438 (\u0434\u043b\u044f \u0444\u0443\u043d\u0446\u0438\u043e\u043d\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u043f\u0435 \u043f\u0435\u0440\u0435\u0444\u0438\u0440\u0438\u0438)
     AFIO -> MAPR |= AFIO_MAPR_SWJ_CFG_1;
     RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;<\/p>\n<\/li>\n
  3. \n
    rx_mod_bus_1_rtu(); — \u0444\u0443\u043d\u043a\u0446\u0438\u044f \u0440\u0430\u0437\u0431\u043e\u0440\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430.<\/p>\n<\/li>\n<\/ol>\n
    Usart.c<\/p>\n
    \u0412\u0441\u0442\u0430\u0432\u043b\u044f\u0435\u043c \u0434\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u0434 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 USART1.<\/p>\n
      \/* USER CODE BEGIN USART1_Init 2 *\/      USART1->CR1  |=   USART_CR1_UE;                      \/\/\u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043c\u043e\u0434\u0443\u043b\u044f USART1      USART1->CR1  |=   USART_CR1_TE;                      \/\/\u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u0435\u0440\u0435\u0434\u0430\u0442\u0447\u0438\u043a\u0430      USART1->CR1  |=   USART_CR1_RE;                      \/\/\u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u043d\u0438\u043a\u0430       \/\/\u0420\u0430\u0437\u0440\u0435\u0448\u0438\u0442\u044c \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f      NVIC_EnableIRQ (USART1_IRQn);                        \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f USART1       \/\/  USART1->CR1  |= USART_CR1_TCIE;                    \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u043f\u043e \u0437\u0430\u0432\u0435\u0440\u0448\u0435\u043d\u0438\u0438 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438      USART1->CR1  |= USART_CR1_RXNEIE;                    \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u043f\u043e \u0437\u0430\u0432\u0435\u0440\u0448\u0435\u043d\u0438\u0438 \u043f\u0440\u0438\u0435\u043c\u0430      USART1->CR3  |= USART_CR3_EIE;                       \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0432\u043e\u0437\u043d\u0438\u043a\u043d\u043e\u0432\u0435\u043d\u0438\u0438 \u043e\u0448\u0438\u0431\u043a\u0438    \/* USER CODE END USART1_Init 2 *\/<\/code><\/pre>\n
    \"\u0414\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0430\u044f<\/p>\n
    \u0414\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0430\u044f \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 Usart1<\/figcaption><\/div>\n<\/figure>\n
    tim.c<\/p>\n
    \u0412\u0441\u0442\u0430\u0432\u043b\u044f\u0435\u043c \u0434\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u043a\u043e\u0434 \u0438\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 TIM6. <\/p>\n
     \/* USER CODE BEGIN TIM6_Init 2 *\/   HAL_TIM_Base_Start_IT (&htim6);   \/* USER CODE END TIM6_Init 2 *\/<\/code><\/pre>\n
    \"\u0414\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0430\u044f<\/p>\n
    \u0414\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0430\u044f \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 TIM6<\/figcaption><\/div>\n<\/figure>\n
    \u0424\u0430\u0439\u043b stm32f1xx_it.c<\/p>\n
    \u0414\u043e\u0431\u0430\u0432\u043b\u044f\u0435\u043c \u0444\u0443\u043d\u043a\u0446\u0438\u044e \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 USART1:<\/p>\n
    void USART1_IRQHandler(void) {   \/* USER CODE BEGIN USART1_IRQn 0 *\/ usart_mod_bus_1_rtu_isr();   \/* USER CODE END USART1_IRQn 0 *\/   HAL_UART_IRQHandler(&huart1);   \/* USER CODE BEGIN USART1_IRQn 1 *\/    \/* USER CODE END USART1_IRQn 1 *\/<\/code><\/pre>\n
    \u0414\u043e\u0431\u0430\u0432\u043b\u044f\u0435\u043c \u0444\u0443\u043d\u043a\u0446\u0438\u044e \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 TIM6:<\/p>\n
    \/**   * @brief This function handles TIM6 global interrupt.   *\/ void TIM6_IRQHandler(void) {   \/* USER CODE BEGIN TIM6_IRQn 0 *\/ timer_mod_bus_1_rtu_isr();   \/* USER CODE END TIM6_IRQn 0 *\/   HAL_TIM_IRQHandler(&htim6);   \/* USER CODE BEGIN TIM6_IRQn 1 *\/    \/* USER CODE END TIM6_IRQn 1 *\/ }<\/code><\/pre>\n
    \"\u0412\u044b\u0437\u043e\u0432<\/p>\n
    \u0412\u044b\u0437\u043e\u0432 \u0444\u0443\u043d\u043a\u0446\u0438\u0439 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439<\/figcaption><\/div>\n<\/figure>\n
    \u041d\u0430 \u044d\u0442\u043e\u043c \u0432\u0441\u0435, \u043c\u043e\u0436\u043d\u043e \u043a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u0438 \u0437\u0430\u0448\u0438\u0432\u0430\u0442\u044c \u0432 \u041c\u041a. \u0414\u043b\u044f \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0438 \u0438 \u043e\u0442\u043b\u0430\u0434\u043a\u0438 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430 \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0431\u0435\u0441\u043f\u043b\u0430\u0442\u043d\u0443\u044e \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0443 Owen OPC Server.<\/p>\n
    \"<\/p>\n
     \u041f\u0440\u0438\u043c\u0435\u0440.  Owen OPC Server.<\/figcaption><\/div>\n<\/figure>\n
    \u0422\u0435\u043f\u0435\u0440\u044c \u0440\u0430\u0441\u0441\u043c\u043e\u0442\u0440\u0438\u043c \u043a\u0430\u043a \u0432\u0441\u0435 \u044d\u0442\u043e \u0440\u0430\u0431\u043e\u0442\u0430\u0435\u0442.<\/p>\n
    \u0421\u0444\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d \u043f\u0440\u0438\u0435\u043c\u043d\u044b\u0439 \u0438 \u043f\u0435\u0440\u0435\u0434\u0430\u044e\u0449\u0438\u0439 \u0431\u0443\u0444\u0435\u0440, \u0441\u0447\u0435\u0442\u0447\u0438\u043a \u043a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u043f\u0440\u0438\u043d\u044f\u0442\u044b\u0445 \u0438 \u0441\u0444\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043a \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445, \u0442\u0430\u0439\u043c\u0435\u0440 \u043d\u0430 5 \u043c\u0441 (\u0434\u043b\u044f \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u0438 9600 \u0432\u0440\u0435\u043c\u044f \u0437\u0430\u0432\u0435\u0440\u0448\u0435\u043d\u0438\u044f \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043f\u0440\u0438\u0431\u043b\u0438\u0437\u0438\u0442\u0435\u043b\u044c\u043d\u043e 3.5 \u043c\u0441):<\/p>\n
    \/\/======================================================================================================== #pragma pack(push,1) typedef struct {  volatile uint32_t        timer;  volatile uint16_t        count_tx;     \/\/\u043f\u0435\u0440\u0435\u043c\u0435\u043d\u043d\u0430\u044f \u0441\u0447\u0435\u0442\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 volatile uint16_t        lens_tx;      \/\/\u0434\u043b\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 volatile uint8_t         status_tx;    \/\/\u0444\u043b\u0430\u0433 \u0441\u0442\u0430\u0442\u0443\u0441\u0430, 0- \u043d\u0435\u0442 , 1- \u0438\u0434\u0435\u0442 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 volatile uint16_t        count_rx;     \/\/\u0441\u0447\u0435\u0442\u0441\u0438\u043a \u0441\u0447\u0435\u0442\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043f\u0440\u0438\u0435\u043c\u0430 volatile uint8_t         status_read;  \/\/0- \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043d\u0435 \u043f\u0440\u0438\u0448\u043b\u0430, 1- \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043f\u0440\u0438\u0448\u043b\u0430   uint8_t                  buff_tx[lens_tx_buff];  \/\/\u0431\u0443\u0444\u0435\u0440 \u043f\u0440\u0438\u0435\u043c\u0430 uint8_t                  buff_rx[lens_rx_buff];  \/\/\u0431\u0443\u0444\u0435\u0440 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438   } glob_modbus_1; extern glob_modbus_1 modbus_1; #pragma pack(pop) \/\/========================================================================================================<\/code><\/pre>\n
    \u0422\u0430\u043a\u0436\u0435 \u0441\u0444\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d\u044b holding \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b. \u0414\u043b\u044f \u0443\u0434\u043e\u0431\u0441\u0442\u0432\u0430 status \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b, \u0437\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0432 \u043d\u0438\u0445 1 \u043f\u0440\u0438 \u0437\u0430\u043f\u0438\u0441\u0438 \u0432 \u0445\u043e\u043b\u0434\u0438\u043d\u0433 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b — \u0434\u0430\u043b\u0435\u0435 \u043f\u043e\u0442\u043e\u043c \u0443\u0434\u043e\u0431\u043d\u043e \u0440\u0430\u0437\u0431\u0438\u0440\u0430\u0442\u044c \u043f\u0440\u0438 \u0437\u0430\u043f\u0438\u0441\u0438.<\/p>\n
    \/\/======================================================================================================== \/\/Holding \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b. typedef struct {    volatile uint16_t holding[256];           \/\/\u0425\u043e\u043b\u0434\u0438\u043d\u0433 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0434\u043b\u044f \u0440\u0430\u0431\u043e\u0442\u044b    volatile uint8_t  holding_status[256];    \/\/Status_registr  } glob_modbus_1_reg; extern glob_modbus_1_reg modbus_1_reg; \/\/========================================================================================================<\/code><\/pre>\n
    \u0423\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u0435 \u043f\u043e\u0440\u0442\u043e\u043c re_de<\/p>\n
    #define    _modbus_1_rx_485      HAL_GPIO_WritePin(rs485_re_de_GPIO_Port, rs485_re_de_Pin, GPIO_PIN_RESET);      \/\/\u043f\u0440\u0438\u0435\u043c 485 #define    _modbus_1_tx_485      HAL_GPIO_WritePin(rs485_re_de_GPIO_Port, rs485_re_de_Pin, GPIO_PIN_SET);      \/\/\u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 485<\/code><\/pre>\n
    \u0414\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0435  \u0430\u0434\u0440\u0435\u0441\u0430 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0434\u043b\u044f \u0444\u0443\u043d\u043a\u0446\u0438\u0439 0\u044503, 0\u044506, 0\u044510. \u0421\u0435\u0442\u0435\u0432\u043e\u0439 \u0430\u0434\u0440\u0435\u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432.<\/p>\n
    #define   modbus_1_func_03_min_adr  1 #define   modbus_1_func_03_max_adr  200  #define   modbus_1_func_06_min_adr  100 #define   modbus_1_func_06_max_adr  200  #define   modbus_1_func_10_min_adr  100 #define   modbus_1_func_10_max_adr  200   #define modbus_adr 1<\/code><\/pre>\n
    \u0417\u0430\u0434\u0435\u043a\u043b\u0430\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u044b \u043a\u043e\u0434\u044b \u043e\u0448\u0438\u0431\u043e\u043a<\/p>\n
    \/\/======================================================================================================== \/\/\u041a\u043e\u0434\u044b \u043e\u0448\u0438\u0431\u043e\u043a modbus rtu #defineillegal_function0x01     \/\/\u041d\u0435\u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0439 \u043d\u043e\u043c\u0435\u0440 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 #defineillegal_data_address0x02     \/\/\u041d\u0435\u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 #define     illegar_data0x03     \/\/\u041d\u0435\u043a\u043e\u0440\u0435\u043a\u0442\u043d\u044b\u0435 \u0434\u0430\u043d\u043d\u044b\u0435 #definefaile_device0x04 \/\/\u041d\u0435\u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u043c\u0430\u044f \u043e\u0448\u0438\u0431\u043a\u0430 #defineacknowledge0x05     \/\/\u0414\u0430\u043d\u043d\u044b\u0435 \u043d\u0435 \u0433\u043e\u0442\u043e\u0432\u044b #define     busy_device0x06 \/\/\u0421\u0438\u0441\u0442\u0435\u043c\u0430 \u0437\u0430\u043d\u044f\u0442\u0430 #define     nak_func0x07     \/\/\u0423\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u043e \u043d\u0435 \u043c\u043e\u0436\u0435\u0442 \u0432\u044b\u043f\u043e\u043b\u043d\u0438\u0442\u044c \u0444\u0443\u043d\u043a\u0446\u0438\u044e \/\/========================================================================================================<\/code><\/pre>\n
    \u0424\u0443\u043d\u043a\u0446\u0438\u0438 <\/p>\n
     void  timer_mod_bus_1_rtu_isr(void);                   \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0443 void  usart_mod_bus_1_rtu_isr(void);                \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443 \u0434\u0430\u043d\u043d\u044b\u0445   void  rx_mod_bus_1_rtu(void);                          \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 void  tx_mod_bus_1_rtu();            \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0431\u0443\u0444\u0435\u0440\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438  void modbus_1_send_error(unsigned char adr, unsigned char function, unsigned char code_error); \/\/\u0412\u044b\u0434\u0430\u0447\u0430 \u043e\u0448\u0438\u0431\u043a\u0438 \u043c\u0430\u0441\u0442\u0435\u0440\u0443: \u0430\u0434\u0440\u0435\u0441\u0441, \u0444\u0443\u043d\u043a\u0446\u0438\u044f, \u043a\u043e\u0434 \u043e\u0448\u0438\u0431\u043a\u0438  void modbus_1_func_03(void);   \/\/\u0424\u0443\u043d\u0446\u0438\u044f 03 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_06(void);   \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f 06 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_10(void);   \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f 10 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430<\/code><\/pre>\n
    \u0418 \u0442\u0430\u043a, \u043f\u0440\u0438 \u043f\u0440\u0438\u0435\u043c\u0435 \u0431\u0430\u0439\u0442\u0430, \u0432\u043e\u0437\u043d\u0438\u043a\u0430\u0435\u0442 \u0438 \u043e\u0431\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u0438 \u043e\u0431\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u043a\u043e\u0434 \u0444\u0443\u043d\u043a\u0446\u0438\u0438, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u043a\u043b\u0430\u0434\u0435\u0442 \u0431\u0430\u0439\u0442 \u0432 \u0431\u0443\u0444\u0435\u0440, \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u0442 \u0432\u0440\u0435\u043c\u044f \u0442\u0430\u0439\u043c\u0435\u0440\u0430 \u043e\u0436\u0438\u0434\u0430\u043d\u0438\u044f \u043a\u043e\u043d\u0446\u0430 \u043f\u0430\u043a\u0435\u0442\u0430. \u041f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u044c\u0441\u044f \u043f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043a\u043e\u0434\u043e\u0432 \u043e\u0448\u0438\u0431\u043e\u043a \u0438 \u0441\u0431\u0440\u043e\u0441 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0432\u0443\u044e\u0449\u0438\u0445 \u0444\u043b\u0430\u0433\u043e\u0432. <\/p>\n
    \/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443 \u0434\u0430\u043d\u043d\u044b\u0445 void  usart_mod_bus_1_rtu_isr(void) {  unsigned int StatusReg, temp_status; uint8_t temp;  StatusReg = USART1->SR; USART3->SR = 0;     \/\/---------------------------------------------------------------------- \/\/ \u0435\u0441\u0442\u044c \u0434\u0430\u043d\u043d\u044b\u0435 if ((StatusReg & USART_SR_RXNE)&& ~modbus_1.lens_tx) { \/* read interrupt         *\/  USART1->SR &= ~USART_SR_RXNE; modbus_1.buff_rx[modbus_1.count_rx] = USART1->DR; modbus_1.count_rx ++; modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11  } \/\/----------------------------------------------------------------------   \/\/----------------------------------------------------------------------         \/\/\u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043e\u0448\u0438\u0431\u043e\u043a  \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_PE))         {             temp_status = USART1->SR;         temp  = USART1->DR;         modbus_1.count_rx ++;         modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------               \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_FE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------          \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_NE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------          \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_ORE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------         \/\/----------------------------------------------------------------------<\/code><\/pre>\n
    \u041f\u0440\u0438 \u044d\u0442\u043e\u043c \u0440\u0430\u0431\u043e\u0442\u0430\u0435\u0442 \u0442\u0430\u0439\u043c\u0435\u0440, \u043a\u043e\u0442\u043e\u0440\u044b\u0439 \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u043f\u0440\u0438 \u043f\u0440\u0438\u0435\u043c\u0435 \u0431\u0430\u0439\u0442\u0430. \u0422\u0430\u0439\u043c\u0435\u0440 \u0434\u0435\u043a\u0440\u0435\u043c\u0435\u043d\u0442\u0438\u0440\u0443\u044e\u0449\u0438\u0439. \u041f\u0440\u0438 \u0434\u043e\u0441\u0442\u0438\u0436\u0435\u043d\u0438\u0438 \u0441\u0447\u0435\u0442\u0447\u0438\u043a\u0430 1 \u0438\u043b\u0438 5 \u043c\u0441 \u043f\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u0438, \u0432\u044b\u0434\u0430\u0435\u0442\u0441\u044f modbus_1.status_read = 1; \u041e\u0437\u043d\u0430\u0447\u0430\u0435\u0442 \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u0430.<\/p>\n
    \/\/========================================================================================== \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0443 void  timer_mod_bus_1_rtu_isr(void) {   if (modbus_1.timer > 0) modbus_1.timer--; if (modbus_1.timer == 1)   { modbus_1.status_read = 1;   }   } \/\/==========================================================================================<\/code><\/pre>\n
    \u041f\u043e\u0441\u044b\u043b\u043a\u0430 \u043f\u0440\u0438\u0448\u043b\u0430, \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u043c \u0440\u0430\u0437\u0431\u043e\u0440. \u041f\u0440\u043e\u0432\u0435\u0440\u044f\u0435\u0442\u0441\u044f \u0430\u0434\u0440\u0435\u0441, \u0434\u043b\u0438\u043d\u0430 \u043f\u0430\u043a\u0435\u0442\u0430, crc, \u0432\u044b\u0437\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0443\u044e\u0449\u0430\u044f \u0444\u0443\u043d\u043a\u0446\u0438\u044f. \u0415\u0441\u043b\u0438 \u0444\u0443\u043d\u043a\u0446\u0438\u044f \u043d\u0435\u0434\u043e\u0441\u0442\u0443\u043f\u043d\u0430 — \u043e\u0442\u043f\u0440\u0430\u0432\u043b\u044f\u0435\u0442\u0441\u044f \u043a\u043e\u0434 \u043e\u0448\u0438\u0431\u043a\u0438. \u041c\u043e\u0436\u043d\u043e \u043f\u043e \u0430\u043d\u0430\u043b\u043e\u0433\u0438\u0438 \u0434\u043e\u0431\u0430\u0432\u0438\u0442\u044c \u0438 \u0434\u0440\u0443\u0433\u0438\u0435 \u0444\u0443\u043d\u043a\u0446\u0438\u0438.<\/p>\n
    \/\/========================================================================================== \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 void  rx_mod_bus_1_rtu(void) { if (modbus_1.status_read == 1) {      volatile uint16_t crc16;  volatile uint8_t  func_status, func_read;     \/\/\u0415\u0441\u043b\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043c\u0430\u043b\u0435\u043d\u044c\u043a\u043e\u0439 \u0434\u043b\u0438\u043d\u044b  if (modbus_1.count_rx <5) {goto end;}   \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0441\u0435\u0442\u0435\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430  if (modbus_adr != modbus_1.buff_rx[0]) {goto end;}    \/\/\u0420\u0430\u0441\u0441\u0447\u0435\u0442 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b  crc16=crc_16(modbus_1.buff_rx,(modbus_1.count_rx-2));   \/\/\u0421\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u0435 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u044c\u043d\u043e\u0439 \u0441\u0443\u043c\u043c\u044b if (crc16!=((modbus_1.buff_rx[modbus_1.count_rx-2]<<8)|(modbus_1.buff_rx[modbus_1.count_rx-1]))) {goto end; }    \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0444\u0443\u043d\u0446\u0438\u0438 func_read=modbus_1.buff_rx[1];          \/\/\/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0441\u0442\u0438 \u043a\u043e\u0434\u0430 \u0444\u0443\u043d\u043a\u0446\u0438\u0438      if ((func_read==0x03)||(func_read==0x06)||(func_read==0x10)||(func_read==0x04)) { func_status=1;  }  else { func_status=0;  }        \/\/\u0424\u043e\u0440\u043c\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043e\u0442\u0432\u0435\u0442\u0430 \u043f\u0440\u0438 \u043e\u0448\u0438\u0431\u043a\u0438 \u0444\u0443\u043d\u0446\u0438\u0438      if (func_status==0)         {      modbus_1_send_error(modbus_adr, func_read, illegal_function);           goto end;         }          if (func_read == 0x03) {  modbus_1_func_03(); }       if (func_read == 0x06) {  modbus_1_func_06(); }       if (func_read == 0x10) {  modbus_1_func_10(); }       end:    modbus_1.status_read=0;    modbus_1.count_rx=0;   }  } \/\/==========================================================================================<\/code><\/pre>\n
    \u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 0\u044503.<\/p>\n
    \/========================================================================================== \/\/\u0424\u0443\u043d\u0446\u0438\u044f 03 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_03(void) {  volatile uint8_t  bus_adr; volatile uint16_t start_reg_adr;           \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441  \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f volatile uint16_t number_reg;              \/\/\u0427\u0438\u0441\u043b\u043e \u043f\u0440\u043e\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 volatile uint16_t temp;     volatile unsigned char count=3;            \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 \u043f\u043e\u0441\u043b\u044b\u043a\u0435 volatile unsigned char len_mess=5;         \/\/\u0414\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 volatile unsigned int crc;   bus_adr = modbus_adr; \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430 start_reg_adr=(modbus_1.buff_rx[2]<<8)|modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430 number_reg=(modbus_1.buff_rx[4]<<8)|modbus_1.buff_rx[5];     \/\/\u0427\u0438\u0441\u043b\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432      \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434 \u0437\u0430 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0433\u043e \u0447\u0442\u0435\u043d\u0438\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432     if ((start_reg_adr < modbus_1_func_03_min_adr)||(start_reg_adr > (modbus_1_func_03_max_adr + number_reg)))       {      modbus_1_send_error(bus_adr, 0x03, illegal_data_address);     goto end;       }      \/\/\u0433\u043e\u0442\u043e\u0432\u0438\u043c \u043f\u043e\u0441\u044b\u043b\u043a\u0443 \u043a \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438      modbus_1.buff_tx[0] = bus_adr;              \/\/\u0410\u0434\u0440\u0435\u0441\u0441      modbus_1.buff_tx[1] = 0x03;           \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f      modbus_1.buff_tx[2] = (number_reg*2);    \/\/\u041a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0431\u0430\u0439\u0442 \u0432 \u043f\u043e\u0441\u044b\u043b\u043a\u0435 \u043c\u043b\u0430\u0434\u0448\u0438\u0439       \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432      temp = start_reg_adr;        while (number_reg--)      {      modbus_1.buff_tx[count] = (modbus_1_reg.holding[temp]>>8);    count++; len_mess++;      modbus_1.buff_tx[count] = ((modbus_1_reg.holding[temp]));    count++; len_mess++;      temp++;       }          \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC        crc = crc_16(modbus_1.buff_tx , count);       modbus_1.buff_tx[count] = (crc>>8); count++;\/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442       modbus_1.buff_tx[count] = crc;                       \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442         \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445       modbus_1.lens_tx = len_mess; modbus_1.count_tx = 0;       tx_mod_bus_1_rtu();     end: return;   } \/\/==========================================================================================<\/code><\/pre>\n
    \u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 0\u044506.<\/p>\n
    \/\/========================================================================================== void modbus_1_func_06(void) {  volatile uint8_t  bus_adr; volatile uint16_t start_reg_adr;           \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441  \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f  volatile uint16_t  data;   \/\/\u0417\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u043c\u0430\u044f \u0434\u0430\u0442\u0430  volatile unsigned char count=6;            \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 \u043f\u043e\u0441\u043b\u044b\u043a\u0435 volatile unsigned char len_mess=8;         \/\/\u0414\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 volatile unsigned int crc;   bus_adr = modbus_adr; \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430  start_reg_adr = (modbus_1.buff_rx[2]<<8) | modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430 data          = (modbus_1.buff_rx[4]<<8) | modbus_1.buff_rx[5];   \/\/\u0417\u0430\u043f\u0438\u0441\u044b\u0432\u0430\u0435\u043c\u0430\u044f \u0434\u0430\u0442\u0430  \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434 \u0437\u0430 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0433\u043e \u0447\u0442\u0435\u043d\u0438\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 if ((start_reg_adr < modbus_1_func_06_min_adr)||(start_reg_adr > modbus_1_func_06_max_adr))  { modbus_1_send_error(bus_adr, 0x03, illegal_data_address);     goto end;  }       \/\/ modbus_1_reg.holding[start_reg_adr] = data; modbus_1_reg.holding_status[start_reg_adr] = 1;   \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043a\u043e\u043c\u0430\u043d\u0434\u044b  modbus_1.buff_tx[0] = bus_adr;               \/\/\u0410\u0434\u0440\u0435\u0441\u0441  modbus_1.buff_tx[1] = 0x06;          \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f  modbus_1.buff_tx[2] = (start_reg_adr)>>8;   \/\/\u0430\u0434\u0440\u0435\u0441\u0441  modbus_1.buff_tx[3] = (start_reg_adr);       \/\/\u0430\u0436\u0440\u0435\u0441\u0441  modbus_1.buff_tx[4] = (data)>>8;         \/\/\u0434\u0430\u043d\u043d\u044b\u0435  modbus_1.buff_tx[5] = (data);                \/\/\u0414\u0430\u043d\u043d\u044b\u0435  \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC crc = crc_16(modbus_1.buff_tx,count); modbus_1.buff_tx[count]=(crc>>8); \/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442 modbus_1.buff_tx[++count]=crc;            \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442        \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445 \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445 modbus_1.lens_tx = len_mess; modbus_1.count_tx = 0; tx_mod_bus_1_rtu(modbus_1.lens_tx);  end: return; } \/\/==========================================================================================<\/code><\/pre>\n
    \u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 0\u044510.<\/p>\n
     \/\/========================================================================================== void modbus_1_func_10(void) {        volatile uint8_t  bus_adr;    volatile uint16_t start_reg_adr;             \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441  \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u0434\u043b\u044f \u0447\u0442\u0435\u043d\u0438\u044f    volatile uint16_t number_reg;                \/\/\u0427\u0438\u0441\u043b\u043e \u043f\u0440\u043e\u0447\u0438\u0442\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432          volatile unsigned char count = 6;            \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0432 \u043f\u043e\u0441\u043b\u044b\u043a\u0435    volatile unsigned char len_mess = 8;         \/\/\u0414\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438    volatile unsigned int crc;    volatile uint16_t adr_data_buff;     volatile uint16_t count_reg = 0;             \/\/\u0421\u0447\u0435\u0442\u0447\u0438\u043a \u0437\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432     adr_data_buff = 7;                           \/\/ C \u0432\u043e\u0441\u044c\u043c\u043e\u0433\u043e \u0431\u0430\u0439\u0442\u0430 \u043d\u0430\u0447\u0438\u043d\u0430\u044e\u0442\u0441\u044f \u0434\u0430\u043d\u043d\u044b\u0435  \/\/   bus_adr = eeprom.modbus_adr;     \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430       bus_adr = modbus_adr; \/\/\u0410\u0434\u0440\u0435\u0441\u0441 \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u0430    start_reg_adr=(modbus_1.buff_rx[2]<<8)|modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430    number_reg=(modbus_1.buff_rx[4]<<8)|modbus_1.buff_rx[5];     \/\/\u0427\u0438\u0441\u043b\u043e \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432     \/\/\u041f\u0440\u043e\u0432\u0435\u0440\u043a\u0430 \u043d\u0430 \u0432\u044b\u0445\u043e\u0434 \u0437\u0430 \u0434\u0438\u0430\u043f\u0430\u0437\u043e\u043d \u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u043e\u0433\u043e \u0447\u0442\u0435\u043d\u0438\u044f \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432    if ((start_reg_adr < modbus_1_func_10_min_adr)||(start_reg_adr > (modbus_1_func_10_max_adr + number_reg)))     {        modbus_1_send_error(bus_adr, 0x03, illegal_data_address);        goto end;     }      while (number_reg--)     {    modbus_1_reg.holding[start_reg_adr]=(modbus_1.buff_rx[adr_data_buff]<<8); adr_data_buff++;    modbus_1_reg.holding[start_reg_adr]+=modbus_1.buff_rx[adr_data_buff];     adr_data_buff++;    modbus_1_reg.holding_status[start_reg_adr] = 1;               start_reg_adr++;      count_reg++;     }      \/\/\u0421\u0442\u0430\u0440\u0442\u043e\u0432\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441    start_reg_adr=(modbus_1.buff_rx[2]<<8)|modbus_1.buff_rx[3];  \/\/\u0427\u0442\u0435\u043d\u0438\u0435 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u043e\u0433\u043e \u0430\u0434\u0440\u0435\u0441\u0441\u0430     \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043a\u043e\u043c\u0430\u043d\u0434\u044b    modbus_1.buff_tx[0] = bus_adr;                   \/\/\u0410\u0434\u0440\u0435\u0441\u0441    modbus_1.buff_tx[1] = 0x10;                \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f    modbus_1.buff_tx[2] = (start_reg_adr)>>8;     \/\/\u0430\u0434\u0440\u0435\u0441\u0441    modbus_1.buff_tx[3] = (start_reg_adr);         \/\/\u0430\u0436\u0440\u0435\u0441\u0441    modbus_1.buff_tx[4] = (count_reg)>>8;         \/\/\u0427\u0438\u0441\u043b\u043e \u0437\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432    modbus_1.buff_tx[5] = (count_reg);               \/\/\u0427\u0438\u0441\u043b\u043e \u0437\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432    \/\/\u0420\u0430\u0441\u0447\u0435\u0442 CRC   crc = crc_16(modbus_1.buff_tx,count);   modbus_1.buff_tx[count] = (crc>>8);     \/\/\u041c\u043b\u0430\u0434\u0448\u0438\u0439 \u0431\u0430\u0439\u0442   modbus_1.buff_tx[++count] = crc;                \/\/\u0421\u0442\u0430\u0440\u0448\u0438\u0439 \u0431\u0430\u0439\u0442           \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445   \/\/\u041f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u0430\u043d\u043d\u044b\u0445   modbus_1.lens_tx = len_mess; modbus_1.count_tx = 0;   tx_mod_bus_1_rtu(modbus_1.lens_tx);   end: return;  } \/\/==========================================================================================<\/code><\/pre>\n
    \u041d\u0435\u043c\u043d\u043e\u0433\u043e \u043e \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0434\u0430\u043d\u043d\u044b\u0445. \u0424\u043e\u0440\u043c\u0438\u0440\u0443\u0435\u0442\u0441\u044f \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u0432 modbus_1.buff_tx[count]. \u041e\u043f\u0440\u0435\u0434\u0435\u043b\u044f\u0435\u0442\u0441\u044f \u0434\u043b\u0438\u043d\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 modbus_1.lens_tx.<\/p>\n
    \u0412 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 \u0432\u044b\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443, \u0432\u044b\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u043f\u0440\u0438\u0435\u043c, \u043b\u0438\u043d\u0438\u044e re_de \u043d\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0443, \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u0444\u043b\u0430\u0433 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e TXE<\/p>\n
    \/\/========================================================================================== \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0431\u0443\u0444\u0435\u0440\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 void  tx_mod_bus_1_rtu() { uint8_t temp;  modbus_1.count_tx = 0;  if (!(USART1->SR & USART_SR_RXNE)) { \/* \u0435\u0441\u043b\u0438 USART_SR_IDLE == 1 \u043b\u0438\u043d\u0438\u044f \u0441\u0432\u043e\u0431\u043e\u0434\u043d\u0430       *\/   USART1->CR1 &= ~USART_CR1_RE;  _modbus_1_tx_485;  USART1->CR1 |= USART_SR_TXE; \/* enable TX interrupt     *\/  } else { temp = USART1->DR; modbus_1.lens_tx = 0; }    } \/\/==========================================================================================<\/code><\/pre>\n
    \u0414\u0430\u043b\u0435\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0435 \u043e\u0431\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0432 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 USART1<\/p>\n
    \/\/ \u043f\u0435\u0440\u0434\u0430\u0447\u0430 \u0437\u0430\u043a\u043e\u043d\u0447\u0435\u043d\u0430 if ((StatusReg & USART_SR_TC)) {  USART1->SR &= ~USART_SR_TC; USART1->CR1 &= ~USART_CR1_TCIE; \/\/\u0432\u044b\u043a\u043b\u044e\u0447\u0438\u0442\u044c \u043a\u043e\u043d\u0435\u0446 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 _modbus_1_rx_485; \/\/ \u0440\u0435\u0436\u0438\u043c \u043f\u0440\u0438\u0435\u043c\u0430         USART1->CR1 |= USART_CR1_RE;         modbus_1.count_tx = 0;         modbus_1.status_tx = 0;  USART1->CR1 |= USART_CR1_RXNEIE; \/\/\u0420\u0430\u0437\u0440\u0435\u0448\u0435\u043d\u0438\u0435 \u043f\u0440\u0438\u0435\u043c\u0430  } \/\/---------------------------------------------------------------------- \/\/ \u043f\u0435\u0440\u0435\u0434\u0430\u044e\u0449\u0438\u0439 \u0431\u0443\u0444\u0435\u0440 \u043f\u0443\u0441\u0442 if ((StatusReg & USART_SR_TXE) && modbus_1.lens_tx) {  \/\/\u0435\u0441\u0442\u044c \u0435\u0449\u0435 \u0434\u0430\u043d\u043d\u044b\u0435 USART1->DR = modbus_1.buff_tx[modbus_1.count_tx]; modbus_1.count_tx ++; if (modbus_1.count_tx >= modbus_1.lens_tx)  {\/\/\u0432\u0441\u0435 \u043f\u0435\u0440\u0435\u0434\u0430\u043d\u043e, \u0436\u0434\u0435\u043c \u043a\u043e\u043d\u0446\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438 modbus_1.lens_tx = 0; USART1->CR1 &= ~USART_SR_TXE; \/* disable TX IRQ if nothing to send  *\/ USART1->CR1 |= USART_CR1_TCIE; \/\/\u0432\u043a\u043b\u044e\u0447\u0438\u0442\u044c \u043a\u043e\u043d\u0435\u0446 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438   } }\/\/USART_SR_TXE<\/code><\/pre>\n
    \u041f\u043e \u0437\u0430\u0432\u0435\u0440\u0448\u0435\u043d\u0438\u044e \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u0442\u0441\u044f \u043f\u0440\u0438\u0435\u043c. <\/p>\n
    \u0412\u043e\u0442 \u0438 \u0432\u0441\u0435. <\/p>\n<\/div>\n<\/div>\n<\/div>\n
    <\/div>\n

     \u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438  https:\/\/habr.com\/ru\/articles\/918168\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"
    <\/div>\n
    \n
    \n
    \n
    \n
    \u0412 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u0435 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u043e\u0439 \u0420\u042d\u0410 \u0434\u043b\u044f \u043d\u0443\u0436\u0434 \u043f\u0440\u043e\u043c\u044b\u0448\u043b\u0435\u043d\u043d\u043e\u0433\u043e \u043a\u043e\u043c\u043f\u043b\u0435\u043a\u0441\u0430 \u0432\u0441\u0442\u0440\u0435\u0447\u0430\u044e\u0442\u0441\u044f \u0437\u0430\u0434\u0430\u0447\u0438 \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b\u0430 ModBus RTU \u043d\u0430 \u041c\u041a. \u0412 \u0441\u0435\u0442\u0438 \u0435\u0441\u0442\u044c \u0433\u043e\u0442\u043e\u0432\u044b\u0435 \u0431\u0438\u0431\u043b\u0438\u043e\u0442\u0435\u043a\u0438 \u043f\u043e\u0434 \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u0440\u0435\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u0438. \u041d\u043e \u0447\u0430\u0441\u0442\u043e \u0437\u0430\u043a\u0430\u0437\u0447\u0438\u043a \u0432\u044b\u0431\u0438\u0440\u0430\u0435\u0442 \u041c\u041a \u0432 \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u043c\u043f\u043b\u0435\u043a\u0442\u0430\u0446\u0438\u0438, \u043a\u0443\u0434\u0430 \u043d\u0435 \u043e\u0441\u043e\u0431\u043e \u0438 \u043f\u043e\u0441\u0442\u0430\u0432\u0438\u0448\u044c \u0441\u0438\u0441\u0442\u0435\u043c\u0443  \u0440\u0435\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0432\u0440\u0435\u043c\u0435\u043d\u0438. <\/p>\n
    \u0421\u0442\u0430\u0442\u044c\u044f \u0431\u0443\u0434\u0435\u0442 \u043f\u043e\u043b\u0435\u0437\u043d\u0430 \u043a\u0430\u043a \u043d\u0430\u0447\u0438\u043d\u0430\u044e\u0449\u0438\u043c \u0442\u0430\u043a \u0438 \u0442\u0435\u043c \u043a\u0442\u043e \u0432 \u0442\u0435\u043c\u0435.<\/p>\n
    \u0418 \u0442\u0430\u043a… \u0415\u0441\u0442\u044c stm32f103ret6 (\u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u0442\u044c \u043c\u043e\u0436\u043d\u043e \u0438 \u043d\u0430 \u0434\u0440\u0443\u0433\u043e\u043c \u043a\u0440\u0438\u0441\u0442\u0430\u043b\u043b\u0435), \u0441\u0440\u0435\u0434\u0430 \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u043a\u0438 STM32CubeIDE  1.12.0.<\/p>\n
    \u0417\u0430\u0434\u0430\u0447\u0430: \u0440\u0435\u0430\u043b\u0438\u0437\u043e\u0432\u0430\u0442\u044c slave \u0443\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u043e, \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u044c 9600, \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b modbus rtu.<\/p>\n
    \u041e\u043f\u0438\u0441\u0430\u043d\u0438\u0435 \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b\u0430 \u043e\u0431\u043c\u0435\u043d\u0430 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u0445\u043e\u0440\u043e\u0448\u043e \u043e\u043f\u0438\u0441\u0430\u043d\u043e \u0432 \u0441\u0435\u0442\u0438, \u0438\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f \u043f\u0440\u0435\u0434\u043e\u0441\u0442\u0430\u0432\u043b\u0435\u043d\u0430 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u043f\u043e\u0434\u0440\u043e\u0431\u043d\u043e.<\/p>\n
    \u0414\u043b\u044f \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u0438 \u043d\u0430 \u041c\u041a \u0431\u0443\u0434\u0435\u043c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c USART1, TIM6, \u0432\u044b\u0432\u043e\u0434 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430 PA8 \u0434\u043b\u044f \u0443\u043f\u0440\u0430\u0432\u043b\u0435\u043d\u0438\u044f \u043f\u0440\u0438\u043c\u0435\u043c\/\u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 \u0434\u043b\u044f \u0444\u0438\u0437\u0438\u0447\u0435\u0441\u043a\u043e\u0433\u043e \u0434\u0440\u0430\u0439\u0432\u0435\u0440\u0430 RS-485.<\/p>\n
    \u0422\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 — \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u043a\u0432\u0430\u0440\u0446\u0435\u0432\u044b\u0439 \u0440\u0435\u0437\u043e\u043d\u0430\u0442\u043e\u0440 \u043d\u0430 8 \u041c\u0413\u0446.<\/p>\n
    1. \u0421\u043e\u0437\u0434\u0430\u0435\u043c \u043f\u0440\u043e\u0435\u043a\u0442 \u0432 STM32CubeIDE, \u0432\u044b\u0431\u0440\u0430\u0432 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0443\u044e\u0449\u0438\u0439 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440. \u0418\u043d\u0444\u043e\u0440\u043c\u0430\u0446\u0438\u044f \u0435\u0441\u0442\u044c \u0432 \u0441\u0435\u0442\u0438. \u0417\u0430\u043e\u0441\u0442\u0440\u044f\u0442\u044c \u043d\u0430 \u044d\u0442\u043e\u043c \u0432\u043d\u0438\u043c\u0430\u043d\u0438\u0435 \u043d\u0435 \u0431\u0443\u0434\u0443. <\/p>\n
    2. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u0440\u043e\u0435\u043a\u0442\u0430. <\/p>\n
    \u0417\u0430\u043f\u0443\u0441\u043a\u0430\u043c \u0444\u0430\u0439\u043b *.ioc \u0438\u0437 Project Explorer. \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Project Manager=>Code Generator. \u0421\u0442\u0430\u0432\u0438\u043c \u0433\u0430\u043b\u043e\u0447\u043a\u0443 Generate peripheral initialization as a pair of ‘.c\/ .h’ files per peripheral. (\u0414\u043b\u044f \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0438 \u0431\u0443\u0434\u0443\u0442 \u0441\u043e\u0437\u0434\u0430\u043d\u044b \u043e\u0442\u0434\u0435\u043b\u044c\u043d\u044b\u0435 \u0444\u0430\u0439\u043b\u044b \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0435)<\/p>\n
    \n
    \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u0440\u043e\u0435\u043a\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n
    3. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f.<\/p>\n
    \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => System Core =>RCC \u0438 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c High Speed Clock.<\/p>\n
    \n
    \u0412\u043a\u043b\u044e\u0447\u0430\u0435\u043c HSE<\/figcaption><\/div>\n<\/figure>\n
    \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Clock Configuration \u0438 \u043d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u0441\u0438\u0441\u0442\u0435\u043c\u0443 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f \u043a\u0430\u043a \u043d\u0430 \u0440\u0438\u0441\u0443\u043d\u043a\u0435.<\/p>\n
    \n
    \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f<\/figcaption><\/div>\n<\/figure>\n
    3. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 USART.<\/p>\n
    \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => Connectivity =>USART1. \u0412\u043e \u0432\u043a\u043b\u0430\u0434\u043a\u0443 \u043d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u044b \u043c\u043e\u0434\u0443\u043b\u044f \u0438 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u0433\u043b\u043e\u0431\u0430\u043b\u044c\u043d\u043e\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f. <\/p>\n
    \n
    \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 USART<\/figcaption><\/div>\n<\/figure>\n
    <\/p>\n
    \n
    \u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f USART<\/figcaption><\/div>\n<\/figure>\n
    4. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 TIM6. \u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u0440\u0430\u0437 \u0432 500 \u043c\u043a\u0441. <\/p>\n
    \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => Timers =>TIM6. \u0412\u043e \u0432\u043a\u043b\u0430\u0434\u043a\u0443 \u043d\u0430\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u044b \u043c\u043e\u0434\u0443\u043b\u044f \u0438 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u043c \u0433\u043b\u043e\u0431\u0430\u043b\u044c\u043d\u043e\u0435 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f.<\/p>\n
    \n
    \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0442\u0430\u043a\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f<\/figcaption><\/div>\n<\/figure>\n
    \n
    \u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u0442\u0430\u0439\u043c\u0435\u0440\u0430<\/figcaption><\/div>\n<\/figure>\n
    5. \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u0432\u044b\u0432\u043e\u0434\u0430 re_de.<\/p>\n
    \u041d\u0430 \u043f\u043e\u043b\u0435 Pinout Viev \u043a\u043b\u0438\u043a\u0430\u0435\u043c PA8 \u0438 \u0432\u044b\u0431\u0438\u0440\u0430\u0435\u043c \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0443\u044e\u0449\u0443\u044e \u0444\u0443\u043d\u043a\u0446\u0438\u044e \u043f\u043e\u0440\u0442\u0430 \u0432\u0432\u043e\u0434\u0430\/\u0432\u044b\u0432\u043e\u0434\u0430<\/p>\n
    \n
    \u0412\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u043e\u0440\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n
    \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0432\u043a\u043b\u0430\u0434\u043a\u0443 Pinaut&Configuration => System Core =>GPIO \u0438 \u0434\u0435\u043b\u0430\u0435\u043c \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0443 \u043f\u043e\u0440\u0442\u0430.<\/p>\n
    \n
    \u041d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u043e\u0440\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n
    6. \u0413\u0435\u043d\u0435\u0440\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u0430. <\/p>\n
    \u041d\u0430 \u043f\u0430\u043d\u0435\u043b\u0438 \u0437\u0430\u0434\u0430\u0447 \u043a\u043b\u0438\u043a\u0430\u0435\u043c \u043a\u043d\u043e\u043f\u043a\u0443 Device Configuration Tool Code Generation.<\/p>\n
    \n
    \u0413\u0435\u043d\u0435\u0440\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u0430<\/figcaption><\/div>\n<\/figure>\n
    7. \u0421\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u0444\u0430\u0439\u043b\u043e\u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0430.<\/p>\n
    \u0412 \u0432\u043a\u043b\u0430\u0434\u043a\u0435 Project Explorer =>Core \u0432\u043e \u0432\u043a\u043b\u0430\u0434\u043a\u0430\u0445 Inc \u0438 Srs \u0441\u043e\u0437\u0434\u0430\u0435\u043c \u0444\u0430\u0439\u043b\u044b cpu_init.* \u0438 mod_bus_rtu_1.*<\/p>\n
    \u0412 \u0444\u0430\u0439\u043b\u0435 cpu_init — \u0434\u043e\u043f\u043e\u043b\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u0430\u044f \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0430 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430<\/p>\n
    \u0412 \u0444\u0430\u0439\u043b\u0435 mod_bus_rtu_1 — \u0440\u0435\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0442\u043e\u043a\u043e\u043b\u0430.<\/p>\n
    \n
    \u0421\u043e\u0437\u0434\u0430\u043d\u0438\u0435 \u0444\u0430\u0439\u043b\u043e\u0432<\/figcaption><\/div>\n<\/figure>\n
    \u041e\u0442\u043a\u0440\u044b\u0432\u0430\u0435\u043c \u0444\u0430\u0439\u043b main.c \u0438 \u0434\u043e\u0431\u0430\u0432\u043b\u044f\u0435\u043c \u0441\u043e\u0437\u0434\u0430\u043d\u043d\u044b\u0435 \u0444\u0430\u0439\u043b\u044b \u043f\u0440\u043e\u0435\u043a\u0442\u0430.<\/p>\n
    \n
    \u041f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u0444\u0430\u0439\u043b\u043e\u0432<\/figcaption><\/div>\n<\/figure>\n
    8. \u041d\u0430\u043f\u043e\u043b\u043d\u044f\u0435\u043c \u0444\u0430\u0439\u043b\u044b.<\/p>\n
    cpu_init.h<\/p>\n
    \/*  * cpu_init.h  *  *  Created on: Jun 5, 2025  *       *\/  #ifndef INC_CPU_INIT_H_ #define INC_CPU_INIT_H_  \/\/================================================================================================ \/\/\u041f\u0440\u043e\u0442\u043e\u0442\u0438\u043f\u044b \u0444\u0443\u043d\u0446\u0438\u0439 void init_cpu(void);    \/\/\u0418\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \/\/================================================================================================  #endif \/* INC_CPU_INIT_H_ *\/<\/code><\/pre>\n
    cpu_init.\u0441<\/p>\n
    #include \"main.h\" #include \"cpu_init.h\"   \/\/========================================================================================================================== \/\/\u0418\u043d\u0438\u0446\u0438\u0430\u043b\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 void init_cpu(void) { \/\/\u043e\u0442\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435 \u043f\u043e\u0440\u0442\u043e\u0432 \u043e\u0442\u043b\u0430\u0434\u043a\u0438 (\u0434\u043b\u044f \u0444\u0443\u043d\u0446\u0438\u043e\u043d\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u043f\u0435 \u043f\u0435\u0440\u0435\u0444\u0438\u0440\u0438\u0438) AFIO -> MAPR |= AFIO_MAPR_SWJ_CFG_1; RCC->APB2ENR |= RCC_APB2ENR_AFIOEN;   } \/\/========================================================================================================================== <\/code><\/pre>\n
    mod_bus_rtu_1.h<\/p>\n
    \/*  * mod_bus_rtu_1.h  *  *  Created on: 1 \u0430\u043f\u0440. 2025 \u0433.  *       *\/  #ifndef INC_MOD_BUS_RTU_1_H_ #define INC_MOD_BUS_RTU_1_H_   #include \"main.h\"    \/\/========================================================================================================================== #define    _modbus_1_rx_485      HAL_GPIO_WritePin(rs485_re_de_GPIO_Port, rs485_re_de_Pin, GPIO_PIN_RESET);      \/\/\u043f\u0440\u0438\u0435\u043c 485 #define    _modbus_1_tx_485      HAL_GPIO_WritePin(rs485_re_de_GPIO_Port, rs485_re_de_Pin, GPIO_PIN_SET);      \/\/\u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0430 485   #define   modbus_1_rx_buff_lens     256 #define   modbus_1_tx_buff_lens     256   #define   modbus_1_func_03_min_adr  1 #define   modbus_1_func_03_max_adr  200  #define   modbus_1_func_06_min_adr  100 #define   modbus_1_func_06_max_adr  200  #define   modbus_1_func_10_min_adr  100 #define   modbus_1_func_10_max_adr  200   #define modbus_adr 1    #define   lens_tx_buff                 1000 #define   lens_rx_buff                 1000  \/\/========================================================================================================   \/\/======================================================================================================== \/\/\u041a\u043e\u0434\u044b \u043e\u0448\u0438\u0431\u043e\u043a modbus rtu #defineillegal_function0x01     \/\/\u041d\u0435\u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0439 \u043d\u043e\u043c\u0435\u0440 \u0444\u0443\u043d\u043a\u0446\u0438\u0438 #defineillegal_data_address0x02     \/\/\u041d\u0435\u0434\u043e\u043f\u0443\u0441\u0442\u0438\u043c\u044b\u0439 \u0430\u0434\u0440\u0435\u0441\u0441 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 #define     illegar_data0x03     \/\/\u041d\u0435\u043a\u043e\u0440\u0435\u043a\u0442\u043d\u044b\u0435 \u0434\u0430\u043d\u043d\u044b\u0435 #definefaile_device0x04 \/\/\u041d\u0435\u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u0435\u043c\u0430\u044f \u043e\u0448\u0438\u0431\u043a\u0430 #defineacknowledge0x05     \/\/\u0414\u0430\u043d\u043d\u044b\u0435 \u043d\u0435 \u0433\u043e\u0442\u043e\u0432\u044b #define     busy_device0x06 \/\/\u0421\u0438\u0441\u0442\u0435\u043c\u0430 \u0437\u0430\u043d\u044f\u0442\u0430 #define     nak_func0x07     \/\/\u0423\u0441\u0442\u0440\u043e\u0439\u0441\u0442\u0432\u043e \u043d\u0435 \u043c\u043e\u0436\u0435\u0442 \u0432\u044b\u043f\u043e\u043b\u043d\u0438\u0442\u044c \u0444\u0443\u043d\u043a\u0446\u0438\u044e \/\/========================================================================================================        \/\/========================================================================================================================== \/\/======================================================================================================== #pragma pack(push,1) typedef struct {  volatile uint32_t        timer;  volatile uint16_t        count_tx;     \/\/\u043f\u0435\u0440\u0435\u043c\u0435\u043d\u043d\u0430\u044f \u0441\u0447\u0435\u0442\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 volatile uint16_t        lens_tx;      \/\/\u0434\u043b\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438 volatile uint8_t         status_tx;    \/\/\u0444\u043b\u0430\u0433 \u0441\u0442\u0430\u0442\u0443\u0441\u0430, 0- \u043d\u0435\u0442 \u043e\u0442\u043f\u0440\u0430\u0443\u0438, 1- \u0438\u0434\u0435\u0442 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 volatile uint16_t        count_rx;     \/\/\u0441\u0447\u0435\u0442\u0441\u0438\u043a \u0441\u0447\u0435\u0442\u0430 \u043f\u043e\u0441\u044b\u043b\u043a\u0438 \u043f\u0440\u0438\u0435\u043c\u0430 volatile uint8_t         status_read;  \/\/0- \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043d\u0435 \u043f\u0440\u0438\u0448\u043b\u0430, 1- \u043f\u043e\u0441\u044b\u043b\u043a\u0430 \u043f\u0440\u0438\u0448\u043b\u0430   uint8_t                  buff_tx[lens_tx_buff];  \/\/\u0431\u0443\u0444\u0435\u0440 \u043f\u0440\u0438\u0435\u043c\u0430 uint8_t                  buff_rx[lens_rx_buff];  \/\/\u0431\u0443\u0444\u0435\u0440 \u043e\u0442\u043f\u0440\u0430\u0432\u043a\u0438   } glob_modbus_1; extern glob_modbus_1 modbus_1; #pragma pack(pop) \/\/========================================================================================================       \/\/======================================================================================================== \/\/Holding \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b. typedef struct {    volatile uint16_t holding[256];           \/\/\u0425\u043e\u043b\u0434\u0438\u043d\u0433 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b \u0434\u043b\u044f \u0440\u0430\u0431\u043e\u0442\u044b    volatile uint8_t  holding_status[256];    \/\/Status_registr  } glob_modbus_1_reg; extern glob_modbus_1_reg modbus_1_reg; \/\/========================================================================================================       \/\/========================================================================================================================== uint16_t crc_16(uint8_t *data, uint16_t data_len);   \/\/\u0424\u0443\u043d\u0446\u0438\u044f \u0440\u0430\u0441\u0447\u0435\u0442\u0430 CRC16 A001h \u043c\u0435\u043d\u044f\u044c\u0431 \u043c\u0435\u0441\u0442\u0430\u043c\u0438 \u043f\u0440\u0438 \u043f\u043e\u0441\u044b\u043b\u043a\u0435 \u043d\u0435 \u043d\u0430\u0434\u043e   void  timer_mod_bus_1_rtu_isr(void);                   \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0443 void  usart_mod_bus_1_rtu_isr(void);                \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443 \u0434\u0430\u043d\u043d\u044b\u0445   void  rx_mod_bus_1_rtu(void);                          \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0438\u043d\u044f\u0442\u043e\u0433\u043e \u043f\u0430\u043a\u0435\u0442\u0430 void  tx_mod_bus_1_rtu();            \/\/\u041e\u0442\u043f\u0440\u0430\u0432\u043a\u0430 \u043f\u0430\u043a\u0435\u0442\u0430 \u0438\u0437 \u0431\u0443\u0444\u0435\u0440\u0430 \u043f\u0435\u0440\u0435\u0434\u0430\u0447\u0438  void modbus_1_send_error(unsigned char adr, unsigned char function, unsigned char code_error); \/\/\u0412\u044b\u0434\u0430\u0447\u0430 \u043e\u0448\u0438\u0431\u043a\u0438 \u043c\u0430\u0441\u0442\u0435\u0440\u0443: \u0430\u0434\u0440\u0435\u0441\u0441, \u0444\u0443\u043d\u043a\u0446\u0438\u044f, \u043a\u043e\u0434 \u043e\u0448\u0438\u0431\u043a\u0438  void modbus_1_func_03(void);   \/\/\u0424\u0443\u043d\u0446\u0438\u044f 03 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_06(void);   \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f 06 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 void modbus_1_func_10(void);   \/\/\u0424\u0443\u043d\u043a\u0446\u0438\u044f 10 \u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430  \/\/==========================================================================================================================  #endif \/* INC_MOD_BUS_RTU_1_H_ *\/<\/code><\/pre>\n
    mod_bus_rtu_1.c<\/p>\n
     #include \"mod_bus_rtu_1.h\" #include \"stm32f1xx_hal.h\"     \/\/====================================================================================================================== glob_modbus_1 modbus_1={0,0,0,0,0};  glob_modbus_1_reg modbus_1_reg; \/\/======================================================================================================================   \/\/========================================================================================== \/\/\u041e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u0442\u0430\u0439\u043c\u0435\u0440\u0443 void  timer_mod_bus_1_rtu_isr(void) {   if (modbus_1.timer > 0) modbus_1.timer--; if (modbus_1.timer == 1)   { modbus_1.status_read = 1;   }   } \/\/==========================================================================================     \/\/========================================================================================== \/\/\u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u043f\u043e \u043f\u0440\u0438\u0435\u043c\u0443 \u0434\u0430\u043d\u043d\u044b\u0445 void  usart_mod_bus_1_rtu_isr(void) {  unsigned int StatusReg, temp_status; uint8_t temp;  StatusReg = USART1->SR; USART3->SR = 0;     \/\/---------------------------------------------------------------------- \/\/ \u0435\u0441\u0442\u044c \u0434\u0430\u043d\u043d\u044b\u0435 if ((StatusReg & USART_SR_RXNE)&& ~modbus_1.lens_tx) { \/* read interrupt         *\/  USART1->SR &= ~USART_SR_RXNE; modbus_1.buff_rx[modbus_1.count_rx] = USART1->DR; modbus_1.count_rx ++; modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11  } \/\/----------------------------------------------------------------------   \/\/----------------------------------------------------------------------         \/\/\u043e\u0431\u0440\u0430\u0431\u043e\u0442\u043a\u0430 \u043e\u0448\u0438\u0431\u043e\u043a  \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_PE))         {             temp_status = USART1->SR;         temp  = USART1->DR;         modbus_1.count_rx ++;         modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------               \/\/----------------------------------------------------------------------         if ((StatusReg & USART_SR_FE))         {          temp_status = USART1->SR;            temp  = USART1->DR;            modbus_1.count_rx ++;            modbus_1.timer = 11;   \/\/300 \u043c\u043a\u0441*11          }         \/\/----------------------------------------------------------------------<\/code><\/pre>\n<\/div>\n<\/div>\n<\/div>\n<\/div>\n","protected":false},"author":1,"featured_media":0,"comment_status":"open","ping_status":"open","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-463310","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/463310","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=463310"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/463310\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=463310"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=463310"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=463310"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}