{"id":477279,"date":"2026-04-24T13:14:49","date_gmt":"2026-04-24T13:14:49","guid":{"rendered":"https:\/\/savepearlharbor.com\/?p=477279"},"modified":"-0001-11-30T00:00:00","modified_gmt":"-0001-11-29T21:00:00","slug":"","status":"publish","type":"post","link":"https:\/\/savepearlharbor.com\/?p=477279","title":{"rendered":"\u0421\u0440\u0430\u0432\u043d\u0438\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u0430\u043d\u0430\u043b\u0438\u0437 RISC-V \u043c\u0438\u043a\u0440\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u0432 picorv32 \u0438 scr1 \u043f\u0440\u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0438 \u0432 FPGA"},"content":{"rendered":"<div xmlns=\"http:\/\/www.w3.org\/1999\/xhtml\">\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/e71\/262\/a17\/e71262a17e4a8aac08985d0e70e08f6c.png\" width=\"640\" height=\"100\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/e71\/262\/a17\/e71262a17e4a8aac08985d0e70e08f6c.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/e71\/262\/a17\/e71262a17e4a8aac08985d0e70e08f6c.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/figure>\n<p>\u0420\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0438 FPGA \u0447\u0430\u0441\u0442\u043e \u0441\u0442\u0430\u043b\u043a\u0438\u0432\u0430\u044e\u0442\u0441\u044f \u0441 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e\u0441\u0442\u044c\u044e \u0432\u043d\u0435\u0434\u0440\u0435\u043d\u0438\u044f \u0432 \u0441\u0432\u043e\u0439 \u043f\u0440\u043e\u0435\u043a\u0442 \u0441\u043e\u0444\u0442 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430. \u041a\u043e\u0433\u0434\u0430-\u0442\u043e \u0434\u0430\u0432\u043d\u043e \u043c\u044b \u043c\u043e\u0433\u043b\u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043f\u0440\u043e\u043f\u0440\u0438\u0435\u0442\u0430\u0440\u043d\u044b\u0435 Altera NIOS \u0438\u043b\u0438 Xilinx MicroBlase. \u041d\u043e \u0432\u0440\u0435\u043c\u044f \u0438\u0434\u0435\u0442. \u0412 \u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0438\u0435 \u0433\u043e\u0434\u044b \u043d\u0430\u0431\u043b\u044e\u0434\u0430\u0435\u0442\u0441\u044f \u0443\u0441\u0442\u043e\u0439\u0447\u0438\u0432\u044b\u0439 \u0442\u0440\u0435\u043d\u0434 \u043f\u0435\u0440\u0435\u0445\u043e\u0434\u0430 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u0439 \u041f\u041b\u0418\u0421 \u0432 \u0441\u0442\u043e\u0440\u043e\u043d\u0443 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0438 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b RISC-V.<\/p>\n<p>RISC-V \u044d\u0442\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u0430\u044f, \u0440\u0430\u0441\u0448\u0438\u0440\u044f\u0435\u043c\u0430\u044f \u0438 \u0431\u0435\u0441\u043f\u043b\u0430\u0442\u043d\u0430\u044f \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 (ISA), \u043a\u043e\u0442\u043e\u0440\u0430\u044f \u043d\u0435 \u0442\u0440\u0435\u0431\u0443\u0435\u0442 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u043e\u043d\u043d\u044b\u0445 \u043e\u0442\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439. \u041e\u0431\u0430 FPGA \u0432\u0435\u043d\u0434\u043e\u0440\u0430 Altera \u0438 Xilinx \u0443\u0436\u0435 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u0434\u0430\u0432\u043d\u043e \u043f\u0440\u0435\u0434\u043b\u0430\u0433\u0430\u044e\u0442 \u0438 \u0430\u043a\u0442\u0438\u0432\u043d\u043e \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u044e\u0442 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0443 RISC-V \u0432 \u0441\u0432\u043e\u0438\u0445 \u043d\u043e\u0432\u044b\u0445 \u043f\u0440\u043e\u0434\u0443\u043a\u0442\u0430\u0445, \u0442\u0435\u043f\u0435\u0440\u044c \u044d\u0442\u043e \u0443\u0436\u0435 \u0441\u043e\u0444\u0442 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u044b NIOS V \u0438 MicroBlase V \u0434\u043b\u044f FPGA.<\/p>\n<p>\u041e\u0434\u043d\u0430\u043a\u043e, \u0437\u0430\u0447\u0435\u043c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0432\u0441\u0451 \u0435\u0449\u0451 \u043f\u0440\u043e\u043f\u0440\u0438\u0435\u0442\u0430\u0440\u043d\u044b\u0435 \u044f\u0434\u0440\u0430, \u0435\u0441\u043b\u0438 \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c Open Source?<\/p>\n<p>\u0412 \u044d\u0442\u043e\u0439 \u0441\u0442\u0430\u0442\u044c\u0435 \u044f \u0441\u0440\u0430\u0432\u043d\u0438\u0432\u0430\u044e \u0434\u0432\u0430 Open Source RISC-V \u043c\u0438\u043a\u0440\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430:<br \/>1) picorv32 \u043e\u0442 \u043a\u043e\u043c\u043f\u0430\u043d\u0438\u0438 YoSys (<a href=\"https:\/\/github.com\/YosysHQ\/picorv32\" rel=\"noopener noreferrer nofollow\">https:\/\/github.com\/YosysHQ\/picorv32<\/a>) \u0438<br \/>2) scr1 \u043e\u0442 Syntacore (<a href=\"https:\/\/github.com\/syntacore\/scr1\" rel=\"noopener noreferrer nofollow\">https:\/\/github.com\/syntacore\/scr1<\/a>)<\/p>\n<p>\u0427\u0442\u043e \u0431\u0443\u0434\u0443 \u0441\u0440\u0430\u0432\u043d\u0438\u0432\u0430\u0442\u044c? \u041f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u044c \u0441\u043e\u0444\u0442 \u044f\u0434\u0435\u0440 \u0438 \u0437\u0430\u043d\u0438\u043c\u0430\u0435\u043c\u044b\u0435 \u0440\u0435\u0441\u0443\u0440\u0441\u044b \u0432 \u041f\u041b\u0418\u0421.<br \/>\u041a\u0430\u043a \u043f\u0440\u0430\u0432\u0438\u043b\u044c\u043d\u043e \u0441\u0440\u0430\u0432\u043d\u0438\u0442\u044c? \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0435\u0434\u0438\u043d\u0443\u044e \u0442\u0435\u0441\u0442\u043e\u0432\u0443\u044e \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0443 \u043d\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u0443\u044e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 C, \u043d\u0430\u043f\u0440\u0438\u043c\u0435\u0440 Dhrystone, \u0438 \u0441\u043a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u0443\u044e \u0432 \u0431\u0438\u043d\u0430\u0440\u043d\u044b\u0439 \u0444\u0430\u0439\u043b, \u0438\u043b\u0438 HEX \u0444\u0430\u0439\u043b \u0438 \u0437\u0430\u043f\u0443\u0441\u043a\u0430\u0435\u043c\u0443\u044e \u0432 \u0434\u0432\u0443\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043d\u043e \u043e\u0434\u0438\u043d\u0430\u043a\u043e\u0432\u044b\u0445 SOC, \u043d\u043e \u0441 \u0440\u0430\u0437\u043d\u044b\u043c\u0438 \u044f\u0434\u0440\u0430\u043c\u0438 RISC-V.<\/p>\n<p>\u0418\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u043e, \u0447\u0442\u043e \u0432 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0430\u0445 picorv32 \u0435\u0441\u0442\u044c \u0442\u0435\u0441\u0442 Dhrystone \u0438 \u0432 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0430\u0445 scr1 \u0435\u0441\u0442\u044c \u0442\u0435\u0441\u0442 Dhrystone, \u043d\u043e \u0443 \u043d\u0438\u0445 \u0445\u043e\u0442\u044c \u0438 \u043f\u043e\u0445\u043e\u0436\u0438\u0435, \u043d\u043e \u0432\u0441\u0451 \u0436\u0435 \u0440\u0430\u0437\u043d\u044b\u0435 \u0444\u0430\u0439\u043b\u044b \u043f\u043e \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u043c\u043e\u043c\u0443! \u041a\u0440\u043e\u043c\u0435 \u044d\u0442\u043e\u0433\u043e, \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0438 \u044d\u0442\u0438\u0445 \u044f\u0434\u0435\u0440 \u0441\u0441\u044b\u043b\u0430\u044e\u0442\u0441\u044f \u043d\u0430 \u0440\u0430\u0437\u043d\u044b\u0435 \u0442\u0443\u043b\u0447\u0435\u0439\u043d\u044b \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438. \u0421\u043e\u0433\u043b\u0430\u0441\u0438\u0442\u0435\u0441\u044c, \u0447\u0442\u043e \u043d\u0435 \u0441\u043e\u0432\u0441\u0435\u043c \u0432\u0435\u0440\u043d\u043e \u0441\u043e\u0431\u0438\u0440\u0430\u0442\u044c \u0435\u0434\u0438\u043d\u0443\u044e \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0443 \u0440\u0430\u0437\u043d\u044b\u043c\u0438 \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440\u0430\u043c\u0438. \u0414\u043b\u044f \u0447\u0438\u0441\u0442\u043e\u0442\u044b \u044d\u043a\u0441\u043f\u0435\u0440\u0438\u043c\u0435\u043d\u0442\u0430 \u044f \u0431\u0443\u0434\u0443 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043e\u0434\u0438\u043d \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440 \u0432\u0437\u044f\u0442\u044b\u0439 \u0432\u043e\u0442 \u043e\u0442\u0441\u044e\u0434\u0430: <a href=\"https:\/\/syntacore.com\/tools\/development-tools\" rel=\"noopener noreferrer nofollow\">https:\/\/syntacore.com\/tools\/development-tools<\/a> \u0423 \u043c\u0435\u043d\u044f \u043f\u043e\u043b\u0443\u0447\u0438\u0442\u0441\u044f \u043e\u0434\u043d\u0430 &#171;\u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0430&#187; \u0434\u043b\u044f \u0434\u0432\u0443\u0445 \u0440\u0430\u0437\u043d\u044b\u0445 SOC \u0438 \u0442\u043e\u0433\u0434\u0430 \u044d\u0442\u043e \u0431\u0443\u0434\u0435\u0442 \u0441\u0430\u043c\u043e\u0435 \u043e\u0431\u044a\u0435\u043a\u0442\u0438\u0432\u043d\u043e\u0435 \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u0435.<\/p>\n<p>\u0415\u0449\u0435 \u043e\u0434\u043d\u043e \u0437\u0430\u043c\u0435\u0447\u0430\u043d\u0438\u0435: RISC-V \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 \u043f\u043e\u0434\u0440\u0430\u0437\u0443\u043c\u0435\u0432\u0430\u0435\u0442 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0438\u0440\u0443\u0435\u043c\u043e\u0441\u0442\u044c. \u0415\u0441\u043b\u0438 \u043c\u0430\u043b\u043e \u0440\u0435\u0441\u0443\u0440\u0441\u043e\u0432 \u0432 \u041f\u041b\u0418\u0421, \u0442\u043e \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0443\u0440\u0435\u0437\u0430\u043d\u043d\u0443\u044e \u0432\u0435\u0440\u0441\u0438\u044e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0438 \u0443 \u043d\u0435\u0433\u043e \u0431\u0443\u0434\u0435\u0442 \u043a \u043f\u0440\u0438\u043c\u0435\u0440\u0443 \u043d\u0435 32 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u043e\u0431\u0449\u0435\u0433\u043e \u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f, \u0430 \u0442\u043e\u043b\u044c\u043a\u043e 16. \u0418\u043b\u0438 \u043c\u043e\u0436\u043d\u043e \u0441\u0434\u0435\u043b\u0430\u0442\u044c \u0432\u0435\u0440\u0441\u0438\u044e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0431\u0435\u0437 \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044f. \u0412\u0430\u0440\u0438\u0430\u043d\u0442\u043e\u0432 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u043c\u043e\u0436\u0435\u0442 \u0431\u044b\u0442\u044c \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u043c\u043d\u043e\u0433\u043e, \u043d\u043e \u0447\u0442\u043e\u0431\u044b \u0441\u0438\u043b\u044c\u043d\u043e \u043d\u0435 \u0437\u0430\u043c\u043e\u0440\u0430\u0447\u0438\u0432\u0430\u0442\u044c\u0441\u044f \u044f \u043e\u0441\u0442\u0430\u043d\u043e\u0432\u0438\u043b\u0441\u044f \u043d\u0430 \u0434\u0432\u0443\u0445 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f\u0445:<\/p>\n<ol>\n<li>\n<p>\u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f, 16 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432, \u0431\u0435\u0437 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u043e\u0433\u043e \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044f, \u043d\u043e \u0441 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u043e\u0439 \u0441\u0436\u0430\u0442\u044b\u0445 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0439<\/p>\n<\/li>\n<li>\n<p>\u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f, 32 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430, \u0441 \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u0435\u043c, \u0441 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u043e\u0439 \u0441\u0436\u0430\u0442\u044b\u0445 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0439.<\/p>\n<\/li>\n<\/ol>\n<p>\u0422\u0430\u043a\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c, \u043c\u043e\u0438 \u0442\u0435\u0441\u0442\u044b \u043a\u043e\u0441\u043d\u0443\u0442\u0441\u044f \u0434\u0432\u0443\u0445 \u0440\u0430\u0437\u043d\u044b\u0445 \u044f\u0434\u0435\u0440 \u0432 \u0434\u0432\u0443\u0445 \u0440\u0430\u0437\u043d\u044b\u0445 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f\u0445.<\/p>\n<p>\u0417\u0430\u043f\u0443\u0441\u043a\u0430\u0442\u044c \u044d\u0442\u0438 SOC \u044f \u0431\u0443\u0434\u0443 \u043d\u0430 \u043f\u043b\u0430\u0442\u0430\u0445 <a href=\"https:\/\/marsohod.org\/projects\/marsohod3-board-prj\" rel=\"noopener noreferrer nofollow\">\u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343<\/a> \u0441 \u0447\u0438\u043f\u043e\u043c FPGA MAX10 50K \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u043e\u0432 \u0438 \u043d\u0430 \u043f\u043b\u0430\u0442\u0435 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343\u0431\u0438\u0441 \u0441 \u0447\u0438\u043f\u043e\u043c FPGA MAX10 8K \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u043e\u0432.<\/p>\n<p>\u041a\u0440\u043e\u043c\u0435 \u044d\u0442\u043e\u0433\u043e, \u044f \u0431\u0443\u0434\u0443 \u0437\u0430\u043f\u0443\u0441\u043a\u0430\u0442\u044c \u0442\u0435\u0441\u0442\u0431\u0435\u043d\u0447\u0438 \u0434\u043b\u044f \u0432\u0441\u0435\u0445 \u044d\u0442\u0438\u0445 \u0447\u0435\u0442\u044b\u0440\u0435\u0445 \u0441\u043b\u0443\u0447\u0430\u0435\u0432.<\/p>\n<p>\u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u043c\u043e\u0435\u0433\u043e \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0434\u043b\u044f \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u044f \u044f\u0434\u0435\u0440 \u043d\u0430\u0445\u043e\u0434\u044f\u0442\u0441\u044f \u043d\u0430 github <a href=\"https:\/\/github.com\/marsohod4you\/riscv-compare\" rel=\"noopener noreferrer nofollow\">https:\/\/github.com\/marsohod4you\/riscv-compare<\/a> \u0423\u0447\u0442\u0438\u0442\u0435, \u0447\u0442\u043e \u044d\u0442\u043e\u0442 \u043f\u0440\u043e\u0435\u043a\u0442 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u0442 \u0432 \u0441\u0435\u0431\u044f \u0441\u0443\u0431\u043c\u043e\u0434\u0443\u043b\u0438 git \u0434\u043b\u044f \u043a\u0430\u0436\u0434\u043e\u0433\u043e \u0438\u0437 \u044f\u0434\u0435\u0440 scr1 \u0438 picorv32.<\/p>\n<h2>\u041a\u043b\u044e\u0447\u0435\u0432\u044b\u0435 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 PicoRV32, YosysHQ<\/h2>\n<p>PicoRV32 \u2014 \u044d\u0442\u043e \u043a\u043e\u043c\u043f\u0430\u043a\u0442\u043d\u043e\u0435 \u0438 \u0433\u0438\u0431\u043a\u043e\u0435 \u044f\u0434\u0440\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430, \u0440\u0435\u0430\u043b\u0438\u0437\u0443\u044e\u0449\u0435\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0443 RISC-V (RV32IMC) \u0438 \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u043d\u043e\u0435 \u0434\u043b\u044f \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u044f \u0432 FPGA \u0438 ASIC. \u041e\u0441\u043d\u043e\u0432\u043d\u044b\u0435 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0438:<\/p>\n<ul>\n<li>\n<p>\u041e\u043f\u0442\u0438\u043c\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u043e \u0440\u0430\u0437\u043c\u0435\u0440\u0443 \u0438 \u0447\u0430\u0441\u0442\u043e\u0442\u0435. <\/p>\n<\/li>\n<li>\n<p>\u0413\u0438\u0431\u043a\u0430\u044f \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f: \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442 \u0440\u0430\u0437\u043d\u044b\u0435 \u0432\u0430\u0440\u0438\u0430\u043d\u0442\u044b \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u043a\u043e\u043c\u0430\u043d\u0434 \u2014 RV32E, RV32I, RV32IC, RV32IM, RV32IMC. <\/p>\n<\/li>\n<li>\n<p>\u041c\u043e\u0436\u043d\u043e \u043e\u0442\u043a\u043b\u044e\u0447\u0430\u0442\u044c \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b x16\u2026x31, \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 RDCYCLE[H], RDTIME[H], RDINSTRET[H], \u0447\u0442\u043e \u0443\u043c\u0435\u043d\u044c\u0448\u0430\u0435\u0442 \u0440\u0430\u0437\u043c\u0435\u0440 \u044f\u0434\u0440\u0430. <\/p>\n<\/li>\n<li>\n<p>\u0418\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u044b: \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b \u0442\u0440\u0438 \u0432\u0430\u0440\u0438\u0430\u043d\u0442\u0430 \u044f\u0434\u0440\u0430 \u0441 \u0440\u0430\u0437\u043d\u044b\u043c\u0438 \u0448\u0438\u043d\u0430\u043c\u0438 \u2014 \u043f\u0440\u043e\u0441\u0442\u043e\u0439 native-\u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441, AXI4-Lite (picorv32_axi) \u0438 Wishbone (picorv32_wb), \u0447\u0442\u043e \u043e\u0431\u043b\u0435\u0433\u0447\u0430\u0435\u0442 \u0438\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u044e \u0432 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0435 \u0441\u0438\u0441\u0442\u0435\u043c\u044b. <\/p>\n<\/li>\n<\/ul>\n<p>\u041e\u043f\u0446\u0438\u043e\u043d\u0430\u043b\u044c\u043d\u044b\u0435 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u0438:<\/p>\n<ul>\n<li>\n<p>\u0412\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u044b\u0439 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 IRQ. <\/p>\n<\/li>\n<li>\n<p>\u0418\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u0441\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 (PCPI) \u0434\u043b\u044f \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u0438\u044f \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u043a\u043e\u043c\u0430\u043d\u0434. <\/p>\n<\/li>\n<li>\n<p>\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u0445 \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044f\/\u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044f \u0438 barrel-shifter. <\/p>\n<\/li>\n<li>\n<p>\u0412\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u044c \u0432\u044b\u0431\u043e\u0440\u0430 \u043c\u0435\u0436\u0434\u0443 \u043e\u0434\u043d\u043e- \u0438 \u0434\u0432\u0443\u0445\u043f\u043e\u0440\u0442\u043e\u0432\u043e\u0439 \u043e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u0435\u0439 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432\u043e\u0433\u043e \u0444\u0430\u0439\u043b\u0430 \u0434\u043b\u044f \u0431\u0430\u043b\u0430\u043d\u0441\u0430 \u043c\u0435\u0436\u0434\u0443 \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u044c\u044e \u0438 \u0440\u0430\u0437\u043c\u0435\u0440\u043e\u043c. <\/p>\n<\/li>\n<li>\n<p>\u0422\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430: \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0435 \u0435\u0441\u0442\u044c \u043c\u043d\u043e\u0436\u0435\u0441\u0442\u0432\u043e \u0442\u0435\u0441\u0442\u0431\u0435\u043d\u0447\u0435\u0439, \u043f\u0440\u0438\u043c\u0435\u0440\u044b SoC, \u0433\u043e\u0442\u043e\u0432\u044b\u0435 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438 \u0438 \u0441\u043a\u0440\u0438\u043f\u0442\u044b \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438 \u0438 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438 (Icarus Verilog, GtkWave), \u0430 \u0442\u0430\u043a\u0436\u0435 \u043f\u043e\u0434\u0440\u043e\u0431\u043d\u044b\u0435 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 \u043f\u043e \u0441\u0431\u043e\u0440\u043a\u0435 \u0438 \u0437\u0430\u043f\u0443\u0441\u043a\u0443 \u043d\u0430 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0445 \u043f\u043b\u0430\u0442\u0430\u0445. <\/p>\n<\/li>\n<li>\n<p>\u041b\u0438\u0446\u0435\u043d\u0437\u0438\u044f: \u044f\u0434\u0440\u043e \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u0435\u0442\u0441\u044f \u043f\u043e \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0438 ISC (\u0430\u043d\u0430\u043b\u043e\u0433 MIT\/BSD), \u0447\u0442\u043e \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0441\u0432\u043e\u0431\u043e\u0434\u043d\u043e\u0435 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435 \u0432 \u043a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0445 \u0438 \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0445 \u043f\u0440\u043e\u0435\u043a\u0442\u0430\u0445. <\/p>\n<\/li>\n<\/ul>\n<p>\u041f\u0440\u0438\u043c\u0435\u043d\u0435\u043d\u0438\u0435: \u0445\u043e\u0440\u043e\u0448\u043e \u043f\u043e\u0434\u0445\u043e\u0434\u0438\u0442 \u043a\u0430\u043a \u0432\u0441\u043f\u043e\u043c\u043e\u0433\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 \u0432 FPGA\/ASIC, \u0434\u043b\u044f \u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0445 \u0446\u0435\u043b\u0435\u0439, \u043f\u0440\u043e\u0442\u043e\u0442\u0438\u043f\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f SoC \u0438 \u0432\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c\u044b\u0445 \u0440\u0435\u0448\u0435\u043d\u0438\u0439. <\/p>\n<p>\u041f\u0440\u0435\u0434\u043f\u043e\u043b\u0430\u0433\u0430\u0435\u043c\u043e\u0435 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435 \u043c\u0438\u043a\u0440\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0432 FPGA \u0441\u043e\u0432\u043c\u0435\u0441\u0442\u043d\u043e \u0441 \u0432\u043d\u0435\u0448\u043d\u0435\u0439 SPI Flash \u043f\u0430\u043c\u044f\u0442\u044c\u044e, \u0433\u0434\u0435 \u0445\u0440\u0430\u043d\u0438\u0442\u0441\u044f \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0430. \u0412\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u0430\u044f \u0432 SOC \u0441\u0442\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u0430\u044f \u043f\u0430\u043c\u044f\u0442\u044c, \u043f\u043e \u0443\u043c\u043e\u043b\u0447\u0430\u043d\u0438\u044e \u0432\u0441\u0435\u0433\u043e 1 \u043a\u0438\u043b\u043e\u0431\u0430\u0439\u0442 \u0441\u043b\u0443\u0436\u0438\u0442 \u043a\u044d\u0448\u0435\u043c \/ scratchpad \u0434\u043b\u044f \u0432\u043d\u0435\u0448\u043d\u0435\u0439 flash \u043f\u0430\u043c\u044f\u0442\u0438. \u0422\u0430\u043a\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c \u043d\u0435 \u043d\u0443\u0436\u043d\u043e \u0437\u0430\u0431\u043e\u0442\u0438\u0442\u044c\u0441\u044f \u043e \u043c\u0438\u043d\u0438\u043c\u0438\u0437\u0430\u0446\u0438\u0438 \u0440\u0430\u0437\u043c\u0435\u0440\u0430 \u043a\u043e\u0434\u0430 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u0441\u043a\u0438\u0445 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c.<\/p>\n<p>\u0412\u043e\u0442 \u0442\u0438\u043f\u043e\u0432\u0430\u044f \u0431\u043b\u043e\u043a \u0441\u0445\u0435\u043c\u0430 SOC, \u043a\u043e\u0442\u043e\u0440\u0443\u044e \u0440\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0443\u0435\u0442 YosysHQ:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/5e3\/0d0\/fe9\/5e30d0fe95a9a694bf96eb07650e61e4.png\" alt=\"\u0420\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0443\u0435\u043c\u0430\u044f \u0441\u0445\u0435\u043c\u0430 SOC \u0441 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435\u043c \u0432\u043d\u0435\u0448\u043d\u0435\u0439 FLASH\" title=\"\u0420\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0443\u0435\u043c\u0430\u044f \u0441\u0445\u0435\u043c\u0430 SOC \u0441 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435\u043c \u0432\u043d\u0435\u0448\u043d\u0435\u0439 FLASH\" width=\"821\" height=\"569\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/5e3\/0d0\/fe9\/5e30d0fe95a9a694bf96eb07650e61e4.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/5e3\/0d0\/fe9\/5e30d0fe95a9a694bf96eb07650e61e4.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>\u0420\u0435\u043a\u043e\u043c\u0435\u043d\u0434\u0443\u0435\u043c\u0430\u044f \u0441\u0445\u0435\u043c\u0430 SOC \u0441 \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0435\u043c \u0432\u043d\u0435\u0448\u043d\u0435\u0439 FLASH<\/figcaption><\/div>\n<\/figure>\n<p>\u0412 \u0441\u0432\u043e\u0451\u043c \u0436\u0435 \u043f\u0440\u043e\u0435\u043a\u0442\u0435 \u0434\u043b\u044f \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u044f \u0445\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u0438\u0441\u0442\u0438\u043a picorv32 \u0438 scr1 \u044f \u0431\u0443\u0434\u0443 \u0434\u0435\u043b\u0430\u0442\u044c \u0441\u043e\u0432\u0441\u0435\u043c \u043d\u0435 \u0442\u0430\u043a, \u0430 \u0433\u043e\u0440\u0430\u0437\u0434\u043e \u043f\u0440\u043e\u0449\u0435. \u0423 \u043c\u0435\u043d\u044f \u043d\u0435 \u0431\u0443\u0434\u0435\u0442 \u0432\u043d\u0435\u0448\u043d\u0435\u0439 \u0444\u043b\u044d\u0448 \u043f\u0430\u043c\u044f\u0442\u0438, \u0430 \u0432\u0441\u044e \u0442\u0435\u0441\u0442\u043e\u0432\u0443\u044e \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0443 Dhrystone \u044f \u0440\u0430\u0437\u043c\u0435\u0449\u0443 \u0432 \u0441\u0442\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u043e\u0439 \u043f\u0430\u043c\u044f\u0442\u0438 \u041f\u041b\u0418\u0421 32 \u043a\u0438\u043b\u043e\u0431\u0430\u0439\u0442\u0430 \u0432 \u0430\u0434\u0440\u0435\u0441\u043d\u043e\u043c \u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u0441\u0442\u0432\u0435 \u043c\u0438\u043a\u0440\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u043f\u043e \u0430\u0434\u0440\u0435\u0441\u0443 \u043d\u043e\u043b\u044c. \u041f\u0440\u0438 \u0432\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u0438 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u043e\u043d \u0431\u0443\u0434\u0435\u0442 \u0441\u0440\u0430\u0437\u0443 \u0447\u0438\u0442\u0430\u0442\u044c \u0438 \u0438\u0441\u043f\u043e\u043b\u043d\u044f\u0442\u044c \u043a\u043e\u043c\u0430\u043d\u0434\u044b \u0441 \u0430\u0434\u0440\u0435\u0441\u0430 \u043d\u043e\u043b\u044c. \u041d\u0438\u043a\u0430\u043a\u0438\u0445 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 \u044f \u043d\u0435 \u0431\u0443\u0434\u0443 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c. \u0412\u043e\u0442 \u0442\u0430\u043a\u0430\u044f \u0431\u0443\u0434\u0435\u0442 \u043c\u043e\u044f \u043f\u0440\u043e\u0441\u0442\u0430\u044f \u0441\u0438\u0441\u0442\u0435\u043c\u0430 \u043d\u0430 \u043a\u0440\u0438\u0441\u0442\u0430\u043b\u043b\u0435:<\/p>\n<figure class=\"\"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/3e0\/d78\/d5c\/3e0d78d5c9f458c0fcc0f2e9f25cbbc9.png\" alt=\"\u041c\u043e\u044f picorv32 soc\" title=\"\u041c\u043e\u044f picorv32 soc\" width=\"512\" height=\"261\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/3e0\/d78\/d5c\/3e0d78d5c9f458c0fcc0f2e9f25cbbc9.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/3e0\/d78\/d5c\/3e0d78d5c9f458c0fcc0f2e9f25cbbc9.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>\u041c\u043e\u044f picorv32 soc<\/figcaption><\/div>\n<\/figure>\n<p>\u0412 \u043c\u043e\u0435\u0439 \u043f\u0440\u043e\u0441\u0442\u0435\u0439\u0448\u0435\u0439 SOC \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 picorv32 \u0431\u0443\u0434\u0435\u0442 \u0442\u043e\u043b\u044c\u043a\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440, \u0438 \u043d\u0430 \u0448\u0438\u043d\u0435 \u0434\u0430\u043d\u043d\u044b\u0445 \u0441\u0442\u0430\u0442\u0438\u0447\u0435\u0441\u043a\u0430\u044f \u043f\u0430\u043c\u044f\u0442\u044c \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c \u0438 \u0434\u0430\u043d\u043d\u044b\u0445, \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u043f\u043e\u0440\u0442, \u0440\u0435\u0433\u0438\u0441\u0442\u0440 7\u043c\u0438 \u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u043e\u0433\u043e \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0430 \u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u043d\u0430 \u0437\u0430\u043f\u0438\u0441\u044c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c\u044b\u0439 \u0432\u043e \u0432\u0440\u0435\u043c\u044f \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438. \u041a\u043e\u0433\u0434\u0430 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0430 \u0437\u0430\u043f\u0438\u0448\u0435\u0442 \u0432 \u044d\u0442\u043e\u0442 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0447\u0442\u043e \u043d\u0438 \u0431\u0443\u0434\u044c &#8212; \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440 \u043e\u0441\u0442\u0430\u043d\u043e\u0432\u0438\u0442 \u0441\u0432\u043e\u044e \u0440\u0430\u0431\u043e\u0442\u0443.<\/p>\n<p>\u041d\u0430 \u0441\u0435\u043c\u0438-\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u043e\u043c \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0435 \u044f \u0431\u0443\u0434\u0443 \u043e\u0442\u043e\u0431\u0440\u0430\u0436\u0430\u0442\u044c \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442 \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u044f \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 \u0432 Dhrystone.<\/p>\n<h2>\u041a\u043b\u044e\u0447\u0435\u0432\u044b\u0435 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 SCR1<\/h2>\n<p>Syntacore SCR1 \u2014 \u044d\u0442\u043e \u0432\u044b\u0441\u043e\u043a\u043e\u043a\u0430\u0447\u0435\u0441\u0442\u0432\u0435\u043d\u043d\u043e\u0435 \u043e\u0442\u043a\u0440\u044b\u0442\u043e\u0435 \u044f\u0434\u0440\u043e \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430, \u0441\u043e\u0432\u043c\u0435\u0441\u0442\u0438\u043c\u043e\u0435 \u0441 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043e\u0439 RISC-V, \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0430\u043d\u043d\u043e\u0435 \u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u043c\u043e\u0435 \u043a\u043e\u043c\u043f\u0430\u043d\u0438\u0435\u0439 Syntacore, \u0441\u0435\u0439\u0447\u0430\u0441 Yadro. \u041e\u0441\u043d\u043e\u0432\u043d\u044b\u0435 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430:<\/p>\n<ul>\n<li>\n<p>\u041e\u0442\u043a\u0440\u044b\u0442\u0430\u044f \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u044f: \u044f\u0434\u0440\u043e \u0440\u0430\u0441\u043f\u0440\u043e\u0441\u0442\u0440\u0430\u043d\u044f\u0435\u0442\u0441\u044f \u043f\u043e \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u0438 SHL, \u0447\u0442\u043e \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u043d\u0435\u043e\u0433\u0440\u0430\u043d\u0438\u0447\u0435\u043d\u043d\u043e\u0435 \u043a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u043e\u0435 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435, \u0447\u0442\u043e \u0440\u0435\u0434\u043a\u043e \u0432\u0441\u0442\u0440\u0435\u0447\u0430\u0435\u0442\u0441\u044f \u0441\u0440\u0435\u0434\u0438 \u044f\u0434\u0435\u0440, \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u043c\u044b\u0445 \u043a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u043c\u0438 \u043a\u043e\u043c\u043f\u0430\u043d\u0438\u044f\u043c\u0438. <\/p>\n<\/li>\n<li>\n<p>\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043d\u044b\u0445 \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u0438\u0439: \u0440\u0435\u0430\u043b\u0438\u0437\u0443\u0435\u0442 \u0431\u0430\u0437\u043e\u0432\u044b\u0439 \u043d\u0430\u0431\u043e\u0440 \u043a\u043e\u043c\u0430\u043d\u0434 RV32I \u0438\u043b\u0438 RV32E \u0441 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u044c\u044e \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u044f \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u0438\u0439 RVM (\u0443\u043c\u043d\u043e\u0436\u0435\u043d\u0438\u0435\/\u0434\u0435\u043b\u0435\u043d\u0438\u0435) \u0438 RVC (\u0441\u0436\u0430\u0442\u044b\u0435 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438). <\/p>\n<\/li>\n<li>\n<p>\u0420\u0435\u0436\u0438\u043c\u044b \u043f\u0440\u0438\u0432\u0438\u043b\u0435\u0433\u0438\u0439: \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442 \u0442\u043e\u043b\u044c\u043a\u043e \u043c\u0430\u0448\u0438\u043d\u043d\u044b\u0439 \u0440\u0435\u0436\u0438\u043c \u043f\u0440\u0438\u0432\u0438\u043b\u0435\u0433\u0438\u0439 (Machine mode), \u0447\u0442\u043e \u0445\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u043d\u043e \u0434\u043b\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u043d\u044b\u0445 \u044f\u0434\u0435\u0440. <\/p>\n<\/li>\n<li>\n<p>\u041a\u043e\u043d\u0432\u0435\u0439\u0435\u0440: 2\u20134 \u0441\u0442\u0430\u0434\u0438\u0438, \u0432 \u0437\u0430\u0432\u0438\u0441\u0438\u043c\u043e\u0441\u0442\u0438 \u043e\u0442 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438, \u0447\u0442\u043e \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0431\u0430\u043b\u0430\u043d\u0441\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u043c\u0435\u0436\u0434\u0443 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u044c\u044e \u0438 \u043f\u043b\u043e\u0449\u0430\u0434\u044c\u044e. <\/p>\n<\/li>\n<li>\n<p>\u0418\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u044b: 32-\u0431\u0438\u0442\u043d\u044b\u0439 \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 AXI4 \u0438\u043b\u0438 AHB-Lite \u0434\u043b\u044f \u0438\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u0438 \u0441 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0435\u0439 \u0438 \u043f\u0430\u043c\u044f\u0442\u044c\u044e.<\/p>\n<\/li>\n<li>\n<p>\u0418\u043d\u0442\u0435\u0433\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0440\u0443\u0435\u043c\u044b\u0439 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 (\u0434\u043e 16 \u043b\u0438\u043d\u0438\u0439 IRQ); <\/p>\n<\/li>\n<li>\n<p>\u041e\u0442\u043b\u0430\u0434\u043e\u0447\u043d\u0430\u044f \u043f\u043e\u0434\u0441\u0438\u0441\u0442\u0435\u043c\u0430 \u0441 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u043c JTAG; <\/p>\n<\/li>\n<li>\n<p>\u041e\u043f\u0446\u0438\u043e\u043d\u0430\u043b\u044c\u043d\u0430\u044f \u0442\u0435\u0441\u043d\u043e \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u0430\u044f \u043f\u0430\u043c\u044f\u0442\u044c (TCM) \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0434\u043e\u0441\u0442\u0443\u043f\u0430 \u043a \u043a\u0440\u0438\u0442\u0438\u0447\u043d\u044b\u043c \u0434\u0430\u043d\u043d\u044b\u043c.<\/p>\n<\/li>\n<li>\n<p>\u042f\u0437\u044b\u043a \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f: \u043d\u0430\u043f\u0438\u0441\u0430\u043d \u043d\u0430 SystemVerilog, \u0447\u0442\u043e \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0438\u0432\u0430\u0435\u0442 \u0445\u043e\u0440\u043e\u0448\u0443\u044e \u043f\u0435\u0440\u0435\u043d\u043e\u0441\u0438\u043c\u043e\u0441\u0442\u044c \u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0443 \u0432 \u0441\u043e\u0432\u0440\u0435\u043c\u0435\u043d\u043d\u044b\u0445 EDA-\u0441\u0440\u0435\u0434\u0430\u0445. <\/p>\n<\/li>\n<li>\n<p>\u041e\u043f\u0442\u0438\u043c\u0438\u0437\u0430\u0446\u0438\u044f: \u044f\u0434\u0440\u043e \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043e \u043f\u043e \u043f\u043b\u043e\u0449\u0430\u0434\u0438 \u0438 \u044d\u043d\u0435\u0440\u0433\u043e\u043f\u043e\u0442\u0440\u0435\u0431\u043b\u0435\u043d\u0438\u044e, \u043f\u043e\u0434\u0445\u043e\u0434\u0438\u0442 \u0434\u043b\u044f MCU-\u043a\u043b\u0430\u0441\u0441\u0430 \u0438 \u0432\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c\u044b\u0445 \u0440\u0435\u0448\u0435\u043d\u0438\u0439. <\/p>\n<\/li>\n<li>\n<p>\u0413\u0438\u0431\u043a\u0430\u044f \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f: \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b \u0442\u0440\u0438 \u043f\u0440\u0435\u0434\u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0451\u043d\u043d\u044b\u0435 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 (MAX, BASE, MIN), \u0430 \u0442\u0430\u043a\u0436\u0435 \u043c\u043d\u043e\u0436\u0435\u0441\u0442\u0432\u043e \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u0432 \u0434\u043b\u044f \u0442\u043e\u043d\u043a\u043e\u0439 \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0438 \u043f\u043e\u0434 \u043a\u043e\u043d\u043a\u0440\u0435\u0442\u043d\u044b\u0435 \u0437\u0430\u0434\u0430\u0447\u0438. <\/p>\n<\/li>\n<li>\n<p>\u0412\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f \u0438 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f: \u043f\u0440\u043e\u0435\u043a\u0442 \u0441\u043e\u043f\u0440\u043e\u0432\u043e\u0436\u0434\u0430\u0435\u0442\u0441\u044f \u043e\u0431\u0448\u0438\u0440\u043d\u043e\u0439 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u0435\u0439, \u0442\u0435\u0441\u0442\u043e\u0432\u044b\u043c\u0438 \u043d\u0430\u0431\u043e\u0440\u0430\u043c\u0438 (\u0432\u043a\u043b\u044e\u0447\u0430\u044f \u0442\u0435\u0441\u0442\u044b \u043d\u0430 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u0435 RISC-V ISA, Dhrystone, CoreMark), \u0430 \u0442\u0430\u043a\u0436\u0435 \u043f\u0440\u0438\u043c\u0435\u0440\u0430\u043c\u0438 \u0434\u043b\u044f \u0431\u044b\u0441\u0442\u0440\u043e\u0433\u043e \u0441\u0442\u0430\u0440\u0442\u0430. <\/p>\n<\/li>\n<li>\n<p>\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u043e\u0432 \u0438 \u043f\u043b\u0430\u0442\u0444\u043e\u0440\u043c: \u0441\u043e\u0432\u043c\u0435\u0441\u0442\u0438\u043c \u0441 \u043e\u0441\u043d\u043e\u0432\u043d\u044b\u043c\u0438 \u043f\u0440\u043e\u043c\u044b\u0448\u043b\u0435\u043d\u043d\u044b\u043c\u0438 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430\u043c\u0438 (Verilator, ModelSim, VCS, NCSim), <\/p>\n<\/li>\n<li>\n<p>\u041f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u0441\u0431\u043e\u0440\u043a\u0430 \u0438 \u0437\u0430\u043f\u0443\u0441\u043a \u043d\u0430 \u043f\u043e\u043f\u0443\u043b\u044f\u0440\u043d\u044b\u0445 \u043e\u0442\u043b\u0430\u0434\u043e\u0447\u043d\u044b\u0445 \u043f\u043b\u0430\u0442\u0430\u0445 (Arty, Nexys 4 DDR, DE10-Lite \u0438 \u0434\u0440.). <\/p>\n<\/li>\n<li>\n<p>\u042d\u043a\u043e\u0441\u0438\u0441\u0442\u0435\u043c\u0430: \u043a \u044f\u0434\u0440\u0443 \u043f\u0440\u0438\u043b\u0430\u0433\u0430\u0435\u0442\u0441\u044f SDK \u0441 \u0437\u0430\u0433\u0440\u0443\u0437\u0447\u0438\u043a\u043e\u043c, \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u043e\u0439 Zephyr RTOS, \u043f\u0440\u0438\u043c\u0435\u0440\u0430\u043c\u0438 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u043d\u043e\u0433\u043e \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0435\u043d\u0438\u044f \u0438 \u0440\u0443\u043a\u043e\u0432\u043e\u0434\u0441\u0442\u0432\u0430\u043c\u0438 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044f. SCR1 \u2014 \u043e\u0434\u043d\u043e \u0438\u0437 \u0441\u0430\u043c\u044b\u0445 \u043f\u043e\u043f\u0443\u043b\u044f\u0440\u043d\u044b\u0445 \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0445 \u044f\u0434\u0435\u0440 RISC-V \u0434\u043b\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u043e\u0432, \u0448\u0438\u0440\u043e\u043a\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c\u043e\u0435 \u043a\u0430\u043a \u0432 \u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0445, \u0442\u0430\u043a \u0438 \u0432 \u043a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0445 \u043f\u0440\u043e\u0435\u043a\u0442\u0430\u0445. <\/p>\n<\/li>\n<\/ul>\n<p>\u0420\u043e\u0441\u0441\u0438\u0439\u0441\u043a\u0438\u0439 RISC-V \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 \u0410\u043c\u0443\u0440 \u043a\u0430\u0436\u0435\u0442\u0441\u044f \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442 \u043e\u0447\u0435\u043d\u044c \u043f\u043e\u0445\u043e\u0436\u0435\u0435 \u044f\u0434\u0440\u043e, \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e \u044d\u0442\u043e \u0436\u0435 \u0441\u0430\u043c\u043e\u0435 (\u043d\u043e \u044d\u0442\u043e \u043d\u0435 \u0442\u043e\u0447\u043d\u043e).<\/p>\n<p>\u0421\u0432\u043e\u044e SOC \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 SCR1 \u044f \u0442\u0430\u043a \u0436\u0435 \u0434\u0435\u043b\u0430\u044e \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0439. \u0412 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0435 \u0443\u0436\u0435 \u0435\u0441\u0442\u044c \u0432\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u0430\u044f TCM (Tightly Coupled Memory) \u043f\u0430\u043c\u044f\u0442\u044c. \u0421 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u043a\u0430\u0441\u0442\u043e\u043c\u043d\u043e\u0439 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u044f \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u044e \u0435\u0451 \u0440\u0430\u0437\u043c\u0435\u0440 \u0432 32\u041a \u0438 \u0440\u0430\u0437\u043c\u0435\u0449\u0430\u044e \u0435\u0451 \u043f\u043e \u0430\u0434\u0440\u0435\u0441\u0443 \u043d\u043e\u043b\u044c. \u041c\u043e\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 \u0442\u0430\u043a \u0436\u0435 \u0431\u0443\u0434\u0435\u0442 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u0430\u0442\u044c \u0441 \u0430\u0434\u0440\u0435\u0441\u0430 \u043d\u043e\u043b\u044c \u043f\u0440\u044f\u043c\u043e \u0432 TCM. \u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u044f \u043d\u0435 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e. \u041d\u0430 \u0432\u043d\u0435\u0448\u043d\u0435\u0439 \u0448\u0438\u043d\u0435 \u0441\u0442\u0430\u0432\u043b\u044e \u043f\u043e \u0442\u0435\u043c \u0436\u0435 \u0430\u0434\u0440\u0435\u0441\u0430\u043c \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u043f\u043e\u0440\u0442, \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0441\u0435\u043c\u0438-\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u043e\u0433\u043e \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0430 \u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u043e\u0441\u0442\u0430\u043d\u043e\u0432\u0430 \u043f\u0440\u0438 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/24b\/156\/280\/24b1562809ae6ee4f119f0619bab796d.png\" alt=\"\u041c\u043e\u044f scr1 SOC\" title=\"\u041c\u043e\u044f scr1 SOC\" width=\"551\" height=\"600\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/24b\/156\/280\/24b1562809ae6ee4f119f0619bab796d.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/24b\/156\/280\/24b1562809ae6ee4f119f0619bab796d.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>\u041c\u043e\u044f scr1 SOC<\/figcaption><\/div>\n<\/figure>\n<p>\u0422\u0430\u043a\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c, \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043d\u043e \u043e\u0431\u0435 \u043f\u0440\u043e\u0435\u043a\u0442\u0438\u0440\u0443\u0435\u043c\u044b\u0435 \u043c\u043d\u043e\u044e SOC \u0431\u0443\u0434\u0443\u0442 \u0438\u0434\u0435\u043d\u0442\u0438\u0447\u043d\u044b\u043c\u0438:<\/p>\n<pre><code>\/\/ 8K 32bit words = 32Kbytes memory localparam MEM_SIZE = (1024*32); \/\/at address zero localparam SERIAL_PORT_ADDR = 32\u2019h1000_0000; localparam SEG7_PORT_ADDR = 32\u2019h1000_0004; localparam SIMSTOP_PORT_ADDR = 32\u2019h1000_1000;<\/code><div class=\"code-explainer\"><a href=\"https:\/\/sourcecraft.dev\/\" class=\"tm-button code-explainer__link\" style=\"visibility: hidden;\"><img style=\"width:87px;height:14px;object-fit:cover;object-position:left;\"\/><\/a><\/div><\/pre>\n<h2>\u041a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u0435\u043c \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0443 Dhrystone<\/h2>\n<p>\u0421\u043a\u043b\u043e\u043d\u0438\u0440\u0443\u0439\u0442\u0435 \u043c\u043e\u0439 \u043f\u0440\u043e\u0435\u043a\u0442 \u0441 github \u0432\u043c\u0435\u0441\u0442\u0435 \u0441 \u0441\u0443\u0431\u043c\u043e\u0434\u0443\u043b\u044f\u043c\u0438:<\/p>\n<blockquote>\n<p>git clone &#8212;recurse-submodules <a href=\"https:\/\/github.com\/marsohod4you\/riscv-compare.git\" rel=\"noopener noreferrer nofollow\">https:\/\/github.com\/marsohod4you\/riscv-compare.git<\/a><\/p>\n<\/blockquote>\n<p>\u041f\u0435\u0440\u0435\u0439\u0434\u0438\u0442\u0435 \u0432 \u0434\u0438\u0440\u0435\u043a\u0442\u043e\u0440\u0438\u044e \u0421\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430:<\/p>\n<blockquote>\n<p>cd riscv-compare\/dhrystone-fw\/<\/p>\n<\/blockquote>\n<p>\u0412\u043e\u0437\u043c\u043e\u0436\u043d\u043e \u0432\u0430\u043c \u043f\u043e\u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f \u0438\u0441\u043f\u0440\u0430\u0432\u0438\u0442\u044c \u0432 \u0441\u043a\u0440\u0438\u043f\u0442\u0435 build.sh \u0441\u0442\u0440\u043e\u043a\u0443 export PATH=$PATH: \u0438 \u0434\u043e\u0431\u0430\u0432\u0438\u0442\u044c \u0442\u0443\u0434\u0430 \u0438\u043c\u0435\u043d\u043d\u043e \u0432\u0430\u0448\u0438 \u043f\u0443\u0442\u0438 \u043a \u0442\u0443\u043b\u0447\u0435\u0439\u043d\u0443 risc-v \u0438 \u043a \u043f\u0438\u0442\u043e\u043d\u0443. \u041d\u0430\u043f\u043e\u043c\u043d\u044e, \u0447\u0442\u043e \u044f \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e \u0442\u0443\u043b\u0447\u0435\u0439\u043d \u0432\u0437\u044f\u0442\u044b\u0439 \u0432\u043e\u0442 \u0437\u0434\u0435\u0441\u044c: <a href=\"https:\/\/syntacore.com\/tools\/development-tools\" rel=\"noopener noreferrer nofollow\">https:\/\/syntacore.com\/tools\/development-tools<\/a><\/p>\n<p>\u0417\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u0435 \u0441\u043a\u0440\u0438\u043f\u0442 build.sh \u0441 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u043c EC \u0438\u043b\u0438 IM. \u042d\u0442\u0438 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u044b \u043a\u0430\u043a \u0440\u0430\u0437 \u0431\u0443\u0434\u0443\u0442 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u044f\u0442\u044c \u043a\u0430\u043a\u043e\u0439 \u043a\u043e\u0434 \u0433\u0435\u043d\u0435\u0440\u0438\u0440\u043e\u0432\u0430\u0442\u044c. EC \u044d\u0442\u043e \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0441 \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0435\u0439, embedded, \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440 gcc \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0442\u043e\u043b\u044c\u043a\u043e 16 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432, \u043d\u0435 \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043e\u043f\u0435\u0440\u0430\u0446\u0438\u0438 \u0443\u043c\u043d\u043e\u0436\u0435\u043d\u0438\u044f, \u043d\u043e \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0441\u0436\u0430\u0442\u044b\u0439 \u043a\u043e\u0434. \u0421\u0436\u0430\u0442\u044b\u0439 \u043a\u043e\u0434 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043a\u043e\u0440\u043e\u0442\u043a\u0438\u0435 16\u0442\u0438 \u0431\u0438\u0442\u043d\u044b\u0435 \u043a\u043e\u043c\u0430\u043d\u0434\u044b \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0435\u0441\u043b\u0438 \u044d\u0442\u043e \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e. \u042d\u0442\u043e \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u044d\u043a\u043e\u043d\u043e\u043c\u0438\u0442\u044c \u043c\u0435\u0441\u0442\u043e \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b. \u041f\u0440\u0438 \u044d\u0442\u043e\u043c 32\u0445 \u0431\u0438\u0442\u043d\u044b\u0435 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 \u043a\u043e\u043d\u0435\u0447\u043d\u043e \u0432\u0441\u0451 \u0435\u0449\u0435 \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b.<\/p>\n<p>\u0415\u0441\u043b\u0438 \u0437\u0430\u0434\u0430\u0442\u044c \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440 IM, \u0442\u043e \u0441\u043a\u0440\u0438\u043f\u0442 \u0431\u0443\u0434\u0435\u0442 \u0433\u0435\u043d\u0435\u0440\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u043a\u043e\u0434 \u0441 \u0443\u0447\u0435\u0442\u043e\u043c \u043d\u0430\u043b\u0438\u0447\u0438\u044f 32\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044f \u043a\u043e\u043c\u0430\u043d\u0434\u044b \u0443\u043c\u043d\u043e\u0436\u0435\u043d\u0438\u044f \u0435\u0441\u043b\u0438 \u043d\u0443\u0436\u043d\u043e.<\/p>\n<p>\u041a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u044e \u0441\u043a\u0440\u0438\u043f\u0442\u043e\u043c:<\/p>\n<blockquote>\n<p>.\/build.sh IM<\/p>\n<\/blockquote>\n<blockquote>\n<p>.\/build.sh EC<\/p>\n<\/blockquote>\n<p>\u041f\u043e\u0441\u043b\u0435 \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0446\u0438\u0438 \u043f\u043e\u044f\u0432\u044f\u0442\u0441\u044f \u043d\u043e\u0432\u044b\u0435 \u0434\u0438\u0440\u0435\u043a\u0442\u043e\u0440\u0438\u0438 riscv-compare\/dhrystone\/done_ec \u0438 riscv-compare\/dhrystone\/done_im. \u0412 \u043d\u0438\u0445 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0438\u0440\u0443\u044e\u0449\u0438\u0435 \u0444\u0430\u0439\u043b\u044b \u0438 \u0432\u044b \u043c\u043e\u0436\u0435\u0442\u0435 \u043f\u043e\u0438\u0437\u0443\u0447\u0430\u0442\u044c \u0438\u0445. \u0412 \u0444\u0430\u0439\u043b\u0435 dhry.dump \u043d\u0430\u043f\u0440\u0438\u043c\u0435\u0440 \u043c\u043e\u0436\u043d\u043e \u043f\u043e\u0441\u043c\u043e\u0442\u0440\u0435\u0442\u044c \u0430\u0441\u0441\u0435\u043c\u0431\u043b\u0435\u0440\u043d\u044b\u0439 \u043a\u043e\u0434 \u043f\u043e\u043b\u0443\u0447\u0435\u043d\u043d\u044b\u0439 \u0432 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442\u0435 \u0441\u0431\u043e\u0440\u043a\u0438. \u041e\u0431\u0440\u0430\u0442\u0438\u0442\u0435 \u0432\u043d\u0438\u043c\u0430\u043d\u0438\u0435, \u0447\u0442\u043e \u0432 \u0444\u0430\u0439\u043b\u0435 riscv-compare\/dhrystone\/done_im\/dhry.dump \u0432\u044b \u043d\u0430\u0439\u0434\u0451\u0442\u0435 \u0433\u043e\u0440\u0430\u0437\u0434\u043e \u0431\u043e\u043b\u044c\u0448\u0435\u0435 \u0447\u0438\u0441\u043b\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c\u044b\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432. \u041a\u0440\u043e\u043c\u0435 \u0442\u043e\u0433\u043e, \u0442\u0430\u043c \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u0435 \u043a\u043e\u043c\u0430\u043d\u0434 \u0442\u0438\u043f\u0430 mulhu, \u0430 \u0432 EC \u0434\u0430\u043c\u043f\u0435 \u0432\u043c\u0435\u0441\u0442\u043e \u044d\u0442\u043e\u0433\u043e \u0432\u044b \u0432\u0441\u0442\u0440\u0435\u0442\u0438\u0442\u0435 \u0432\u044b\u0437\u043e\u0432 \u043f\u043e\u0434\u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c \u0442\u0438\u043f\u0430 jal &lt;__mulsi3&gt;.<\/p>\n<p>\u0424\u0430\u0439\u043b\u044b \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c\u044b\u0435 \u0434\u043b\u044f \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u0438 \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438 FPGA \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u044d\u0442\u043e \u043e\u0431\u044b\u0447\u043d\u043e *.hex. \u042d\u0442\u0438 \u0444\u0430\u0439\u043b\u044b \u0442\u0430\u043a \u0436\u0435 \u0441\u043e\u0437\u0434\u0430\u044e\u0442\u0441\u044f.<\/p>\n<p>\u042d\u0442\u043e\u0442 \u0436\u0435 \u0441\u043a\u0440\u0438\u043f\u0442 \u0441\u043a\u043e\u043f\u0438\u0440\u0443\u0435\u0442 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0438\u0440\u0443\u044e\u0449\u0438\u0435 \u0444\u0430\u0439\u043b\u044b \u043a\u0443\u0434\u0430 \u043d\u0443\u0436\u043d\u043e \u0438 \u0434\u043b\u044f \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u0438 \u0434\u043b\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u043e\u0432 Quartus Prime \u0434\u043b\u044f \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0446\u0438\u0438 FPGA \u043f\u0440\u043e\u0435\u043a\u0442\u043e\u0432.<\/p>\n<h2>\u0421\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u044f \u0440\u0430\u0431\u043e\u0442\u044b SOC \u0441 RISC-V \u044f\u0434\u0440\u0430\u043c\u0438. <\/h2>\n<p>\u0421\u0438\u043c\u0443\u043b\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u043f\u0440\u043e\u0435\u043a\u0442 picorv32 SOC \u043e\u0447\u0435\u043d\u044c \u043f\u0440\u043e\u0441\u0442\u043e \u0434\u0430\u0436\u0435 \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e Icarus Verilog &#8212; \u043d\u043e \u043e\u043d \u0434\u043e\u043b\u0436\u0435\u043d \u0431\u044b\u0442\u044c \u0437\u0430\u0440\u0430\u043d\u0435\u0435 \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d \u0443 \u0432\u0430\u0441. \u042d\u0442\u043e \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e \u043f\u043e\u0442\u043e\u043c\u0443, \u0447\u0442\u043e \u0432\u0441\u0451 \u044f\u0434\u0440\u043e \u043e\u043f\u0438\u0441\u0430\u043d\u043e \u043d\u0430 Verilog HDL. \u0418 \u0432\u0441\u0451 \u044f\u0434\u0440\u043e \u044d\u0442\u043e \u043e\u0434\u0438\u043d \u0444\u0430\u0439\u043b picorv32.v.<\/p>\n<p>\u041f\u0435\u0440\u0435\u0439\u0434\u0438\u0442\u0435 \u0432 \u043f\u0430\u043f\u043a\u0443 riscv-compare\/FPGA\/m3-picorv32\/sim \u0438 \u0437\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u0435 \u0441\u043a\u0440\u0438\u043f\u0442 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430 \u043e\u043f\u044f\u0442\u044c \u0436\u0435 \u0441 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u043c EC \u0438\u043b\u0438 IM:<\/p>\n<blockquote>\n<p>cd .\/riscv-compare\/FPGA\/m3-picorv32\/sim .\/simulate.sh IM<\/p>\n<\/blockquote>\n<p>\u042d\u0442\u043e\u0442 \u0441\u043a\u0440\u0438\u043f\u0442 \u0438 \u043a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u0435\u0442 \u0438 \u0441\u0438\u043c\u0443\u043b\u0438\u0440\u0443\u0435\u0442. \u0412 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442\u0435 \u0432\u044b \u0441\u043c\u043e\u0436\u0435\u0442\u0435 \u0443\u0432\u0438\u0434\u0435\u0442\u044c \u0432\u043e\u0442 \u0442\u0430\u043a\u043e\u0439 \u0432\u044b\u0432\u043e\u0434:<\/p>\n<pre><code>$ .\/simulate.sh IMSimulate for CPU with mul\/dev and 32 regsFirmware Boot File exists: dhry_im.hexSimulation with FW Boot File for CPU with MUL\/DIV instructions number of REGs=32Simulation Config for CPU with MUL\/DIV and number of REGs=32VCD info: dumpfile testbench.vcd opened for output.STARTDhrystone Benchmark, Version 2.1 (Language: C)Program compiled without 'register' attributeExecution starts, 500 runs through DhrystoneExecution endsFinal values of the variables used in the benchmark:Int_Glob:            5        should be:   5Bool_Glob:           1        should be:   1Ch_1_Glob:           A        should be:   ACh_2_Glob:           B        should be:   BArr_1_Glob[8]:       7        should be:   7Arr_2_Glob[8][7]:    510        should be:   Number_Of_Runs + 10Ptr_Glob-&gt;  Ptr_Comp:          12540        should be:   (implementation-dependent)  Discr:             0        should be:   0  Enum_Comp:         2        should be:   2  Int_Comp:          17        should be:   17  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING        should be:   DHRYSTONE PROGRAM, SOME STRINGNext_Ptr_Glob-&gt;  Ptr_Comp:          12540        should be:   (implementation-dependent), same as above  Discr:             0        should be:   0  Enum_Comp:         1        should be:   1  Int_Comp:          18        should be:   18  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING        should be:   DHRYSTONE PROGRAM, SOME STRINGInt_1_Loc:           5        should be:   5Int_2_Loc:           13        should be:   13Int_3_Loc:           7        should be:   7Enum_Loc:            1        should be:   1Str_1_Loc:           DHRYSTONE PROGRAM, 1'ST STRING        should be:   DHRYSTONE PROGRAM, 1'ST STRINGStr_2_Loc:           DHRYSTONE PROGRAM, 2'ND STRING        should be:   DHRYSTONE PROGRAM, 2'ND STRINGBeginTime 57844 EndTime 789033 UserTime 731189Number_Of_Runs= 500, HZ= 1000000Time: begin= 57844, end= 789033, diff= 731189Microseconds for one run through Dhrystone: 1462Dhrystones per Second:                      683Cycles_Per_Instruction: 5.623Seg4x7 register Written 00000683DONE..\/soc.v:135: $finish called at 963340000000 (1ps)<\/code><div class=\"code-explainer\"><a href=\"https:\/\/sourcecraft.dev\/\" class=\"tm-button code-explainer__link\" style=\"visibility: hidden;\"><img style=\"width:14px;height:14px;object-fit:cover;object-position:left;\"\/><\/a><\/div><\/pre>\n<p>\u0415\u0441\u043b\u0438 \u0435\u0441\u0442\u044c \u0436\u0435\u043b\u0430\u043d\u0438\u0435, \u043c\u043e\u0436\u043d\u043e \u0434\u0435\u0442\u0430\u043b\u044c\u043d\u043e \u0440\u0430\u0441\u0441\u043c\u043e\u0442\u0440\u0435\u0442\u044c \u0432\u0441\u0435 \u0441\u0438\u0433\u043d\u0430\u043b\u044b \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0435 \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e gtkwave \u0438 \u0441\u0433\u0435\u043d\u0435\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u043e\u0433\u043e testbench.vcd \u0444\u0430\u0439\u043b\u0430.<\/p>\n<p>\u0421\u0438\u043c\u0443\u043b\u0438\u0440\u043e\u0432\u0430\u0442\u044c scr1 \u043f\u0440\u043e\u0435\u043a\u0442 \u043d\u0435 \u0442\u0430\u043a \u043f\u0440\u043e\u0441\u0442\u043e. Scr1 \u043d\u0430\u043f\u0438\u0441\u0430\u043d \u043d\u0430 SystemVerilog \u0438 Icarus \u0435\u0433\u043e \u043f\u043e\u0447\u0442\u0438 \u043d\u0435 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442. \u0417\u0434\u0435\u0441\u044c \u043d\u0443\u0436\u0435\u043d Verilator. \u041f\u0440\u043e\u0449\u0435 \u0432\u0441\u0435\u0433\u043e \u0435\u0433\u043e \u043a\u043e\u043d\u0435\u0447\u043d\u043e \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u0438\u0442\u044c \u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0432 \u0441\u0440\u0435\u0434\u0435 Linux.<\/p>\n<p>\u042f \u0442\u0430\u043a \u0436\u0435 \u043f\u0440\u0438\u0433\u043e\u0442\u043e\u0432\u0438\u043b \u0441\u043a\u0440\u0438\u043f\u0442 \u0434\u043b\u044f \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438.<\/p>\n<p>\u041f\u0435\u0440\u0435\u0439\u0434\u0438\u0442\u0435 \u0432 \u0434\u0438\u0440\u0435\u043a\u0442\u043e\u0440\u0438\u044e riscv-compare\/FPGA\/m3-scr1\/sim \u0438 \u0437\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u0435 \u0441\u043a\u0440\u0438\u043f\u0442 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438<\/p>\n<blockquote>\n<p>cd .\/riscv-compare\/FPGA\/m3-scr1\/sim .\/simulate.sh IM<\/p>\n<\/blockquote>\n<p>\u0421\u043a\u0440\u0438\u043f\u0442 \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u043e \u0438 \u043a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u0435\u0442 \u0438 \u0441\u0438\u043c\u0443\u043b\u0438\u0440\u0443\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044f Verilator. \u0412\u044b\u0432\u043e\u0434 \u0441\u043a\u0440\u0438\u043f\u0442\u0430 \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0432\u043e\u0442 \u0442\u0430\u043a\u043e\u0439 \u0434\u043b\u0438\u043d\u043d\u044b\u0439 \u0442\u0435\u043a\u0441\u0442:<\/p>\n<details class=\"spoiler\">\n<summary>\u0421\u043a\u0440\u044b\u0442\u044b\u0439 \u0442\u0435\u043a\u0441\u0442<\/summary>\n<div class=\"spoiler__content\">\n<p>Simulate for CPU with mul\/dev and 32 regsFirmware Boot File exists: dhry32_im.hex****************************************************** Patching SCR1 project..                     ******************************************************Patching SCR1 project done..****************************************************** Compile with Verilator..                    ******************************************************rm: cannot remove &#8216;obj_dir&#8217;: Is a directory%Warning-TIMESCALEMOD: ..\/..\/m3-scr1\/max10.v:4:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)    4 | module max10(      |        ^~~~~                       ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:123:8: &#8230; Location of module with timescale  123 | module generic_fifo_dc_gray( rd_clk, wr_clk, rst, clr, din, we,      |        ^~~~~~~~~~~~~~~~~~~~                       &#8230; For warning description see <a href=\"https:\/\/verilator.org\/warn\/TIMESCALEMOD?v=5.037\" rel=\"noopener noreferrer nofollow\">https:\/\/verilator.org\/warn\/TIMESCALEMOD?v=5.037<\/a>                       &#8230; Use &#171;\/* verilator lint_off TIMESCALEMOD <em>\/&#187; and lint_on around source to disable this message.%Warning-TIMESCALEMOD: ..\/..\/common\/sserial.v:3:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)    3 | module sserial(      |        ^~~~~~~                       ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:123:8: &#8230; Location of module with timescale  123 | module generic_fifo_dc_gray( rd_clk, wr_clk, rst, clr, din, we,      |        ^~~~~~~~~~~~~~~~~~~~%Warning-TIMESCALEMOD: ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_dpram.v:99:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)   99 | module generic_dpram(      |        ^~~~~~~~~~~~~                       ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:123:8: &#8230; Location of module with timescale  123 | module generic_fifo_dc_gray( rd_clk, wr_clk, rst, clr, din, we,      |        ^~~~~~~~~~~~~~~~~~~~%Warning-TIMESCALEMOD: ..\/..\/..\/FPGA\/m3-scr1\/seg4x7.v:1:8: Timescale missing on this module as other modules have it (IEEE 1800-2023 3.14.2.3)    1 | module seg4x7(      |        ^~~~~~                       ..\/..\/m3-scr1\/max10.v:197:1: &#8230; note: In file included from &#8216;max10.v&#8217;                       ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:123:8: &#8230; Location of module with timescale  123 | module generic_fifo_dc_gray( rd_clk, wr_clk, rst, clr, din, we,      |        ^~~~~~~~~~~~~~~~~~~~%Warning-IMPLICIT: ..\/..\/m3-scr1\/max10.v:108:30: Signal definition not found, creating implicitly: &#8216;tdo&#8217;                                               : &#8230; Suggested alternative: &#8216;tdi&#8217;  108 |     .tdo                    (tdo                    ),      |                              ^~~                   &#8230; For warning description see <\/em><a href=\"https:\/\/verilator.org\/warn\/IMPLICIT?v=5.037\" rel=\"noopener noreferrer nofollow\"><em>https:\/\/verilator.org\/warn\/IMPLICIT?v=5.037<\/em><\/a><em>                   &#8230; Use &#171;\/<\/em> verilator lint_off IMPLICIT <em>\/&#187; and lint_on around source to disable this message.%Warning-IMPLICIT: ..\/..\/m3-scr1\/max10.v:109:30: Signal definition not found, creating implicitly: &#8216;tdo_en&#8217;  109 |     .tdo_en                 (tdo_en                 ),      |                              ^~~~~~%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_hdu.svh:21:25: Operator VAR &#8216;SCR1_HDU_DEBUGCSR_ADDR_SPAN&#8217; expects 32 bits on the Initial value, but Initial value&#8217;s VARREF &#8216;SCR1_CSR_ADDR_HDU_MSPAN&#8217; generates 12 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   21 | localparam int unsigned SCR1_HDU_DEBUGCSR_ADDR_SPAN      = SCR1_CSR_ADDR_HDU_MSPAN;      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:17:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;                      &#8230; For warning description see <\/em><a href=\"https:\/\/verilator.org\/warn\/WIDTHEXPAND?v=5.037\" rel=\"noopener noreferrer nofollow\"><em>https:\/\/verilator.org\/warn\/WIDTHEXPAND?v=5.037<\/em><\/a><em>                      &#8230; Use &#171;\/<\/em> verilator lint_off WIDTHEXPAND <em>\/&#187; and lint_on around source to disable this message.%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:70:41: Operator ADD expects 32 or 5 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_DBG_DMI_OP_WIDTH&#8217; generates 2 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;   70 | localparam    DMI_OP_HI   = DMI_OP_LO   + SCR1_DBG_DMI_OP_WIDTH   &#8212; 1;      |                                         ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_dm.svh:19:76: Operator ADD expects 6 bits on the LHS, but LHS&#8217;s VARREF &#8216;SCR1_DBG_DMI_OP_WIDTH&#8217; generates 2 bits.                                                                              : &#8230; note: In instance &#8216;max10&#8217;   19 | parameter SCR1_DBG_DMI_DR_DMI_ACCESS_WIDTH         = SCR1_DBG_DMI_OP_WIDTH +      |                                                                            ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:11:1: &#8230; note: In file included from &#8216;scr1_tapc_<\/em><a href=\"http:\/\/synchronizer.sv\" rel=\"noopener noreferrer nofollow\"><em>synchronizer.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_hdu.svh:123:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_HDU_DBGCSR_OFFS_DPC&#8217; generates 2 bits.                                                                                : &#8230; note: In instance &#8216;max10&#8217;  123 | localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DPC       = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DPC;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:17:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_hdu.svh:124:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_HDU_DBGCSR_OFFS_DSCRATCH0&#8217; generates 2 bits.                                                                                : &#8230; note: In instance &#8216;max10&#8217;  124 | localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH0 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH0;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:17:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:120:65: Operator SHIFTL expects 32 bits on the LHS, but LHS&#8217;s VARREF &#8216;SCR1_MISA_MXL_32&#8217; generates 2 bits.                                                                                : &#8230; note: In instance &#8216;max10&#8217;  120 | parameter bit [32-1:0]  SCR1_CSR_MISA       = (SCR1_MISA_MXL_32 &lt;&lt; (32-2))      |                                                                 ^~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:84:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_CISV&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   84 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CISV     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CISV );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:85:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_CICSR&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   85 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_CICSR    = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_CICSR);      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:86:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_IPR&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   86 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IPR      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IPR  );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:87:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_ISVR&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   87 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ISVR     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ISVR );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:88:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_EOI&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   88 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_EOI      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_EOI  );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:89:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_SOI&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   89 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_SOI      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_SOI  );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:90:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_IDX&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   90 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_IDX      = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_IDX  );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_csr.svh:91:96: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_IPIC_ICSR&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   91 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_IPIC_ICSR     = (SCR1_CSR_ADDR_IPIC_BASE + SCR1_IPIC_ICSR );      |                                                                                                ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_tracelog.sv:9:1: &#8230; note: In file included from &#8216;scr1_<\/em><a href=\"http:\/\/tracelog.sv\" rel=\"noopener noreferrer nofollow\"><em>tracelog.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_hdu.svh:122:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_HDU_DBGCSR_OFFS_DCSR&#8217; generates 2 bits.                                                                                : &#8230; note: In instance &#8216;max10&#8217;  122 | localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DCSR      = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DCSR;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:17:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_hdu.svh:125:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_HDU_DBGCSR_OFFS_DSCRATCH1&#8217; generates 2 bits.                                                                                : &#8230; note: In instance &#8216;max10&#8217;  125 | localparam bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_HDU_DBGCSR_ADDR_DSCRATCH1 = SCR1_CSR_ADDR_HDU_MBASE + SCR1_HDU_DBGCSR_OFFS_DSCRATCH1;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:17:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:36:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_CSR_ADDR_TDU_OFFS_TSELECT&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   36 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TSELECT       = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TSELECT;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:37:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_CSR_ADDR_TDU_OFFS_TDATA1&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   37 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA1        = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA1;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:38:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_CSR_ADDR_TDU_OFFS_TDATA2&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   38 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TDATA2        = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TDATA2;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:39:99: Operator ADD expects 12 bits on the RHS, but RHS&#8217;s VARREF &#8216;SCR1_CSR_ADDR_TDU_OFFS_TINFO&#8217; generates 3 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   39 | parameter bit [SCR1_CSR_ADDR_WIDTH-1:0] SCR1_CSR_ADDR_TDU_TINFO         = SCR1_CSR_ADDR_TDU_MBASE + SCR1_CSR_ADDR_TDU_OFFS_TINFO;      |                                                                                                   ^                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:72:25: Operator VAR &#8216;SCR1_TDU_MCONTROL_TYPE_VAL&#8217; expects 4 bits on the Initial value, but Initial value&#8217;s CONST &#8216;2&#8217;h2&#8242; generates 2 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   72 |                         SCR1_TDU_MCONTROL_TYPE_VAL           = 2&#8217;d2;      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:78:25: Operator VAR &#8216;SCR1_TDU_MCONTROL_MASKMAX_VAL&#8217; expects 6 bits on the Initial value, but Initial value&#8217;s CONST &#8216;1&#8217;h0&#8242; generates 1 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   78 |                         SCR1_TDU_MCONTROL_MASKMAX_VAL        = 1&#8217;b0;      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:98:25: Operator VAR &#8216;SCR1_TDU_ICOUNT_TYPE_VAL&#8217; expects 4 bits on the Initial value, but Initial value&#8217;s CONST &#8216;2&#8217;h3&#8242; generates 2 bits.                                                                               : &#8230; note: In instance &#8216;max10&#8217;   98 |                         SCR1_TDU_ICOUNT_TYPE_VAL             = 2&#8217;d3;      |                         ^~~~~~~~~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/includes\/scr1_tdu.svh:101:25: Operator VAR &#8216;SCR1_TDU_ICOUNT_RESERVEDB_VAL&#8217; expects 2 bits on the Initial value, but Initial value&#8217;s CONST &#8216;1&#8217;h0&#8242; generates 1 bits.                                                                                : &#8230; note: In instance &#8216;max10&#8217;  101 |                         SCR1_TDU_ICOUNT_RESERVEDB_VAL        = 1&#8217;b0;      |                         ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_top.sv:21:1: &#8230; note: In file included from &#8216;scr1_pipe_<\/em><a href=\"http:\/\/top.sv\" rel=\"noopener noreferrer nofollow\"><em>top.sv<\/em><\/a><em>&#8216;%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:409:30: Operator COND expects 64 bits on the Conditional False, but Conditional False&#8217;s SIGNED generates 1 bits.                                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_exu.i_ialu&#8217;  409 | assign mul_res = mdu_cmd_mul ? mul_op1 <\/em> mul_op2                           : $signed(&#8216;0);      |                              ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:467:23: Operator COND expects 32 bits on the Conditional True, but Conditional True&#8217;s REPLICATE generates 2 bits.                                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_exu.i_ialu&#8217;  467 |                       ? {&#8216;0, div_quo_bit}      |                       ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:506:40: Operator COND expects 33 bits on the Conditional True, but Conditional True&#8217;s SIGNED generates 2 bits.                                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_exu.i_ialu&#8217;  506 |                         : mdu_fsm_idle ? $signed({div_op1_is_neg, exu2ialu_main_op1_i[32-1]})      |                                        ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:596:58: Operator XOR expects 32 bits on the LHS, but LHS&#8217;s SEL generates 1 bits.                                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_exu.i_ialu&#8217;  596 |             ialu2exu_main_res_o = 32&#8242;(~(main_sum_flags.s ^ main_sum_flags.o));      |                                                          ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:596:58: Operator XOR expects 32 bits on the RHS, but RHS&#8217;s SEL generates 1 bits.                                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_exu.i_ialu&#8217;  596 |             ialu2exu_main_res_o = 32&#8242;(~(main_sum_flags.s ^ main_sum_flags.o));      |                                                          ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_ipic.sv:396:38: Operator COND expects 5 bits on the Conditional False, but Conditional False&#8217;s CONST &#8216;1&#8217;h0&#8242; generates 1 bits.                                                                                     : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ipic&#8217;  396 |                       : ipic_eoi_req ? irq_eoi_req_vd ? {1&#8217;b0, irq_eoi_req_idx}      |                                      ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_exu.sv:939:26: Operator COND expects 32 bits on the Conditional False, but Conditional False&#8217;s REPLICATE generates 6 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_exu&#8217;  939 |                          ? mprf2exu_rs1_data_i      |                          ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_hdu.sv:550:43: Operator EQ expects 32 bits on the LHS, but LHS&#8217;s VARREF &#8216;pbuf_addr_ff&#8217; generates 3 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_hdu&#8217;  550 | assign pbuf_addr_end      = (pbuf_addr_ff == (SCR1_HDU_PBUF_ADDR_SPAN-1));      |                                           ^~%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_hdu.sv:711:24: Operator ASSIGNDLY expects 3 bits on the Assign RHS, but Assign RHS&#8217;s CONST &#8216;1&#8217;h0&#8242; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_hdu&#8217;  711 |         csr_dcsr_cause &lt;= 1&#8217;b0;      |                        ^~%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:450:79: Operator SUB expects 32 bits on the LHS, but LHS&#8217;s VARREF &#8216;q_wptr&#8217; generates 3 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  450 | assign q_free_h_next    = SCR1_IFU_Q_FREE_H_W'(SCR1_IFU_Q_SIZE_HALF &#8212; (q_wptr &#8212; q_rptr_next));      |                                                                               ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:450:79: Operator SUB expects 32 bits on the RHS, but RHS&#8217;s VARREF &#8216;q_rptr_next&#8217; generates 3 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  450 | assign q_free_h_next    = SCR1_IFU_Q_FREE_H_W'(SCR1_IFU_Q_SIZE_HALF &#8212; (q_wptr &#8212; q_rptr_next));      |                                                                               ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:531:89: Operator ADD expects 4 bits on the RHS, but RHS&#8217;s VARREF &#8216;imem_handshake_done&#8217; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  531 |                                              : {imem_addr_ff[32-1:6], imem_addr_ff[5:2] + imem_handshake_done};      |                                                                                         ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:529:89: Operator ADD expects 30 bits on the RHS, but RHS&#8217;s VARREF &#8216;imem_handshake_done&#8217; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  529 | assign imem_addr_next = exu2ifu_pc_new_req_i ? exu2ifu_pc_new_i[32-1:2]                 + imem_handshake_done      |                                                                                         ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:530:97: Operator ADD expects 30 bits on the RHS, but RHS&#8217;s VARREF &#8216;imem_handshake_done&#8217; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  530 |                       : &amp;imem_addr_ff[5:2]   ? imem_addr_ff                                     + imem_handshake_done      |                                                                                                 ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:553:74: Operator SUB expects 3 bits on the LHS, but LHS&#8217;s VARREF &#8216;imem_handshake_done&#8217; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  553 | assign imem_pnd_txns_cnt_next = imem_pnd_txns_cnt + (imem_handshake_done &#8212; imem_resp_received);      |                                                                          ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:553:74: Operator SUB expects 3 bits on the RHS, but RHS&#8217;s VARREF &#8216;imem_resp_received&#8217; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  553 | assign imem_pnd_txns_cnt_next = imem_pnd_txns_cnt + (imem_handshake_done &#8212; imem_resp_received);      |                                                                          ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:581:87: Operator SUB expects 3 bits on the RHS, but RHS&#8217;s VARREF &#8216;imem_handshake_done&#8217; generates 1 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  581 | assign imem_resp_discard_cnt_next = exu2ifu_pc_new_req_i     ? imem_pnd_txns_cnt_next &#8212; imem_handshake_done      |                                                                                       ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_tdu.sv:173:33: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS&#8217;s REPLICATE generates 4 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_tdu&#8217;  173 |                 tdu2csr_rdata_o = {&#8216;0, csr_tselect_ff};      |                                 ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_tdu.sv:226:40: Bit extraction of var[31:0] requires 5 bit index, not 4 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_tdu&#8217;  226 |                         tdu2csr_rdata_o[SCR1_TDU_MCONTROL_TYPE_VAL] = 1&#8217;b1;      |                                        ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_tdu.sv:231:36: Bit extraction of var[31:0] requires 5 bit index, not 4 bits.                                                                                         : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_tdu&#8217;  231 |                     tdu2csr_rdata_o[SCR1_TDU_ICOUNT_TYPE_VAL] = 1&#8217;b1;      |                                    ^%Warning-WIDTHEXPAND: ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_dpram.v:334:16: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;start&#8217; generates 4 bits.                                                                                   : &#8230; note: In instance &#8216;max10.u_sserial.u_serial_fifo.u0&#8217;  334 |       for (rnum=start;rnum&lt;=finish;rnum=rnum+1)      |                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:465:64: Operator ASSIGN expects 9 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;DMSTATUS_RESERVEDC&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  465 |                            SCR1_DBG_DMSTATUS_RESERVEDC_LO]     = DMSTATUS_RESERVEDC;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:468:64: Operator ASSIGN expects 2 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;DMSTATUS_RESERVEDB&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  468 |                            SCR1_DBG_DMSTATUS_RESERVEDB_LO]     = DMSTATUS_RESERVEDB;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:486:64: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;DMSTATUS_VERSION&#8217; generates 2 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  486 |                            SCR1_DBG_DMSTATUS_VERSION_LO]       = DMSTATUS_VERSION;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:497:64: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;DMCONTROL_HARTSELLO&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  497 |                            SCR1_DBG_DMCONTROL_HARTSELLO_LO]    = DMCONTROL_HARTSELLO;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:499:64: Operator ASSIGN expects 10 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;DMCONTROL_HARTSELHI&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  499 |                            SCR1_DBG_DMCONTROL_HARTSELHI_LO]    = DMCONTROL_HARTSELHI;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:501:64: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;DMCONTROL_RESERVEDA&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  501 |                            SCR1_DBG_DMCONTROL_RESERVEDA_LO]    = DMCONTROL_RESERVEDA;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:508:64: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;ABSTRACTCS_RESERVEDD&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  508 |                            SCR1_DBG_ABSTRACTCS_RESERVEDD_LO]   = ABSTRACTCS_RESERVEDD;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:512:64: Operator ASSIGN expects 11 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;ABSTRACTCS_RESERVEDC&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  512 |                            SCR1_DBG_ABSTRACTCS_RESERVEDC_LO]   = ABSTRACTCS_RESERVEDC;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:518:64: Operator ASSIGN expects 4 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;ABSTRACTCS_RESERVEDA&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  518 |                            SCR1_DBG_ABSTRACTCS_RESERVEDA_LO]   = ABSTRACTCS_RESERVEDA;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:525:64: Operator ASSIGN expects 8 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;HARTINFO_RESERVEDB&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  525 |                            SCR1_DBG_HARTINFO_RESERVEDB_LO]     = HARTINFO_RESERVEDB;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:529:64: Operator ASSIGN expects 3 bits on the Assign RHS, but Assign RHS&#8217;s VARREF &#8216;HARTINFO_RESERVEDA&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  529 |                            SCR1_DBG_HARTINFO_RESERVEDA_LO]     = HARTINFO_RESERVEDA;      |                                                                ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:756:49: Operator EQ expects 8 bits on the RHS, but RHS&#8217;s VARREF &#8216;ABS_CMD_HARTREG&#8217; generates 1 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  756 | assign abs_cmd_hartreg_vd       = (abs_cmd_type == ABS_CMD_HARTREG) &amp; abs_cmd_regvalid;      |                                                 ^~%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:757:49: Operator EQ expects 8 bits on the RHS, but RHS&#8217;s VARREF &#8216;ABS_CMD_HARTMEM&#8217; generates 2 bits.                                                                          : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217;  757 | assign abs_cmd_hartmem_vd       = (abs_cmd_type == ABS_CMD_HARTMEM) &amp; abs_cmd_memvalid;      |                                                 ^~%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:1135:40: Operator AND expects 3 bits on the LHS, but LHS&#8217;s CASTWRAP generates 1 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dm&#8217; 1135 |                                        &amp; (~dmi2dm_wdata_i[SCR1_DBG_ABSTRACTCS_CMDERR_HI:      |                                        ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:101:47: Operator EQ expects 2 bits on the RHS, but RHS&#8217;s CONST &#8216;1&#8217;h1&#8242; generates 1 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  101 | assign tapc_dtmcs_sel = (tapcsync2dmi_ch_id_i == 1&#8217;d1);      |                                               ^~%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:108:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  108 |         tap_dr_rdata[DTMCS_RESERVEDB_HI:DTMCS_RESERVEDB_LO] = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:109:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  109 |         tap_dr_rdata[DTMCS_DMIHARDRESET]                    = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:110:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  110 |         tap_dr_rdata[DTMCS_DMIRESET]                        = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:111:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  111 |         tap_dr_rdata[DTMCS_RESERVEDA]                       = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:112:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  112 |         tap_dr_rdata[DTMCS_IDLE_HI:DTMCS_IDLE_LO]           = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:113:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  113 |         tap_dr_rdata[DTMCS_DMISTAT_HI:DTMCS_DMISTAT_LO]     = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:114:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  114 |         tap_dr_rdata[DTMCS_ABITS_HI  :DTMCS_ABITS_LO]       = SCR1_DBG_DMI_ADDR_WIDTH;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:115:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  115 |         tap_dr_rdata[DTMCS_VERSION_LO]                      = 1&#8217;b1;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:119:21: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  119 |         tap_dr_rdata[DMI_OP_HI  :DMI_OP_LO]                 = &#8216;b0;      |                     ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:156:28: Operator ASSIGN expects 7 bits on the Assign RHS, but Assign RHS&#8217;s CONST &#8216;1&#8217;h0&#8242; generates 1 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  156 |     dmi2dm_addr_o          = 1&#8217;b0;      |                            ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:157:28: Operator ASSIGN expects 32 bits on the Assign RHS, but Assign RHS&#8217;s CONST &#8216;1&#8217;h0&#8242; generates 1 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  157 |     dmi2dm_wdata_o         = 1&#8217;b0;      |                            ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:160:35: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  160 |         dmi2dm_req_o   = tap_dr_ff[DMI_OP_HI  :DMI_OP_LO] != 2&#8217;b00;      |                                   ^%Warning-WIDTHEXPAND: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dmi.sv:161:35: Bit extraction of var[40:0] requires 6 bit index, not 5 bits.                                                                           : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_dmi&#8217;  161 |         dmi2dm_wr_o    = tap_dr_ff[DMI_OP_HI  :DMI_OP_LO] == 2&#8217;b10;      |                                   ^%Warning-WIDTHTRUNC: ..\/..\/common\/sserial.v:57:4: Logical operator IF expects 1 bit on the If, but If&#8217;s VARREF &#8216;serial_cnt&#8217; generates 4 bits.                                                : &#8230; note: In instance &#8216;max10.u_sserial&#8217;   57 |    if(serial_cnt)      |    ^~                     &#8230; For warning description see <a href=\"https:\/\/verilator.org\/warn\/WIDTHTRUNC?v=5.037\" rel=\"noopener noreferrer nofollow\">https:\/\/verilator.org\/warn\/WIDTHTRUNC?v=5.037<\/a>                     &#8230; Use &#171;\/* verilator lint_off WIDTHTRUNC <em>\/&#187; and lint_on around source to disable this message.%Warning-UNSIGNED: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_idu.sv:928:30: Comparison is constant due to unsigned arithmetic                                                                                      : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_idu&#8217;  928 |     ((idu2exu_cmd_o.ialu_cmd &gt;= SCR1_IALU_CMD_NONE) &amp;      |                              ^~                   &#8230; For warning description see <\/em><a href=\"https:\/\/verilator.org\/warn\/UNSIGNED?v=5.037\" rel=\"noopener noreferrer nofollow\"><em>https:\/\/verilator.org\/warn\/UNSIGNED?v=5.037<\/em><\/a><em>                   &#8230; Use &#171;\/<\/em> verilator lint_off UNSIGNED <em>\/&#187; and lint_on around source to disable this message.%Warning-UNSIGNED: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:788:28: Comparison is constant due to unsigned arithmetic                                                                                      : &#8230; note: In instance &#8216;max10.i_top.i_core_top.i_pipe_top.i_pipe_ifu&#8217;  788 |     (imem_resp_discard_cnt &gt;= 0) &amp; (imem_resp_discard_cnt &lt;= imem_pnd_txns_cnt)      |                            ^~%Warning-CASEINCOMPLETE: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ifu.sv:426:9: Case values incompletely covered (example pattern 0x0)  426 |         case (q_wr_size)      |         ^~~~                         &#8230; For warning description see <\/em><a href=\"https:\/\/verilator.org\/warn\/CASEINCOMPLETE?v=5.037\" rel=\"noopener noreferrer nofollow\"><em>https:\/\/verilator.org\/warn\/CASEINCOMPLETE?v=5.037<\/em><\/a><em>                         &#8230; Use &#171;\/<\/em> verilator lint_off CASEINCOMPLETE <em>\/&#187; and lint_on around source to disable this message.%Warning-CASEINCOMPLETE: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:352:9: Case values incompletely covered (example pattern 0x3)  352 |         case (mdu_fsm_ff)      |         ^~~~%Warning-CASEINCOMPLETE: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/pipeline\/scr1_pipe_ialu.sv:634:13: Case values incompletely covered (example pattern 0x3)  634 |             case (mdu_fsm_ff)      |             ^~~~%Warning-CASEINCOMPLETE: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_dm.sv:821:5: Case values incompletely covered (example pattern 0xd)  821 |     case (abs_fsm_ff)      |     ^~~~%Warning-MULTIDRIVEN: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:60:17: Signal has multiple driving blocks with different clocking: &#8216;max10.i_top.i_core_top.i_tapc_synchronizer.dmi_ch_capture_sync&#8217;                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:126:9: &#8230; Location of first driving block  126 |         dmi_ch_capture_sync[2:1] &lt;= {dmi_ch_capture_sync[1], dmi_ch_capture_sync[0]};      |         ^~~~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:113:9: &#8230; Location of other driving block  113 |         dmi_ch_capture_sync[0] &lt;= &#8216;0;      |         ^~~~~~~~~~~~~~~~~~~                      &#8230; For warning description see <\/em><a href=\"https:\/\/verilator.org\/warn\/MULTIDRIVEN?v=5.037\" rel=\"noopener noreferrer nofollow\"><em>https:\/\/verilator.org\/warn\/MULTIDRIVEN?v=5.037<\/em><\/a><em>                      &#8230; Use &#171;\/<\/em> verilator lint_off MULTIDRIVEN <em>\/&#187; and lint_on around source to disable this message.%Warning-MULTIDRIVEN: ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:61:17: Signal has multiple driving blocks with different clocking: &#8216;max10.i_top.i_core_top.i_tapc_synchronizer.dmi_ch_shift_sync&#8217;                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:127:9: &#8230; Location of first driving block  127 |         dmi_ch_shift_sync[2:1]   &lt;= {dmi_ch_shift_sync[1], dmi_ch_shift_sync[0]};      |         ^~~~~~~~~~~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/core\/scr1_tapc_synchronizer.sv:114:9: &#8230; Location of other driving block  114 |         dmi_ch_shift_sync[0]   &lt;= &#8216;0;      |         ^~~~~~~~~~~~~~~~~%Warning-MULTIDRIVEN: ..\/..\/..\/riscv-cores\/scr1\/src\/top\/scr1_timer.sv:65:53: Signal has multiple driving blocks with different clocking: &#8216;max10.i_top.i_timer.rtc_sync&#8217;                      ..\/..\/..\/riscv-cores\/scr1\/src\/top\/scr1_timer.sv:204:13: &#8230; Location of first driving block  204 |             rtc_sync[3:1]   &lt;= rtc_sync[2:0];      |             ^~~~~~~~                      ..\/..\/..\/riscv-cores\/scr1\/src\/top\/scr1_timer.sv:194:13: &#8230; Location of other driving block  194 |             rtc_sync[0] &lt;= ~rtc_sync[0];      |             ^~~~~~~~%Warning-UNOPTFLAT: ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:153:24: Signal unoptimizable: Circular combinational logic: &#8216;max10.u_sserial.u_serial_fifo.rp_bin_x&#8217;  153 | wire [aw:0]  wp_bin_x, rp_bin_x;      |                        ^~~~~~~~                    &#8230; For warning description see <\/em><a href=\"https:\/\/verilator.org\/warn\/UNOPTFLAT?v=5.037\" rel=\"noopener noreferrer nofollow\"><em>https:\/\/verilator.org\/warn\/UNOPTFLAT?v=5.037<\/em><\/a><em>                    &#8230; Use &#171;\/<\/em> verilator lint_off UNOPTFLAT <em>\/&#187; and lint_on around source to disable this message.                    ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:153:24:      Example path: max10.u_sserial.u_serial_fifo.rp_bin_x                    ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:278:17:      Example path: ASSIGNW                    ..\/..\/common\/generic_fifos\/rtl\/verilog\/generic_fifo_dc_gray.v:153:24:      Example path: max10.u_sserial.u_serial_fifo.rp_bin_x- V e r i l a t i o n   R e p o r t: Verilator 5.037 devel rev v5.036-174-g17c2512d0- Verilator: Built from 16.261 MB sources in 41 modules, into 1.835 MB in 12 C++ files needing 0.001 MB- Verilator: Walltime 0.212 s (elab=0.022, cvt=0.122, bld=0.000); cpu 0.206 s on 1 threads; alloced 34.949 MBg++  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -Os  -c -o tb.o \/home\/nick\/fpga\/riscv-compare\/FPGA\/m3-scr1\/sim\/tb.cppg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated.o \/usr\/local\/share\/verilator\/include\/verilated.cppg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -c -o verilated_threads.o \/usr\/local\/share\/verilator\/include\/verilated_threads.cppg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -x c++-header Vmax10__pch.h -o Vmax10__<\/em><a href=\"http:\/\/pch.h.fast\" rel=\"noopener noreferrer nofollow\"><em>pch.h.fast<\/em><\/a><em>.gchg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__<\/em><a href=\"http:\/\/pch.h.fast\" rel=\"noopener noreferrer nofollow\"><em>pch.h.fast<\/em><\/a><em> -c -o Vmax10.o Vmax10.cppg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__<\/em><a href=\"http:\/\/pch.h.fast\" rel=\"noopener noreferrer nofollow\"><em>pch.h.fast<\/em><\/a><em> -c -o Vmax10___024root__DepSet_h093b22e1__0.o Vmax10___024root__DepSet_h093b22e1__0.cppg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__<\/em><a href=\"http:\/\/pch.h.fast\" rel=\"noopener noreferrer nofollow\"><em>pch.h.fast<\/em><\/a><em> -c -o Vmax10___024root__DepSet_hedb980a7__0.o Vmax10___024root__DepSet_hedb980a7__0.cppg++ -Os  -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__<\/em><a href=\"http:\/\/pch.h.fast\" rel=\"noopener noreferrer nofollow\"><em>pch.h.fast<\/em><\/a><em> -c -o Vmax10___024root__DepSet_hedb980a7__1.o Vmax10___024root__DepSet_hedb980a7__1.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -x c++-header Vmax10__pch.h -o Vmax10__pch.h.slow.gchg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10__ConstPool_0.o Vmax10__ConstPool_0.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10___024root__Slow.o Vmax10___024root__Slow.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10___024root__DepSet_h093b22e1__0__Slow.o Vmax10___024root__DepSet_h093b22e1__0__Slow.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10___024root__DepSet_hedb980a7__0__Slow.o Vmax10___024root__DepSet_hedb980a7__0__Slow.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10___024root__DepSet_hedb980a7__1__Slow.o Vmax10___024root__DepSet_hedb980a7__1__Slow.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10___024unit__Slow.o Vmax10___024unit__Slow.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10___024unit__DepSet_hc138aaae__0__Slow.o Vmax10___024unit__DepSet_hc138aaae__0__Slow.cppg++   -I.  -MMD -I\/usr\/local\/share\/verilator\/include -I\/usr\/local\/share\/verilator\/include\/vltstd -DVM_COVERAGE=0 -DVM_SC=0 -DVM_TIMING=0 -DVM_TRACE=0 -DVM_TRACE_FST=0 -DVM_TRACE_VCD=0 -DVM_TRACE_SAIF=0 -faligned-new -fcf-protection=none -Wno-bool-operation -Wno-shadow -Wno-sign-compare -Wno-subobject-linkage -Wno-tautological-compare -Wno-uninitialized -Wno-unused-but-set-parameter -Wno-unused-but-set-variable -Wno-unused-parameter -Wno-unused-variable      -include Vmax10__pch.h.slow -c -o Vmax10__Syms.o Vmax10__Syms.cppecho &#171;&#187; &gt; Vmax10__ALL.verilator_deplist.tmpg++    tb.o verilated.o verilated_threads.o Vmax10__ALL.a    -pthread -lpthread -latomic   -o Vmax10rm Vmax10__ALL.verilator_deplist.tmp<\/em>***************************************************** Start Simulator                             ******************************************************Testbench started!TCM memory content from start address 0:  00000093  00000113  00000193  00000213  00000293  00000313  00000393  00000413STARTDhrystone Benchmark, Version 2.1 (Language: C)Program compiled without &#8216;register&#8217; attributeExecution starts, 500 runs through DhrystoneExecution endsFinal values of the variables used in the benchmark:Int_Glob:            5        should be:   5Bool_Glob:           1        should be:   1Ch_1_Glob:           A        should be:   ACh_2_Glob:           B        should be:   BArr_1_Glob[8]:       7        should be:   7Arr_2_Glob[8][7]:    510        should be:   Number_Of_Runs + 10Ptr_Glob-&gt;  Ptr_Comp:          12540        should be:   (implementation-dependent)  Discr:             0        should be:   0  Enum_Comp:         2        should be:   2  Int_Comp:          17        should be:   17  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING        should be:   DHRYSTONE PROGRAM, SOME STRINGNext_Ptr_Glob-&gt;  Ptr_Comp:          12540        should be:   (implementation-dependent), same as above  Discr:             0        should be:   0  Enum_Comp:         1        should be:   1  Int_Comp:          18        should be:   18  Str_Comp:          DHRYSTONE PROGRAM, SOME STRING        should be:   DHRYSTONE PROGRAM, SOME STRINGInt_1_Loc:           5        should be:   5Int_2_Loc:           13        should be:   13Int_3_Loc:           7        should be:   7Enum_Loc:            1        should be:   1Str_1_Loc:           DHRYSTONE PROGRAM, 1&#8217;ST STRING        should be:   DHRYSTONE PROGRAM, 1&#8217;ST STRINGStr_2_Loc:           DHRYSTONE PROGRAM, 2&#8217;ND STRING        should be:   DHRYSTONE PROGRAM, 2&#8217;ND STRINGBeginTime 19201 EndTime 245752 UserTime 226551Number_Of_Runs= 500, HZ= 1000000Time: begin= 19201, end= 245752, diff= 226551Microseconds for one run through Dhrystone: 453Dhrystones per Second:                      2207Cycles_Per_Instruction: 1.742Seg4x7 register Written 00002207DONE- ..\/..\/m3-scr1\/max10.v:182: Verilog $finishTestbench finished!\u00a0<\/p>\n<\/div>\n<\/details>\n<p>\u041e\u0431\u0440\u0430\u0442\u0438\u0442\u0435 \u0432\u043d\u0438\u043c\u0430\u043d\u0438\u0435, \u0447\u0442\u043e \u0432 \u043a\u043e\u043d\u0446\u0435 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u043b\u043e\u0433 \u0432\u044b\u0434\u0430\u0451\u0442 \u0447\u0438\u0441\u043b\u043e Dhrystones per Second \u0438 \u0443 \u0440\u0430\u0437\u043d\u044b\u0445 \u044f\u0434\u0435\u0440 \u044d\u0442\u043e \u0447\u0438\u0441\u043b\u043e \u0440\u0430\u0437\u043d\u043e\u0435! \u0414\u043b\u044f SOC \u0441 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u043e\u043c SCR1 \u0432 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 IM \u044d\u0442\u043e \u0447\u0438\u0441\u043b\u043e 2207.<\/p>\n<h2>\u041a\u043e\u043c\u043f\u0438\u043b\u044f\u0446\u0438\u044f \u043f\u0440\u043e\u0435\u043a\u0442\u043e\u0432 FPGA scr1 \u0438 picorv32 SOC.<\/h2>\n<p>\u041f\u0440\u043e\u0435\u043a\u0442\u044b SOC \u0434\u043b\u044f picorv32 \u0438 \u0434\u043b\u044f scr1 \u043d\u0430\u0445\u043e\u0434\u044f\u0442\u0441\u044f \u0432 \u043f\u0430\u043f\u043a\u0430\u0445 riscv-compare\/FPGA\/m3-picorv32 \u0438 riscv-compare\/FPGA\/m3-scr1 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0435\u043d\u043d\u043e. \u041d\u0443\u0436\u043d\u043e \u0437\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u044c \u0421\u0410\u041f\u0420 Quartus Prime, \u043f\u0435\u0440\u0435\u0439\u0442\u0438 \u0432 \u043d\u0443\u0436\u043d\u0443\u044e \u043f\u0430\u043f\u043a\u0443  \u0438 \u043e\u0442\u043a\u0440\u044b\u0442\u044c \u043f\u0440\u043e\u0435\u043a\u0442.<\/p>\n<p>\u041f\u043e\u0441\u043b\u0435 \u0442\u043e\u0433\u043e, \u043a\u0430\u043a \u043e\u0442\u043a\u0440\u043e\u0435\u0442\u0435 \u043f\u0440\u043e\u0435\u043a\u0442 \u043d\u0443\u0436\u043d\u043e \u0432\u044b\u0431\u0440\u0430\u0442\u044c \u0440\u0435\u0432\u0438\u0437\u0438\u044e \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0447\u0435\u0440\u0435\u0437 \u043c\u0435\u043d\u044e \u043a\u0432\u0430\u0440\u0442\u0443\u0441\u0430 Project -&gt; Revisions. \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u0434\u043b\u044f SOC Scr1 \u0435\u0441\u0442\u044c \u0447\u0435\u0442\u044b\u0440\u0435 \u043c\u043d\u043e\u044e \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043d\u044b\u0445 \u0440\u0435\u0432\u0438\u0437\u0438\u0439 \u0434\u043b\u044f \u0434\u0432\u0443\u0445 \u043f\u043b\u0430\u0442 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343 \u0438 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343\u0431\u0438\u0441 &#8212; \u043e\u043d\u0438 \u043e\u0442\u043b\u0438\u0447\u0430\u044e\u0442\u0441\u044f \u0443\u0441\u0442\u0430\u043d\u043e\u0432\u043b\u0435\u043d\u043d\u044b\u043c \u0447\u0438\u043f\u043e\u043c MAX10 \u0438 \u043a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e\u043c \u0438\u043c\u0435\u044e\u0449\u0438\u0445\u0441\u044f \u0432 \u043d\u0435\u043c \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u043e\u0432 50 \u0442\u044b\u0441\u044f\u0447 \u0438\u043b\u0438 8 \u0442\u044b\u0441\u044f\u0447. \u0414\u043b\u044f \u043a\u0430\u0436\u0434\u043e\u0439 \u0438\u0437 \u043f\u043b\u0430\u0442 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0435\u043d\u043e \u0442\u0430\u043a \u0436\u0435 \u043a\u0430\u043a\u0430\u044f \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0430 \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f EC \u0438\u043b\u0438 \u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f IM.<\/p>\n<p>\u0412\u0441\u0435\u0433\u043e 4 \u0440\u0435\u0432\u0438\u0437\u0438\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u043e\u043f\u0438\u0441\u0430\u043d\u044b \u0432 \u0444\u0430\u0439\u043b\u0435 max10.qpf (Quartus Project File):<\/p>\n<pre><code>QUARTUS_VERSION = \"23.1\"DATE = \"19:24:25 April 23, 2026\"# RevisionsPROJECT_REVISION = \"max10_8K_ec\"PROJECT_REVISION = \"max10_50K_im\"PROJECT_REVISION = \"max10_50K_ec\"PROJECT_REVISION = \"max10_8K_im\"<\/code><div class=\"code-explainer\"><a href=\"https:\/\/sourcecraft.dev\/\" class=\"tm-button code-explainer__link\" style=\"visibility: hidden;\"><img style=\"width:14px;height:14px;object-fit:cover;object-position:left;\"\/><\/a><\/div><\/pre>\n<p>\u0412\u044b\u0431\u0438\u0440\u0430\u0435\u0442\u0435 \u0438\u043d\u0442\u0435\u0440\u0435\u0441\u0443\u044e\u0449\u0443\u044e \u0432\u0430\u0441 \u0440\u0435\u0432\u0438\u0437\u0438\u044e, \u043a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u0435\u0442\u0435 \u0434\u043b\u044f \u0432\u0430\u0448\u0435\u0439 \u043f\u043b\u0430\u0442\u044b \u0438 \u0437\u0430\u0433\u0440\u0443\u0436\u0430\u0435\u0442\u0435 \u0432 \u041f\u041b\u0418\u0421.<\/p>\n<p>\u041d\u0430 \u0441\u0435\u043c\u0438-\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u043e\u043c \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0435 \u043f\u043b\u0430\u0442\u044b \u0432\u044b \u0443\u0432\u0438\u0434\u0438\u0442\u0435 \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u0435 Dhrystone \u0442\u0435\u0441\u0442\u0430:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/1d2\/18f\/86d\/1d218f86dbdc933a120d78c986d1d046.jpg\" alt=\"FPGA \u043f\u043b\u0430\u0442\u0430 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343, SCR1 IM, Dhrystone 2207\" title=\"FPGA \u043f\u043b\u0430\u0442\u0430 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343, SCR1 IM, Dhrystone 2207\" width=\"720\" height=\"397\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/1d2\/18f\/86d\/1d218f86dbdc933a120d78c986d1d046.jpg 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/1d2\/18f\/86d\/1d218f86dbdc933a120d78c986d1d046.jpg 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>FPGA \u043f\u043b\u0430\u0442\u0430 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343, SCR1 IM, Dhrystone 2207<\/figcaption><\/div>\n<\/figure>\n<p>\u041a \u043f\u043b\u0430\u0442\u0435 \u043c\u043e\u0436\u043d\u043e \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0438\u0442\u044c\u0441\u044f \u0447\u0435\u0440\u0435\u0437 \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u043f\u043e\u0440\u0442 \u043d\u0430 \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u0438 12\u041c\u0431\u0438\u0442\/\u0441\u0435\u043a \u0438 \u0442\u043e\u0433\u0434\u0430 \u043c\u043e\u0436\u043d\u043e \u0443\u0432\u0438\u0434\u0435\u0442\u044c \u0432\u044b\u0432\u043e\u0434 \u0432\u0441\u0435\u0439 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b Dhrystone \u0432 \u043a\u043e\u043d\u0441\u043e\u043b\u0438 Putty:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/16d\/77f\/50f\/16d77f50f79aaa0f3ca5800d22e50cb9.png\" alt=\"Putty serial console to RISC-V Scr1, config  IM\" title=\"Putty serial console to RISC-V Scr1, config  IM\" width=\"720\" height=\"369\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/16d\/77f\/50f\/16d77f50f79aaa0f3ca5800d22e50cb9.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/16d\/77f\/50f\/16d77f50f79aaa0f3ca5800d22e50cb9.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>Putty serial console to RISC-V Scr1, config  IM<\/figcaption><\/div>\n<\/figure>\n<p>\u041a\u0430\u043a \u0432\u044b \u043c\u043e\u0436\u0435\u0442\u0435 \u0437\u0430\u043c\u0435\u0442\u0438\u0442\u044c, \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438 \u0441 Verilator \u0438 \u0437\u0430\u043f\u0443\u0441\u043a \u0432 \u0440\u0435\u0430\u043b\u044c\u043d\u043e\u0439 \u043f\u043b\u0430\u0442\u0435 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343 \u043e\u0442\u043e\u0431\u0440\u0430\u0436\u0430\u044e\u0442 \u0432 \u043a\u043e\u043d\u0441\u043e\u043b\u0438 \u0438 \u043d\u0430 \u0441\u0435\u043c\u0438-\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u043e\u043c \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0435 \u043e\u0434\u043d\u043e \u0438 \u0442\u043e \u0436\u0435 \u0447\u0438\u0441\u043b\u043e \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u043d\u043e\u0439 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 2207!<\/p>\n<p>\u0412 \u0441\u0440\u0435\u0434\u0435 \u043a\u0432\u0430\u0440\u0442\u0443\u0441 \u0435\u0441\u0442\u044c \u043f\u043e\u043b\u0435\u0437\u043d\u044b\u0435 \u043e\u0442\u0447\u0435\u0442\u044b \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440\u0430 \u0438\u0437 \u043a\u043e\u0442\u043e\u0440\u044b\u0445 \u043c\u044b \u0443\u0437\u043d\u0430\u0435\u043c \u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u0443\u044e \u0447\u0430\u0441\u0442\u043e\u0442\u0443 Fmax, \u043a\u043e\u0442\u043e\u0440\u0443\u044e \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043d\u0430 \u044f\u0434\u0440\u0435 \u0438 \u043a\u043e\u0442\u043e\u0440\u0443\u044e \u043e\u0431\u0435\u0449\u0430\u0435\u0442 Quartus, \u0430 \u0442\u0430\u043a \u0436\u0435 \u043a\u043e\u043b\u0438\u0447\u0435\u0441\u0442\u0432\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u043d\u044b\u0445 \u0440\u0435\u0441\u0443\u0440\u0441\u043e\u0432 FPGA: \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432, \u043f\u0430\u043c\u044f\u0442\u0438, \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u0435\u0439 \u0438 \u0442\u0430\u043a \u0434\u0430\u043b\u0435\u0435. \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u0432\u043e\u0442 Resource Usage by Entity:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/ede\/2af\/85f\/ede2af85f68db59103ee67877d231b2f.png\" alt=\"Quartus Compilation Report, Usage by Entity\" title=\"Quartus Compilation Report, Usage by Entity\" width=\"1320\" height=\"453\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/ede\/2af\/85f\/ede2af85f68db59103ee67877d231b2f.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/ede\/2af\/85f\/ede2af85f68db59103ee67877d231b2f.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>Quartus Compilation Report, Usage by Entity<\/figcaption><\/div>\n<\/figure>\n<p>\u041e\u0442\u0441\u044e\u0434\u0430 \u0438 \u0438\u0437 \u0434\u0440\u0443\u0433\u0438\u0445 \u043e\u0442\u0447\u0435\u0442\u043e\u0432 \u044f \u0431\u0443\u0434\u0443 \u0431\u0440\u0430\u0442\u044c \u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f \u0434\u043b\u044f \u0438\u0442\u043e\u0433\u043e\u0432\u043e\u0439 \u0442\u0430\u0431\u043b\u0438\u0446\u044b \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u0439.<\/p>\n<p>\u0418\u0442\u043e\u0433\u043e\u0432\u0430\u044f \u0442\u0430\u0431\u043b\u0438\u0446\u0430 \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u0439.<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/855\/7b0\/735\/8557b0735392e318c9f9ed88eb1ba57d.png\" width=\"1000\" height=\"137\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/855\/7b0\/735\/8557b0735392e318c9f9ed88eb1ba57d.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/855\/7b0\/735\/8557b0735392e318c9f9ed88eb1ba57d.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/figure>\n<p>\u0412\u043e\u0442 \u0434\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u0430 Fmax \u0434\u043b\u044f \u0440\u0430\u0437\u043d\u044b\u0445 \u043f\u0440\u043e\u0435\u043a\u0442\u043e\u0432, \u043a\u0430\u043a \u0435\u0451 \u0440\u0430\u043f\u043e\u0440\u0442\u0443\u0435\u0442 \u0421\u0410\u041f\u0420 Quartus:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/76f\/08a\/c06\/76f08ac06c05e864dbd868393ec2cdec.png\" alt=\"Fmax Chart\" title=\"Fmax Chart\" width=\"572\" height=\"333\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/76f\/08a\/c06\/76f08ac06c05e864dbd868393ec2cdec.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/76f\/08a\/c06\/76f08ac06c05e864dbd868393ec2cdec.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>Fmax Chart<\/figcaption><\/div>\n<\/figure>\n<p>\u0418\u0437 \u044d\u0442\u043e\u0439 \u0442\u0430\u0431\u043b\u0438\u0446\u044b \u0438 \u0434\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u044b \u0432\u0438\u0434\u043d\u043e, \u0447\u0442\u043e \u0432\u0438\u0434\u0438\u043c\u043e \u044f\u0434\u0440\u043e scr1 \u0431\u043e\u043b\u0435\u0435 \u0441\u043b\u043e\u0436\u043d\u043e\u0435, \u043e\u043d\u043e \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u0442 \u0431\u043e\u043b\u044c\u0448\u0435 \u043b\u043e\u0433\u0438\u043a\u0438 \u0438 \u0442\u0440\u0435\u0431\u0443\u0435\u0442 \u0431\u043e\u043b\u044c\u0448\u0435 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432. \u0421\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0435\u043d\u043d\u043e \u0438 \u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u0430\u044f \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u0430\u044f \u0442\u0430\u043a\u0442\u043e\u0432\u0430\u044f \u0447\u0430\u0441\u0442\u043e\u0442\u0430 \u0434\u043b\u044f \u043c\u043e\u0435\u0439 FPGA \u043f\u043e\u043b\u0443\u0447\u0430\u0435\u0442\u0441\u044f \u043d\u0438\u0436\u0435. \u041f\u0440\u0438 \u0432\u0441\u0451\u043c \u043f\u0440\u0438 \u044d\u0442\u043e\u043c, \u044d\u0442\u043e \u044f\u0434\u0440\u043e \u044f\u0432\u043d\u043e \u0431\u044b\u0441\u0442\u0440\u0435\u0435, \u0442\u0430\u043a \u043a\u0430\u043a \u0432\u044b\u043f\u043e\u043b\u043d\u044f\u0435\u0442 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 \u0437\u0430 \u043c\u0435\u043d\u044c\u0448\u0435\u0435 \u0447\u0438\u0441\u043b\u043e \u0442\u0430\u043a\u0442\u043e\u0432 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430.<\/p>\n<p>\u041d\u0438\u0436\u0435 \u044f \u043f\u0440\u0438\u0432\u0435\u0434\u0443 \u043f\u043e\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u044b\u0435 \u043f\u043e \u044d\u0442\u043e\u0439 \u0442\u0430\u0431\u043b\u0438\u0446\u0435 \u0434\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u044b \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438.<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/3d3\/976\/775\/3d3976775d6e9ad1e6e61b50c7bfcf68.png\" alt=\"Dhry Chart\" title=\"Dhry Chart\" width=\"571\" height=\"340\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/3d3\/976\/775\/3d3976775d6e9ad1e6e61b50c7bfcf68.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/3d3\/976\/775\/3d3976775d6e9ad1e6e61b50c7bfcf68.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>Dhry Chart<\/figcaption><\/div>\n<\/figure>\n<p>\u0414\u0438\u0430\u0433\u0440\u0430\u043c\u043c\u0430 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 \u044f\u0434\u0435\u0440 scr1 \u0438 picorv32 \u0432 \u0435\u0434\u0438\u043d\u0438\u0446\u0430\u0445 \u0438\u0437\u043c\u0435\u0440\u0435\u043d\u0438\u044f Dhrystone. \u0418\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u043e, \u0447\u0442\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 scr1 \u0432 \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 EC \u043f\u043e\u0447\u0442\u0438 \u043d\u0435 \u0443\u0441\u0442\u0443\u043f\u0430\u0435\u0442 \u043c\u0430\u043a\u0441\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 IM, \u043d\u043e \u0442\u0430\u043a, \u043a\u0430\u043a Fmax \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0443 EC \u043e\u043a\u0430\u0437\u0430\u043b\u0430\u0441\u044c \u0432\u044b\u0448\u0435, \u0442\u043e \u0432 \u0446\u0435\u043b\u043e\u043c \u0435\u0433\u043e \u043c\u043e\u0436\u043d\u043e \u0431\u044b\u0441\u0442\u0440\u0435\u0435 \u0440\u0430\u0437\u043e\u0433\u043d\u0430\u0442\u044c \u0438 \u0434\u0430\u0436\u0435 \u043e\u0431\u043e\u0439\u0442\u0438 \u0432 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044e IM.<\/p>\n<p>\u041d\u0443 \u0438 \u0432\u0438\u0434\u043d\u043e, \u0447\u0442\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 scr1 \u044f\u0432\u043d\u043e \u0432\u044b\u0438\u0433\u0440\u044b\u0432\u0430\u0435\u0442 \u043f\u043e \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u0438 \u0443 picorv32 \u0434\u0430\u0436\u0435 \u0432 \u043f\u0435\u0440\u0435\u0441\u0447\u0451\u0442\u0435 \u043d\u0430 Fmax.<\/p>\n<p>\u041c\u043e\u0438 FPGA \u043f\u0440\u043e\u0435\u043a\u0442\u044b \u043f\u043e\u0434\u0430\u044e\u0442 \u043d\u0430 \u044f\u0434\u0440\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 20\u041c\u0413\u0446. \u0417\u043d\u0430\u0447\u0438\u0442 \u043f\u0435\u0440\u0435\u0441\u0447\u0435\u0442 \u043d\u0430 Fmax \u0431\u0443\u0434\u0435\u0442 Dhry\/20*Fmax. \u0412\u043e\u0442 \u0442\u0430\u043a \u044f \u044d\u0442\u043e \u0441\u0447\u0438\u0442\u0430\u044e.<\/p>\n<p>\u041d\u0443 \u0438 \u043f\u043e \u0440\u0435\u0441\u0443\u0440\u0441\u0430\u043c. \u041a\u043e\u043d\u0435\u0447\u043d\u043e, picorv32 \u043e\u043a\u0430\u0437\u044b\u0432\u0430\u0435\u0442\u0441\u044f \u0431\u043e\u043b\u0435\u0435 \u043a\u043e\u043c\u043f\u0430\u043a\u0442\u043d\u044b\u043c:<\/p>\n<figure class=\"full-width \"><img decoding=\"async\" src=\"https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/645\/e83\/712\/645e837121aa86fdc92d5d0807fceeb2.png\" alt=\"Resource Usage\" title=\"Resource Usage\" width=\"569\" height=\"337\" sizes=\"auto, (max-width: 780px) 100vw, 50vw\" srcset=\"https:\/\/habrastorage.org\/r\/w780\/getpro\/habr\/upload_files\/645\/e83\/712\/645e837121aa86fdc92d5d0807fceeb2.png 780w,&#10;       https:\/\/habrastorage.org\/r\/w1560\/getpro\/habr\/upload_files\/645\/e83\/712\/645e837121aa86fdc92d5d0807fceeb2.png 781w\" loading=\"lazy\" decode=\"async\"\/><\/p>\n<div><figcaption>Resource Usage<\/figcaption><\/div>\n<\/figure>\n<p>\u042f\u0434\u0440\u0443 picorv32 \u043d\u0443\u0436\u043d\u043e \u043c\u0435\u043d\u044c\u0448\u0435 \u043b\u043e\u0433\u0438\u043a\u0438 \u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0434\u043b\u044f \u043d\u043e\u0440\u043c\u0430\u043b\u044c\u043d\u043e\u0433\u043e \u0444\u0443\u043d\u043a\u0446\u0438\u043e\u043d\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u044f.<\/p>\n<p>\u0412 \u0446\u0435\u043b\u043e\u043c \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0430\u0442 \u043e\u0436\u0438\u0434\u0430\u0435\u043c\u044b\u0439. \u0411\u043e\u043b\u0435\u0435 \u0441\u043b\u043e\u0436\u043d\u0430\u044f \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 scr1 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0443\u043b\u0443\u0447\u0448\u0438\u0442\u044c \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u044c, \u043d\u043e \u043e\u043d\u0430 \u0442\u0440\u0435\u0431\u0443\u0435\u0442 \u0431\u043e\u043b\u044c\u0448\u0438\u0445 \u0440\u0435\u0441\u0443\u0440\u0441\u043e\u0432 \u0432 FPGA.<\/p>\n<p>\u041d\u0443 \u0438 \u0432 \u043a\u043e\u043d\u0446\u0435 \u044f \u0445\u043e\u0442\u0435\u043b \u0431\u044b \u0434\u043e\u0431\u0430\u0432\u0438\u0442\u044c, \u0447\u0442\u043e \u043c\u043d\u0435 \u043e\u0434\u0438\u043d\u0430\u043a\u043e\u0432\u043e \u0441\u0438\u043c\u043f\u0430\u0442\u0438\u0447\u043d\u044b \u043e\u0431\u0430 \u044f\u0434\u0440\u0430 \u0438 scr1 \u0438 picorv32. \u041e\u043d\u0438 \u043d\u0435\u0441\u043e\u043c\u043d\u0435\u043d\u043d\u043e \u043c\u043e\u0433\u0443\u0442 \u0431\u044b\u0442\u044c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u044b \u0432\u043e \u0432\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c\u044b\u0445 \u043f\u0440\u0438\u043b\u043e\u0436\u0435\u043d\u0438\u044f\u0445. \u041d\u0443 \u0430 \u043a\u0430\u043a\u043e\u0435 \u044f\u0434\u0440\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0430\u0445 \u0443\u0436\u0435 \u0440\u0435\u0448\u0430\u0442\u044c \u0432\u0430\u043c.<\/p>\n<p>\u0415\u0449\u0451 \u0445\u043e\u0442\u0435\u043b \u0431\u044b \u0434\u043e\u0431\u0430\u0432\u0438\u0442\u044c, \u0447\u0442\u043e \u043e\u0434\u043d\u0430 \u0438\u0437 \u0432\u0430\u0436\u043d\u044b\u0445 \u0438 \u0438\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u044b\u0445 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0435\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 scr1 \u044d\u0442\u043e \u043d\u0430\u0441\u0442\u043e\u044f\u0449\u0430\u044f \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 JTAG \u043e\u0442\u043b\u0430\u0434\u043a\u0438. \u0427\u0435\u0440\u0435\u0437 JTAG \u043c\u043e\u0436\u043d\u043e \u0432\u0435\u0441\u0442\u0438 \u043e\u0442\u043b\u0430\u0434\u043a\u0443 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c \u0440\u0430\u0431\u043e\u0442\u0430\u044e\u0449\u0438\u0445 \u043f\u0440\u044f\u043c\u043e \u0432 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0435 \u0441 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u043e\u0442\u043b\u0430\u0434\u0447\u0438\u043a\u0430 GDB. \u0418 \u0434\u043b\u044f \u044d\u0442\u043e\u0433\u043e \u043d\u0430 \u0441\u0430\u043c\u043e\u043c \u0434\u0435\u043b\u0435 \u0434\u0430\u0436\u0435 \u0438 \u043f\u043b\u0430\u0442\u0430 \u043d\u0435 \u043d\u0443\u0436\u043d\u0430. \u042f \u0443\u0436\u0435 \u043d\u0430\u043f\u0438\u0441\u0430\u043b, \u043a\u0430\u043a <a href=\"https:\/\/marsohod.org\/projects\/marsohod3-board-prj\/risc-v\/458-gdb-verilator-sim\" rel=\"noopener noreferrer nofollow\">\u0432\u0435\u0441\u0442\u0438 \u043e\u0442\u043b\u0430\u0434\u043a\u0443 \u044f\u0434\u0440\u0430 scr1 \u0440\u0430\u0431\u043e\u0442\u0430\u044e\u0449\u0435\u0433\u043e \u043f\u043e\u0434 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u043e\u043c Verilator \u0447\u0435\u0440\u0435\u0437 \u0432\u0438\u0440\u0442\u0443\u0430\u043b\u044c\u043d\u044b\u0439 JTAG<\/a>.<\/p>\n<p>\u041e\u0434\u043d\u0430\u043a\u043e \u0443\u0447\u0442\u0438\u0442\u0435, \u0447\u0442\u043e \u0441\u0435\u0439\u0447\u0430\u0441 \u0432 \u043c\u043e\u0435\u043c \u043f\u0440\u043e\u0435\u043a\u0442\u0435 \u044f \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0438\u043b \u043a \u043b\u0438\u043d\u0438\u044f\u043c JTAG \u043f\u0440\u043e\u0441\u0442\u043e \u043a\u043e\u043d\u0441\u0442\u0430\u043d\u0442\u044b \u043d\u043e\u043b\u044c, \u0442\u043e \u0435\u0441\u0442\u044c \u043e\u043d\u0438 \u043d\u0435 \u0440\u0430\u0431\u043e\u0442\u0430\u044e\u0442 \u0438 \u0437\u043d\u0430\u0447\u0438\u0442 \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440 \u0432\u044b\u0431\u0440\u043e\u0441\u0438\u043b \u0438\u0437 \u0430\u043d\u0430\u043b\u0438\u0437\u0430 \u0432\u0441\u044e \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u0443\u044e \u043b\u043e\u0433\u0438\u043a\u0443. \u0421 \u0440\u0430\u0431\u043e\u0442\u0430\u044e\u0449\u0438\u043c JTAG \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 scr1 \u0431\u0443\u0434\u0435\u0442 \u0437\u0430\u043d\u0438\u043c\u0430\u0442\u044c \u0433\u043e\u0440\u0430\u0437\u0434\u043e \u0431\u043e\u043b\u044c\u0448\u0435 \u043c\u0435\u0441\u0442\u0430 \u0432 \u041f\u041b\u0418\u0421.<\/p>\n<p>\u0427\u0442\u043e \u043a\u0430\u0441\u0430\u0435\u0442\u0441\u044f \u044f\u0434\u0440\u0430 \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u0430 picorv32, \u0442\u043e \u0435\u0433\u043e \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u043f\u0440\u043e\u0441\u0442\u043e \u0437\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u044c \u0434\u0430\u0436\u0435 \u043d\u0430 \u043f\u043b\u0430\u0442\u0430\u0445 \u0441 \u043e\u0433\u0440\u0430\u043d\u0438\u0447\u0435\u043d\u043d\u044b\u043c\u0438 \u0440\u0435\u0441\u0443\u0440\u0441\u0430\u043c\u0438. \u041d\u0430\u043f\u0440\u0438\u043c\u0435\u0440, \u044f \u0437\u0430\u043f\u0443\u0441\u043a\u0430\u043b \u044d\u0442\u043e \u044f\u0434\u0440\u043e \u043d\u0430 \u043f\u043b\u0430\u0442\u0435 <a href=\"https:\/\/marsohod.org\/projects\/marsohod3gw-prj\" rel=\"noopener noreferrer nofollow\">\u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343WG2<\/a> \u0441 \u043c\u0438\u043a\u0440\u043e\u0441\u0445\u0435\u043c\u043e\u0439 \u041f\u041b\u0418\u0421 \u043e\u0442 Gowin. \u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u044d\u0442\u043e\u0433\u043e \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0442\u0430\u043a \u0436\u0435 <a href=\"https:\/\/github.com\/marsohod4you\/Marsohod3GW\/tree\/Marsohod3GW2_GW1NR-LV9QN88PC6I5\/_picotiny\" rel=\"noopener noreferrer nofollow\">\u0435\u0441\u0442\u044c \u043d\u0430 Github<\/a>.<\/p>\n<\/div>\n<p>\u0441\u0441\u044b\u043b\u043a\u0430 \u043d\u0430 \u043e\u0440\u0438\u0433\u0438\u043d\u0430\u043b \u0441\u0442\u0430\u0442\u044c\u0438 <a href=\"https:\/\/habr.com\/ru\/articles\/1027538\/\">https:\/\/habr.com\/ru\/articles\/1027538\/<\/a><\/p>\n","protected":false},"excerpt":{"rendered":"<p>\u0420\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0438 FPGA \u0447\u0430\u0441\u0442\u043e \u0441\u0442\u0430\u043b\u043a\u0438\u0432\u0430\u044e\u0442\u0441\u044f \u0441 \u043d\u0435\u043e\u0431\u0445\u043e\u0434\u0438\u043c\u043e\u0441\u0442\u044c\u044e \u0432\u043d\u0435\u0434\u0440\u0435\u043d\u0438\u044f \u0432 \u0441\u0432\u043e\u0439 \u043f\u0440\u043e\u0435\u043a\u0442 \u0441\u043e\u0444\u0442 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430. \u041a\u043e\u0433\u0434\u0430-\u0442\u043e \u0434\u0430\u0432\u043d\u043e \u043c\u044b \u043c\u043e\u0433\u043b\u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043f\u0440\u043e\u043f\u0440\u0438\u0435\u0442\u0430\u0440\u043d\u044b\u0435 Altera NIOS \u0438\u043b\u0438 Xilinx MicroBlase. \u041d\u043e \u0432\u0440\u0435\u043c\u044f \u0438\u0434\u0435\u0442. \u0412 \u043f\u043e\u0441\u043b\u0435\u0434\u043d\u0438\u0435 \u0433\u043e\u0434\u044b \u043d\u0430\u0431\u043b\u044e\u0434\u0430\u0435\u0442\u0441\u044f \u0443\u0441\u0442\u043e\u0439\u0447\u0438\u0432\u044b\u0439 \u0442\u0440\u0435\u043d\u0434 \u043f\u0435\u0440\u0435\u0445\u043e\u0434\u0430 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u0435\u0439 \u041f\u041b\u0418\u0421 \u0432 \u0441\u0442\u043e\u0440\u043e\u043d\u0443 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0438 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u044b RISC-V.RISC-V \u044d\u0442\u043e \u043e\u0442\u043a\u0440\u044b\u0442\u0430\u044f, \u0440\u0430\u0441\u0448\u0438\u0440\u044f\u0435\u043c\u0430\u044f \u0438 \u0431\u0435\u0441\u043f\u043b\u0430\u0442\u043d\u0430\u044f \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 \u043d\u0430\u0431\u043e\u0440\u0430 \u043a\u043e\u043c\u0430\u043d\u0434 (ISA), \u043a\u043e\u0442\u043e\u0440\u0430\u044f \u043d\u0435 \u0442\u0440\u0435\u0431\u0443\u0435\u0442 \u043b\u0438\u0446\u0435\u043d\u0437\u0438\u043e\u043d\u043d\u044b\u0445 \u043e\u0442\u0447\u0438\u0441\u043b\u0435\u043d\u0438\u0439. \u041e\u0431\u0430 FPGA \u0432\u0435\u043d\u0434\u043e\u0440\u0430 Altera \u0438 Xilinx \u0443\u0436\u0435 \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e \u0434\u0430\u0432\u043d\u043e \u043f\u0440\u0435\u0434\u043b\u0430\u0433\u0430\u044e\u0442 \u0438 \u0430\u043a\u0442\u0438\u0432\u043d\u043e \u0440\u0430\u0437\u0440\u0430\u0431\u0430\u0442\u044b\u0432\u0430\u044e\u0442 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0443 RISC-V \u0432 \u0441\u0432\u043e\u0438\u0445 \u043d\u043e\u0432\u044b\u0445 \u043f\u0440\u043e\u0434\u0443\u043a\u0442\u0430\u0445, \u0442\u0435\u043f\u0435\u0440\u044c \u044d\u0442\u043e \u0443\u0436\u0435 \u0441\u043e\u0444\u0442 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u044b NIOS V \u0438 MicroBlase V \u0434\u043b\u044f FPGA.\u041e\u0434\u043d\u0430\u043a\u043e, \u0437\u0430\u0447\u0435\u043c \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0432\u0441\u0451 \u0435\u0449\u0451 \u043f\u0440\u043e\u043f\u0440\u0438\u0435\u0442\u0430\u0440\u043d\u044b\u0435 \u044f\u0434\u0440\u0430, \u0435\u0441\u043b\u0438 \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c Open Source?\u0412 \u044d\u0442\u043e\u0439 \u0441\u0442\u0430\u0442\u044c\u0435 \u044f \u0441\u0440\u0430\u0432\u043d\u0438\u0432\u0430\u044e \u0434\u0432\u0430 Open Source RISC-V \u043c\u0438\u043a\u0440\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430:1) picorv32 \u043e\u0442 \u043a\u043e\u043c\u043f\u0430\u043d\u0438\u0438 YoSys (https:\/\/github.com\/YosysHQ\/picorv32) \u04382) scr1 \u043e\u0442 Syntacore (https:\/\/github.com\/syntacore\/scr1)\u0427\u0442\u043e \u0431\u0443\u0434\u0443 \u0441\u0440\u0430\u0432\u043d\u0438\u0432\u0430\u0442\u044c? \u041f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u044c \u0441\u043e\u0444\u0442 \u044f\u0434\u0435\u0440 \u0438 \u0437\u0430\u043d\u0438\u043c\u0430\u0435\u043c\u044b\u0435 \u0440\u0435\u0441\u0443\u0440\u0441\u044b \u0432 \u041f\u041b\u0418\u0421.\u041a\u0430\u043a \u043f\u0440\u0430\u0432\u0438\u043b\u044c\u043d\u043e \u0441\u0440\u0430\u0432\u043d\u0438\u0442\u044c? \u0418\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0435\u0434\u0438\u043d\u0443\u044e \u0442\u0435\u0441\u0442\u043e\u0432\u0443\u044e \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0443 \u043d\u0430\u043f\u0438\u0441\u0430\u043d\u043d\u0443\u044e \u043d\u0430 \u044f\u0437\u044b\u043a\u0435 C, \u043d\u0430\u043f\u0440\u0438\u043c\u0435\u0440 Dhrystone, \u0438 \u0441\u043a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u0443\u044e \u0432 \u0431\u0438\u043d\u0430\u0440\u043d\u044b\u0439 \u0444\u0430\u0439\u043b, \u0438\u043b\u0438 HEX \u0444\u0430\u0439\u043b \u0438 \u0437\u0430\u043f\u0443\u0441\u043a\u0430\u0435\u043c\u0443\u044e \u0432 \u0434\u0432\u0443\u0445 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043d\u043e \u043e\u0434\u0438\u043d\u0430\u043a\u043e\u0432\u044b\u0445 SOC, \u043d\u043e \u0441 \u0440\u0430\u0437\u043d\u044b\u043c\u0438 \u044f\u0434\u0440\u0430\u043c\u0438 RISC-V.\u0418\u043d\u0442\u0435\u0440\u0435\u0441\u043d\u043e, \u0447\u0442\u043e \u0432 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0430\u0445 picorv32 \u0435\u0441\u0442\u044c \u0442\u0435\u0441\u0442 Dhrystone \u0438 \u0432 \u0438\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0430\u0445 scr1 \u0435\u0441\u0442\u044c \u0442\u0435\u0441\u0442 Dhrystone, \u043d\u043e \u0443 \u043d\u0438\u0445 \u0445\u043e\u0442\u044c \u0438 \u043f\u043e\u0445\u043e\u0436\u0438\u0435, \u043d\u043e \u0432\u0441\u0451 \u0436\u0435 \u0440\u0430\u0437\u043d\u044b\u0435 \u0444\u0430\u0439\u043b\u044b \u043f\u043e \u0441\u043e\u0434\u0435\u0440\u0436\u0438\u043c\u043e\u043c\u0443! \u041a\u0440\u043e\u043c\u0435 \u044d\u0442\u043e\u0433\u043e, \u0440\u0430\u0437\u0440\u0430\u0431\u043e\u0442\u0447\u0438\u043a\u0438 \u044d\u0442\u0438\u0445 \u044f\u0434\u0435\u0440 \u0441\u0441\u044b\u043b\u0430\u044e\u0442\u0441\u044f \u043d\u0430 \u0440\u0430\u0437\u043d\u044b\u0435 \u0442\u0443\u043b\u0447\u0435\u0439\u043d\u044b \u0434\u043b\u044f \u0441\u0431\u043e\u0440\u043a\u0438. \u0421\u043e\u0433\u043b\u0430\u0441\u0438\u0442\u0435\u0441\u044c, \u0447\u0442\u043e \u043d\u0435 \u0441\u043e\u0432\u0441\u0435\u043c \u0432\u0435\u0440\u043d\u043e \u0441\u043e\u0431\u0438\u0440\u0430\u0442\u044c \u0435\u0434\u0438\u043d\u0443\u044e \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0443 \u0440\u0430\u0437\u043d\u044b\u043c\u0438 \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440\u0430\u043c\u0438. \u0414\u043b\u044f \u0447\u0438\u0441\u0442\u043e\u0442\u044b \u044d\u043a\u0441\u043f\u0435\u0440\u0438\u043c\u0435\u043d\u0442\u0430 \u044f \u0431\u0443\u0434\u0443 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043e\u0434\u0438\u043d \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440 \u0432\u0437\u044f\u0442\u044b\u0439 \u0432\u043e\u0442 \u043e\u0442\u0441\u044e\u0434\u0430: https:\/\/syntacore.com\/tools\/development-tools \u0423 \u043c\u0435\u043d\u044f \u043f\u043e\u043b\u0443\u0447\u0438\u0442\u0441\u044f \u043e\u0434\u043d\u0430 &#171;\u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0430&#187; \u0434\u043b\u044f \u0434\u0432\u0443\u0445 \u0440\u0430\u0437\u043d\u044b\u0445 SOC \u0438 \u0442\u043e\u0433\u0434\u0430 \u044d\u0442\u043e \u0431\u0443\u0434\u0435\u0442 \u0441\u0430\u043c\u043e\u0435 \u043e\u0431\u044a\u0435\u043a\u0442\u0438\u0432\u043d\u043e\u0435 \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u0435.\u0415\u0449\u0435 \u043e\u0434\u043d\u043e \u0437\u0430\u043c\u0435\u0447\u0430\u043d\u0438\u0435: RISC-V \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0430 \u043f\u043e\u0434\u0440\u0430\u0437\u0443\u043c\u0435\u0432\u0430\u0435\u0442 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0438\u0440\u0443\u0435\u043c\u043e\u0441\u0442\u044c. \u0415\u0441\u043b\u0438 \u043c\u0430\u043b\u043e \u0440\u0435\u0441\u0443\u0440\u0441\u043e\u0432 \u0432 \u041f\u041b\u0418\u0421, \u0442\u043e \u043c\u043e\u0436\u043d\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0443\u0440\u0435\u0437\u0430\u043d\u043d\u0443\u044e \u0432\u0435\u0440\u0441\u0438\u044e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0438 \u0443 \u043d\u0435\u0433\u043e \u0431\u0443\u0434\u0435\u0442 \u043a \u043f\u0440\u0438\u043c\u0435\u0440\u0443 \u043d\u0435 32 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u0430 \u043e\u0431\u0449\u0435\u0433\u043e \u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u0438\u044f, \u0430 \u0442\u043e\u043b\u044c\u043a\u043e 16. \u0418\u043b\u0438 \u043c\u043e\u0436\u043d\u043e \u0441\u0434\u0435\u043b\u0430\u0442\u044c \u0432\u0435\u0440\u0441\u0438\u044e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0431\u0435\u0437 \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044f. \u0412\u0430\u0440\u0438\u0430\u043d\u0442\u043e\u0432 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u043c\u043e\u0436\u0435\u0442 \u0431\u044b\u0442\u044c \u0434\u043e\u0432\u043e\u043b\u044c\u043d\u043e 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\u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u0435\u043c, \u0441 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u043e\u0439 \u0441\u0436\u0430\u0442\u044b\u0445 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0439.\u0422\u0430\u043a\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c, \u043c\u043e\u0438 \u0442\u0435\u0441\u0442\u044b \u043a\u043e\u0441\u043d\u0443\u0442\u0441\u044f \u0434\u0432\u0443\u0445 \u0440\u0430\u0437\u043d\u044b\u0445 \u044f\u0434\u0435\u0440 \u0432 \u0434\u0432\u0443\u0445 \u0440\u0430\u0437\u043d\u044b\u0445 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f\u0445.\u0417\u0430\u043f\u0443\u0441\u043a\u0430\u0442\u044c \u044d\u0442\u0438 SOC \u044f \u0431\u0443\u0434\u0443 \u043d\u0430 \u043f\u043b\u0430\u0442\u0430\u0445 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343 \u0441 \u0447\u0438\u043f\u043e\u043c FPGA MAX10 50K \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u043e\u0432 \u0438 \u043d\u0430 \u043f\u043b\u0430\u0442\u0435 \u041c\u0430\u0440\u0441\u043e\u0445\u043e\u04343\u0431\u0438\u0441 \u0441 \u0447\u0438\u043f\u043e\u043c FPGA MAX10 8K \u043b\u043e\u0433\u0438\u0447\u0435\u0441\u043a\u0438\u0445 \u044d\u043b\u0435\u043c\u0435\u043d\u0442\u043e\u0432.\u041a\u0440\u043e\u043c\u0435 \u044d\u0442\u043e\u0433\u043e, \u044f \u0431\u0443\u0434\u0443 \u0437\u0430\u043f\u0443\u0441\u043a\u0430\u0442\u044c \u0442\u0435\u0441\u0442\u0431\u0435\u043d\u0447\u0438 \u0434\u043b\u044f \u0432\u0441\u0435\u0445 \u044d\u0442\u0438\u0445 \u0447\u0435\u0442\u044b\u0440\u0435\u0445 \u0441\u043b\u0443\u0447\u0430\u0435\u0432.\u0418\u0441\u0445\u043e\u0434\u043d\u0438\u043a\u0438 \u043c\u043e\u0435\u0433\u043e \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u0434\u043b\u044f \u0441\u0440\u0430\u0432\u043d\u0435\u043d\u0438\u044f \u044f\u0434\u0435\u0440 \u043d\u0430\u0445\u043e\u0434\u044f\u0442\u0441\u044f \u043d\u0430 github https:\/\/github.com\/marsohod4you\/riscv-compare \u0423\u0447\u0442\u0438\u0442\u0435, \u0447\u0442\u043e \u044d\u0442\u043e\u0442 \u043f\u0440\u043e\u0435\u043a\u0442 \u0432\u043a\u043b\u044e\u0447\u0430\u0435\u0442 \u0432 \u0441\u0435\u0431\u044f \u0441\u0443\u0431\u043c\u043e\u0434\u0443\u043b\u0438 git \u0434\u043b\u044f \u043a\u0430\u0436\u0434\u043e\u0433\u043e \u0438\u0437 \u044f\u0434\u0435\u0440 scr1 \u0438 picorv32.\u041a\u043b\u044e\u0447\u0435\u0432\u044b\u0435 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 PicoRV32, YosysHQPicoRV32 \u2014 \u044d\u0442\u043e \u043a\u043e\u043c\u043f\u0430\u043a\u0442\u043d\u043e\u0435 \u0438 \u0433\u0438\u0431\u043a\u043e\u0435 \u044f\u0434\u0440\u043e \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430, \u0440\u0435\u0430\u043b\u0438\u0437\u0443\u044e\u0449\u0435\u0435 \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u0443 RISC-V (RV32IMC) \u0438 \u043f\u0440\u0435\u0434\u043d\u0430\u0437\u043d\u0430\u0447\u0435\u043d\u043d\u043e\u0435 \u0434\u043b\u044f \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u043d\u0438\u044f \u0432 FPGA \u0438 ASIC. \u041e\u0441\u043d\u043e\u0432\u043d\u044b\u0435 \u043e\u0441\u043e\u0431\u0435\u043d\u043d\u043e\u0441\u0442\u0438:\u041e\u043f\u0442\u0438\u043c\u0438\u0437\u0430\u0446\u0438\u044f \u043f\u043e \u0440\u0430\u0437\u043c\u0435\u0440\u0443 \u0438 \u0447\u0430\u0441\u0442\u043e\u0442\u0435. \u0413\u0438\u0431\u043a\u0430\u044f \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f: \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442 \u0440\u0430\u0437\u043d\u044b\u0435 \u0432\u0430\u0440\u0438\u0430\u043d\u0442\u044b \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u043a\u043e\u043c\u0430\u043d\u0434 \u2014 RV32E, RV32I, RV32IC, RV32IM, RV32IMC. \u041c\u043e\u0436\u043d\u043e \u043e\u0442\u043a\u043b\u044e\u0447\u0430\u0442\u044c \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u044b x16\u2026x31, \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 RDCYCLE[H], RDTIME[H], RDINSTRET[H], \u0447\u0442\u043e \u0443\u043c\u0435\u043d\u044c\u0448\u0430\u0435\u0442 \u0440\u0430\u0437\u043c\u0435\u0440 \u044f\u0434\u0440\u0430. \u0418\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u044b: \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b \u0442\u0440\u0438 \u0432\u0430\u0440\u0438\u0430\u043d\u0442\u0430 \u044f\u0434\u0440\u0430 \u0441 \u0440\u0430\u0437\u043d\u044b\u043c\u0438 \u0448\u0438\u043d\u0430\u043c\u0438 \u2014 \u043f\u0440\u043e\u0441\u0442\u043e\u0439 native-\u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441, AXI4-Lite (picorv32_axi) \u0438 Wishbone (picorv32_wb), \u0447\u0442\u043e \u043e\u0431\u043b\u0435\u0433\u0447\u0430\u0435\u0442 \u0438\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u044e \u0432 \u0440\u0430\u0437\u043b\u0438\u0447\u043d\u044b\u0435 \u0441\u0438\u0441\u0442\u0435\u043c\u044b. \u041e\u043f\u0446\u0438\u043e\u043d\u0430\u043b\u044c\u043d\u044b\u0435 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u0438:\u0412\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u044b\u0439 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 IRQ. \u0418\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 \u0441\u043e\u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 (PCPI) \u0434\u043b\u044f \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u0438\u044f \u0441\u0438\u0441\u0442\u0435\u043c\u044b \u043a\u043e\u043c\u0430\u043d\u0434. \u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u0430\u043f\u043f\u0430\u0440\u0430\u0442\u043d\u044b\u0445 \u0443\u043c\u043d\u043e\u0436\u0438\u0442\u0435\u043b\u044f\/\u0434\u0435\u043b\u0438\u0442\u0435\u043b\u044f \u0438 barrel-shifter. \u0412\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u044c \u0432\u044b\u0431\u043e\u0440\u0430 \u043c\u0435\u0436\u0434\u0443 \u043e\u0434\u043d\u043e- \u0438 \u0434\u0432\u0443\u0445\u043f\u043e\u0440\u0442\u043e\u0432\u043e\u0439 \u043e\u0440\u0433\u0430\u043d\u0438\u0437\u0430\u0446\u0438\u0435\u0439 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432\u043e\u0433\u043e \u0444\u0430\u0439\u043b\u0430 \u0434\u043b\u044f \u0431\u0430\u043b\u0430\u043d\u0441\u0430 \u043c\u0435\u0436\u0434\u0443 \u0441\u043a\u043e\u0440\u043e\u0441\u0442\u044c\u044e \u0438 \u0440\u0430\u0437\u043c\u0435\u0440\u043e\u043c. \u0422\u0435\u0441\u0442\u0438\u0440\u043e\u0432\u0430\u043d\u0438\u0435 \u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430: \u0432 \u043f\u0440\u043e\u0435\u043a\u0442\u0435 \u0435\u0441\u0442\u044c \u043c\u043d\u043e\u0436\u0435\u0441\u0442\u0432\u043e \u0442\u0435\u0441\u0442\u0431\u0435\u043d\u0447\u0435\u0439, \u043f\u0440\u0438\u043c\u0435\u0440\u044b SoC, \u0433\u043e\u0442\u043e\u0432\u044b\u0435 \u043f\u0440\u043e\u0448\u0438\u0432\u043a\u0438 \u0438 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\u043d\u0430\u0431\u043e\u0440 \u043a\u043e\u043c\u0430\u043d\u0434 RV32I \u0438\u043b\u0438 RV32E \u0441 \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0441\u0442\u044c\u044e \u043f\u043e\u0434\u043a\u043b\u044e\u0447\u0435\u043d\u0438\u044f \u0440\u0430\u0441\u0448\u0438\u0440\u0435\u043d\u0438\u0439 RVM (\u0443\u043c\u043d\u043e\u0436\u0435\u043d\u0438\u0435\/\u0434\u0435\u043b\u0435\u043d\u0438\u0435) \u0438 RVC (\u0441\u0436\u0430\u0442\u044b\u0435 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438). \u0420\u0435\u0436\u0438\u043c\u044b \u043f\u0440\u0438\u0432\u0438\u043b\u0435\u0433\u0438\u0439: \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442 \u0442\u043e\u043b\u044c\u043a\u043e \u043c\u0430\u0448\u0438\u043d\u043d\u044b\u0439 \u0440\u0435\u0436\u0438\u043c \u043f\u0440\u0438\u0432\u0438\u043b\u0435\u0433\u0438\u0439 (Machine mode), \u0447\u0442\u043e \u0445\u0430\u0440\u0430\u043a\u0442\u0435\u0440\u043d\u043e \u0434\u043b\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u043d\u044b\u0445 \u044f\u0434\u0435\u0440. \u041a\u043e\u043d\u0432\u0435\u0439\u0435\u0440: 2\u20134 \u0441\u0442\u0430\u0434\u0438\u0438, \u0432 \u0437\u0430\u0432\u0438\u0441\u0438\u043c\u043e\u0441\u0442\u0438 \u043e\u0442 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438, \u0447\u0442\u043e \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0431\u0430\u043b\u0430\u043d\u0441\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u043c\u0435\u0436\u0434\u0443 \u043f\u0440\u043e\u0438\u0437\u0432\u043e\u0434\u0438\u0442\u0435\u043b\u044c\u043d\u043e\u0441\u0442\u044c\u044e \u0438 \u043f\u043b\u043e\u0449\u0430\u0434\u044c\u044e. \u0418\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u044b: 32-\u0431\u0438\u0442\u043d\u044b\u0439 \u0432\u043d\u0435\u0448\u043d\u0438\u0439 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441 AXI4 \u0438\u043b\u0438 AHB-Lite \u0434\u043b\u044f \u0438\u043d\u0442\u0435\u0433\u0440\u0430\u0446\u0438\u0438 \u0441 \u043f\u0435\u0440\u0438\u0444\u0435\u0440\u0438\u0435\u0439 \u0438 \u043f\u0430\u043c\u044f\u0442\u044c\u044e.\u0418\u043d\u0442\u0435\u0433\u0440\u0438\u0440\u043e\u0432\u0430\u043d\u043d\u044b\u0439 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0438\u0440\u0443\u0435\u043c\u044b\u0439 \u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 \u043f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u0439 (\u0434\u043e 16 \u043b\u0438\u043d\u0438\u0439 IRQ); \u041e\u0442\u043b\u0430\u0434\u043e\u0447\u043d\u0430\u044f \u043f\u043e\u0434\u0441\u0438\u0441\u0442\u0435\u043c\u0430 \u0441 \u0438\u043d\u0442\u0435\u0440\u0444\u0435\u0439\u0441\u043e\u043c JTAG; \u041e\u043f\u0446\u0438\u043e\u043d\u0430\u043b\u044c\u043d\u0430\u044f \u0442\u0435\u0441\u043d\u043e \u0441\u0432\u044f\u0437\u0430\u043d\u043d\u0430\u044f \u043f\u0430\u043c\u044f\u0442\u044c (TCM) \u0434\u043b\u044f \u0443\u0441\u043a\u043e\u0440\u0435\u043d\u0438\u044f \u0434\u043e\u0441\u0442\u0443\u043f\u0430 \u043a \u043a\u0440\u0438\u0442\u0438\u0447\u043d\u044b\u043c \u0434\u0430\u043d\u043d\u044b\u043c.\u042f\u0437\u044b\u043a \u043e\u043f\u0438\u0441\u0430\u043d\u0438\u044f: \u043d\u0430\u043f\u0438\u0441\u0430\u043d \u043d\u0430 SystemVerilog, \u0447\u0442\u043e \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0438\u0432\u0430\u0435\u0442 \u0445\u043e\u0440\u043e\u0448\u0443\u044e \u043f\u0435\u0440\u0435\u043d\u043e\u0441\u0438\u043c\u043e\u0441\u0442\u044c \u0438 \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0443 \u0432 \u0441\u043e\u0432\u0440\u0435\u043c\u0435\u043d\u043d\u044b\u0445 EDA-\u0441\u0440\u0435\u0434\u0430\u0445. \u041e\u043f\u0442\u0438\u043c\u0438\u0437\u0430\u0446\u0438\u044f: \u044f\u0434\u0440\u043e \u043e\u043f\u0442\u0438\u043c\u0438\u0437\u0438\u0440\u043e\u0432\u0430\u043d\u043e \u043f\u043e \u043f\u043b\u043e\u0449\u0430\u0434\u0438 \u0438 \u044d\u043d\u0435\u0440\u0433\u043e\u043f\u043e\u0442\u0440\u0435\u0431\u043b\u0435\u043d\u0438\u044e, \u043f\u043e\u0434\u0445\u043e\u0434\u0438\u0442 \u0434\u043b\u044f MCU-\u043a\u043b\u0430\u0441\u0441\u0430 \u0438 \u0432\u0441\u0442\u0440\u0430\u0438\u0432\u0430\u0435\u043c\u044b\u0445 \u0440\u0435\u0448\u0435\u043d\u0438\u0439. \u0413\u0438\u0431\u043a\u0430\u044f \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u044f: \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b \u0442\u0440\u0438 \u043f\u0440\u0435\u0434\u043e\u043f\u0440\u0435\u0434\u0435\u043b\u0451\u043d\u043d\u044b\u0435 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 (MAX, BASE, MIN), \u0430 \u0442\u0430\u043a\u0436\u0435 \u043c\u043d\u043e\u0436\u0435\u0441\u0442\u0432\u043e \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u0432 \u0434\u043b\u044f \u0442\u043e\u043d\u043a\u043e\u0439 \u043d\u0430\u0441\u0442\u0440\u043e\u0439\u043a\u0438 \u043f\u043e\u0434 \u043a\u043e\u043d\u043a\u0440\u0435\u0442\u043d\u044b\u0435 \u0437\u0430\u0434\u0430\u0447\u0438. \u0412\u0435\u0440\u0438\u0444\u0438\u043a\u0430\u0446\u0438\u044f \u0438 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u044f: \u043f\u0440\u043e\u0435\u043a\u0442 \u0441\u043e\u043f\u0440\u043e\u0432\u043e\u0436\u0434\u0430\u0435\u0442\u0441\u044f \u043e\u0431\u0448\u0438\u0440\u043d\u043e\u0439 \u0434\u043e\u043a\u0443\u043c\u0435\u043d\u0442\u0430\u0446\u0438\u0435\u0439, \u0442\u0435\u0441\u0442\u043e\u0432\u044b\u043c\u0438 \u043d\u0430\u0431\u043e\u0440\u0430\u043c\u0438 (\u0432\u043a\u043b\u044e\u0447\u0430\u044f \u0442\u0435\u0441\u0442\u044b \u043d\u0430 \u0441\u043e\u043e\u0442\u0432\u0435\u0442\u0441\u0442\u0432\u0438\u0435 RISC-V ISA, Dhrystone, CoreMark), \u0430 \u0442\u0430\u043a\u0436\u0435 \u043f\u0440\u0438\u043c\u0435\u0440\u0430\u043c\u0438 \u0434\u043b\u044f \u0431\u044b\u0441\u0442\u0440\u043e\u0433\u043e \u0441\u0442\u0430\u0440\u0442\u0430. \u041f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u0430 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u043e\u0432 \u0438 \u043f\u043b\u0430\u0442\u0444\u043e\u0440\u043c: \u0441\u043e\u0432\u043c\u0435\u0441\u0442\u0438\u043c \u0441 \u043e\u0441\u043d\u043e\u0432\u043d\u044b\u043c\u0438 \u043f\u0440\u043e\u043c\u044b\u0448\u043b\u0435\u043d\u043d\u044b\u043c\u0438 \u0441\u0438\u043c\u0443\u043b\u044f\u0442\u043e\u0440\u0430\u043c\u0438 (Verilator, ModelSim, VCS, NCSim), \u041f\u043e\u0434\u0434\u0435\u0440\u0436\u0438\u0432\u0430\u0435\u0442\u0441\u044f \u0441\u0431\u043e\u0440\u043a\u0430 \u0438 \u0437\u0430\u043f\u0443\u0441\u043a \u043d\u0430 \u043f\u043e\u043f\u0443\u043b\u044f\u0440\u043d\u044b\u0445 \u043e\u0442\u043b\u0430\u0434\u043e\u0447\u043d\u044b\u0445 \u043f\u043b\u0430\u0442\u0430\u0445 (Arty, Nexys 4 DDR, DE10-Lite \u0438 \u0434\u0440.). \u042d\u043a\u043e\u0441\u0438\u0441\u0442\u0435\u043c\u0430: \u043a \u044f\u0434\u0440\u0443 \u043f\u0440\u0438\u043b\u0430\u0433\u0430\u0435\u0442\u0441\u044f SDK \u0441 \u0437\u0430\u0433\u0440\u0443\u0437\u0447\u0438\u043a\u043e\u043c, \u043f\u043e\u0434\u0434\u0435\u0440\u0436\u043a\u043e\u0439 Zephyr RTOS, \u043f\u0440\u0438\u043c\u0435\u0440\u0430\u043c\u0438 \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u043d\u043e\u0433\u043e \u043e\u0431\u0435\u0441\u043f\u0435\u0447\u0435\u043d\u0438\u044f \u0438 \u0440\u0443\u043a\u043e\u0432\u043e\u0434\u0441\u0442\u0432\u0430\u043c\u0438 \u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044f. SCR1 \u2014 \u043e\u0434\u043d\u043e \u0438\u0437 \u0441\u0430\u043c\u044b\u0445 \u043f\u043e\u043f\u0443\u043b\u044f\u0440\u043d\u044b\u0445 \u043e\u0442\u043a\u0440\u044b\u0442\u044b\u0445 \u044f\u0434\u0435\u0440 RISC-V \u0434\u043b\u044f \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440\u043e\u0432, \u0448\u0438\u0440\u043e\u043a\u043e \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u043c\u043e\u0435 \u043a\u0430\u043a \u0432 \u043e\u0431\u0440\u0430\u0437\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0445, \u0442\u0430\u043a \u0438 \u0432 \u043a\u043e\u043c\u043c\u0435\u0440\u0447\u0435\u0441\u043a\u0438\u0445 \u043f\u0440\u043e\u0435\u043a\u0442\u0430\u0445. \u0420\u043e\u0441\u0441\u0438\u0439\u0441\u043a\u0438\u0439 RISC-V \u043c\u0438\u043a\u0440\u043e\u043a\u043e\u043d\u0442\u0440\u043e\u043b\u043b\u0435\u0440 \u0410\u043c\u0443\u0440 \u043a\u0430\u0436\u0435\u0442\u0441\u044f \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u0435\u0442 \u043e\u0447\u0435\u043d\u044c \u043f\u043e\u0445\u043e\u0436\u0435\u0435 \u044f\u0434\u0440\u043e, \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e \u044d\u0442\u043e \u0436\u0435 \u0441\u0430\u043c\u043e\u0435 (\u043d\u043e \u044d\u0442\u043e \u043d\u0435 \u0442\u043e\u0447\u043d\u043e).\u0421\u0432\u043e\u044e SOC \u043d\u0430 \u043e\u0441\u043d\u043e\u0432\u0435 SCR1 \u044f \u0442\u0430\u043a \u0436\u0435 \u0434\u0435\u043b\u0430\u044e \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e\u0439. \u0412 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0435 \u0443\u0436\u0435 \u0435\u0441\u0442\u044c \u0432\u0441\u0442\u0440\u043e\u0435\u043d\u043d\u0430\u044f TCM (Tightly Coupled Memory) \u043f\u0430\u043c\u044f\u0442\u044c. \u0421 \u043f\u043e\u043c\u043e\u0449\u044c\u044e \u043a\u0430\u0441\u0442\u043e\u043c\u043d\u043e\u0439 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430 \u044f \u0443\u0441\u0442\u0430\u043d\u0430\u0432\u043b\u0438\u0432\u0430\u044e \u0435\u0451 \u0440\u0430\u0437\u043c\u0435\u0440 \u0432 32\u041a \u0438 \u0440\u0430\u0437\u043c\u0435\u0449\u0430\u044e \u0435\u0451 \u043f\u043e \u0430\u0434\u0440\u0435\u0441\u0443 \u043d\u043e\u043b\u044c. \u041c\u043e\u0439 \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440 \u0442\u0430\u043a \u0436\u0435 \u0431\u0443\u0434\u0435\u0442 \u0441\u0442\u0430\u0440\u0442\u043e\u0432\u0430\u0442\u044c \u0441 \u0430\u0434\u0440\u0435\u0441\u0430 \u043d\u043e\u043b\u044c \u043f\u0440\u044f\u043c\u043e \u0432 TCM. \u041f\u0440\u0435\u0440\u044b\u0432\u0430\u043d\u0438\u044f \u044f \u043d\u0435 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e. \u041d\u0430 \u0432\u043d\u0435\u0448\u043d\u0435\u0439 \u0448\u0438\u043d\u0435 \u0441\u0442\u0430\u0432\u043b\u044e \u043f\u043e \u0442\u0435\u043c \u0436\u0435 \u0430\u0434\u0440\u0435\u0441\u0430\u043c \u043f\u043e\u0441\u043b\u0435\u0434\u043e\u0432\u0430\u0442\u0435\u043b\u044c\u043d\u044b\u0439 \u043f\u043e\u0440\u0442, \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u0441\u0435\u043c\u0438-\u0441\u0435\u0433\u043c\u0435\u043d\u0442\u043d\u043e\u0433\u043e \u0438\u043d\u0434\u0438\u043a\u0430\u0442\u043e\u0440\u0430 \u0438 \u0440\u0435\u0433\u0438\u0441\u0442\u0440 \u043e\u0441\u0442\u0430\u043d\u043e\u0432\u0430 \u043f\u0440\u0438 \u0441\u0438\u043c\u0443\u043b\u044f\u0446\u0438\u0438:\u041c\u043e\u044f scr1 SOC\u0422\u0430\u043a\u0438\u043c \u043e\u0431\u0440\u0430\u0437\u043e\u043c, \u0430\u0440\u0445\u0438\u0442\u0435\u043a\u0442\u0443\u0440\u043d\u043e \u043e\u0431\u0435 \u043f\u0440\u043e\u0435\u043a\u0442\u0438\u0440\u0443\u0435\u043c\u044b\u0435 \u043c\u043d\u043e\u044e SOC \u0431\u0443\u0434\u0443\u0442 \u0438\u0434\u0435\u043d\u0442\u0438\u0447\u043d\u044b\u043c\u0438:\/\/ 8K 32bit words = 32Kbytes memory localparam MEM_SIZE = (1024*32); \/\/at address zero localparam SERIAL_PORT_ADDR = 32\u2019h1000_0000; localparam SEG7_PORT_ADDR = 32\u2019h1000_0004; localparam SIMSTOP_PORT_ADDR = 32\u2019h1000_1000;\u041a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u0435\u043c \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u0443 Dhrystone\u0421\u043a\u043b\u043e\u043d\u0438\u0440\u0443\u0439\u0442\u0435 \u043c\u043e\u0439 \u043f\u0440\u043e\u0435\u043a\u0442 \u0441 github \u0432\u043c\u0435\u0441\u0442\u0435 \u0441 \u0441\u0443\u0431\u043c\u043e\u0434\u0443\u043b\u044f\u043c\u0438:git clone &#8212;recurse-submodules https:\/\/github.com\/marsohod4you\/riscv-compare.git\u041f\u0435\u0440\u0435\u0439\u0434\u0438\u0442\u0435 \u0432 \u0434\u0438\u0440\u0435\u043a\u0442\u043e\u0440\u0438\u044e \u0421\u0438 \u043f\u0440\u043e\u0435\u043a\u0442\u0430:cd riscv-compare\/dhrystone-fw\/\u0412\u043e\u0437\u043c\u043e\u0436\u043d\u043e \u0432\u0430\u043c \u043f\u043e\u0442\u0440\u0435\u0431\u0443\u0435\u0442\u0441\u044f \u0438\u0441\u043f\u0440\u0430\u0432\u0438\u0442\u044c \u0432 \u0441\u043a\u0440\u0438\u043f\u0442\u0435 build.sh \u0441\u0442\u0440\u043e\u043a\u0443 export PATH=$PATH: \u0438 \u0434\u043e\u0431\u0430\u0432\u0438\u0442\u044c \u0442\u0443\u0434\u0430 \u0438\u043c\u0435\u043d\u043d\u043e \u0432\u0430\u0448\u0438 \u043f\u0443\u0442\u0438 \u043a \u0442\u0443\u043b\u0447\u0435\u0439\u043d\u0443 risc-v \u0438 \u043a \u043f\u0438\u0442\u043e\u043d\u0443. \u041d\u0430\u043f\u043e\u043c\u043d\u044e, \u0447\u0442\u043e \u044f \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044e \u0442\u0443\u043b\u0447\u0435\u0439\u043d \u0432\u0437\u044f\u0442\u044b\u0439 \u0432\u043e\u0442 \u0437\u0434\u0435\u0441\u044c: https:\/\/syntacore.com\/tools\/development-tools\u0417\u0430\u043f\u0443\u0441\u0442\u0438\u0442\u0435 \u0441\u043a\u0440\u0438\u043f\u0442 build.sh \u0441 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u043e\u043c EC \u0438\u043b\u0438 IM. \u042d\u0442\u0438 \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440\u044b \u043a\u0430\u043a \u0440\u0430\u0437 \u0431\u0443\u0434\u0443\u0442 \u043e\u043f\u0440\u0435\u0434\u0435\u043b\u044f\u0442\u044c \u043a\u0430\u043a\u043e\u0439 \u043a\u043e\u0434 \u0433\u0435\u043d\u0435\u0440\u0438\u0440\u043e\u0432\u0430\u0442\u044c. EC \u044d\u0442\u043e \u0434\u043b\u044f \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0441 \u043c\u0438\u043d\u0438\u043c\u0430\u043b\u044c\u043d\u043e\u0439 \u043a\u043e\u043d\u0444\u0438\u0433\u0443\u0440\u0430\u0446\u0438\u0435\u0439, embedded, \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0442\u043e\u0440 gcc \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0442\u043e\u043b\u044c\u043a\u043e 16 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432, \u043d\u0435 \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043e\u043f\u0435\u0440\u0430\u0446\u0438\u0438 \u0443\u043c\u043d\u043e\u0436\u0435\u043d\u0438\u044f, \u043d\u043e \u0431\u0443\u0434\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u0441\u0436\u0430\u0442\u044b\u0439 \u043a\u043e\u0434. \u0421\u0436\u0430\u0442\u044b\u0439 \u043a\u043e\u0434 \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u043e\u0432\u0430\u0442\u044c \u043a\u043e\u0440\u043e\u0442\u043a\u0438\u0435 16\u0442\u0438 \u0431\u0438\u0442\u043d\u044b\u0435 \u043a\u043e\u043c\u0430\u043d\u0434\u044b \u043f\u0440\u043e\u0446\u0435\u0441\u0441\u043e\u0440\u0430 \u0435\u0441\u043b\u0438 \u044d\u0442\u043e \u0432\u043e\u0437\u043c\u043e\u0436\u043d\u043e. \u042d\u0442\u043e \u043f\u043e\u0437\u0432\u043e\u043b\u044f\u0435\u0442 \u044d\u043a\u043e\u043d\u043e\u043c\u0438\u0442\u044c \u043c\u0435\u0441\u0442\u043e \u043f\u0440\u043e\u0433\u0440\u0430\u043c\u043c\u044b. \u041f\u0440\u0438 \u044d\u0442\u043e\u043c 32\u0445 \u0431\u0438\u0442\u043d\u044b\u0435 \u0438\u043d\u0441\u0442\u0440\u0443\u043a\u0446\u0438\u0438 \u043a\u043e\u043d\u0435\u0447\u043d\u043e \u0432\u0441\u0451 \u0435\u0449\u0435 \u0434\u043e\u0441\u0442\u0443\u043f\u043d\u044b.\u0415\u0441\u043b\u0438 \u0437\u0430\u0434\u0430\u0442\u044c \u043f\u0430\u0440\u0430\u043c\u0435\u0442\u0440 IM, \u0442\u043e \u0441\u043a\u0440\u0438\u043f\u0442 \u0431\u0443\u0434\u0435\u0442 \u0433\u0435\u043d\u0435\u0440\u0438\u0440\u043e\u0432\u0430\u0442\u044c \u043a\u043e\u0434 \u0441 \u0443\u0447\u0435\u0442\u043e\u043c \u043d\u0430\u043b\u0438\u0447\u0438\u044f 32\u0445 \u0440\u0435\u0433\u0438\u0441\u0442\u0440\u043e\u0432 \u0438 \u0438\u0441\u043f\u043e\u043b\u044c\u0437\u0443\u044f \u043a\u043e\u043c\u0430\u043d\u0434\u044b \u0443\u043c\u043d\u043e\u0436\u0435\u043d\u0438\u044f \u0435\u0441\u043b\u0438 \u043d\u0443\u0436\u043d\u043e.\u041a\u043e\u043c\u043f\u0438\u043b\u0438\u0440\u0443\u044e \u0441\u043a\u0440\u0438\u043f\u0442\u043e\u043c:.\/build.sh IM.\/build.sh EC\u041f\u043e\u0441\u043b\u0435 \u043a\u043e\u043c\u043f\u0438\u043b\u044f\u0446\u0438\u0438 \u043f\u043e\u044f\u0432\u044f\u0442\u0441\u044f \u043d\u043e\u0432\u044b\u0435 \u0434\u0438\u0440\u0435\u043a\u0442\u043e\u0440\u0438\u0438 riscv-compare\/dhrystone\/done_ec \u0438 riscv-compare\/dhrystone\/done_im. \u0412 \u043d\u0438\u0445 \u0440\u0435\u0437\u0443\u043b\u044c\u0442\u0438\u0440\u0443\u044e\u0449\u0438\u0435 \u0444\u0430\u0439\u043b\u044b \u0438 \u0432\u044b \u043c\u043e\u0436\u0435\u0442\u0435&#8230;<\/p>\n","protected":false},"author":1,"featured_media":0,"comment_status":"closed","ping_status":"closed","sticky":false,"template":"","format":"standard","meta":{"footnotes":""},"categories":[],"tags":[],"class_list":["post-477279","post","type-post","status-publish","format-standard","hentry"],"_links":{"self":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/477279","targetHints":{"allow":["GET"]}}],"collection":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts"}],"about":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/types\/post"}],"author":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/users\/1"}],"replies":[{"embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcomments&post=477279"}],"version-history":[{"count":0,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=\/wp\/v2\/posts\/477279\/revisions"}],"wp:attachment":[{"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fmedia&parent=477279"}],"wp:term":[{"taxonomy":"category","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Fcategories&post=477279"},{"taxonomy":"post_tag","embeddable":true,"href":"https:\/\/savepearlharbor.com\/index.php?rest_route=%2Fwp%2Fv2%2Ftags&post=477279"}],"curies":[{"name":"wp","href":"https:\/\/api.w.org\/{rel}","templated":true}]}}