The next steps after a good meetup on Portable SystemVerilog Examples for ASIC and FPGA

The meetup on January 14 at Hacker Dojo in Mountain View, California, went well, although not as planned — we spent almost all the time talking instead of doing hands-on exercises. The room we booked can fit 30 people and approximately 30 people did show up. The quality of participants was high: approximately half were familiar with hardware description languages and another half came from various software topics. 12 people filled out the questionnaire despite the fact that I forgot to bring 30 pens.

The discussion during and after the presentation was focused and very meaningful: microarchitecture and education, EDA infrastructure / build scripts, open-source ASIC design tools, the economics of ASIC design and manufacturing, high-level synthesis, transaction-level modeling, ASIC prototyping using FPGA boards, FPGA embedded in ASIC (Menta), new FPGA manufacturers (Gowin) and new design languages — Chisel and SpinalHDL.

Four persons came to me after the meeting to discuss their participation in working on open-source portable SystemVerilog examples, and another seven expressed this intention in the questionnaire. So we are meeting again in Hacker Dojo on Sunday, January 21, at 2 PM, this time not in the classroom area, but in the common shared area.

Generally, I am thinking of having regular meetings, probably on a weekly basis for a small team of developers of the educational materials and on a monthly basis for a wider audience, discussing various design and verification topics.

There were two correspondents of Slavic Sacramento who recorded the video of the presentation:

The information to run the examples

While I did show four persons how to run the examples, I had to print an instruction and put it near every computer, which I did not. After the meeting, I inserted three slides into the presentation with a brief instruction. The instruction works both under Linux and Windows, although in order to run Bash scripts under Windows you have to use Bash from Git for Windows.

Slide 8:

The public project repositories

1. https://github.com/yuri-panchul/basics-graphics-music

2. https://github.com/yuri-panchul/systemverilog-homework

   1. This is a public version of the corresponding private repository. The private repository contains solutions to all the problems

3. valid-ready-etc — under construction

Slide 9:

How to start working with the examples

1. Install the applicable toolchain

2. Connect the board

3. git clone https://github.com/yuri-panchul/basics-graphics-music.git

4. cd basics-graphics-music/labs/07_binary_counter

5. ./03_synthesize_for_fpga.bash

6. After the synthesis finishes, you should see the running lights

7. If anything goes wrong, the script will tell you what to do

Slide 10:

How to start working with the examples — more details

1. git clone https://github.com/yuri-panchul/basics-graphics-music.git

   • If the repository already cloned, cd inside and “git pull” to get the latest version

2. cd basics-graphics-music

3. ./check_setup_and_choose_fpga_board.bash

   • You need to do it only the first time

4. cd labs/07_binary_counter

   • Or any other labs/* you like

5. ./03_synthesize_for_fpga.bash

6. ./04_configure_fpga.bash

   • You need to run it only if the synthesis script failed at the end because the board is not connected. You don’t need to re-run the synthesis; connect the board and run configuration only

7. ./06_choose_another_fpga_board.bash

   • Run this script if you want to try another board

Slide 7:

The software we are using

1. Intel Quartus Prime Lite 23.1

2. Altera Quartus II Web Edition 13.0sp1 for older boards

3. AMD Xilinx Vivado ML Standard Edition 2023.2

4. Gowin V1.9.9Beta-4 Education

5. Gowin Programmer V1.9.9 Beta-4 Education

6. openFPGALoader

7. Icarus Verilog v12.0

8. GTKWave

9. OpenLane

10. Planned for the future: OSS CAD Suite from YosysHQ and EDA tools from Lattice

The plan for the next meeting

During the next meeting of the small working group, tentatively on Sunday, January 21, I plan to focus on working with code and boards, with no presentations. First, we are going to run all the examples in four to six repositories:

1. https://github.com/yuri-panchul/basics-graphics-music

2. The private variant of https://github.com/yuri-panchul/systemverilog-homework

3. valid-ready-etc-private

4. https://github.com/zhelnio/schoolRISCV

5. Maybe https://github.com/yuri-panchul/yrv-plus

6. Maybe https://github.com/MPSU/MIRISCV to explore its potential

Then we need to start working on the current needs:

1. The boards I have support different numbers of bits per color channel for exercises with graphics: from 1 to 8 bits per channel. The current board wrappers assume 4 bits per channel. Somebody needs to modify all the board wrappers and graphic examples to support adjustable quality via parameterization.

2. We need to update the microarchitectural examples in valid-ready-etc-private with the scripts from basics-graphics-music to make these examples run on all the boards we have.

3. We need to formulate a new list of examples, including the examples that feature credit-based flow control and other popular design techniques.

4. We need to add examples of multiple RISC-V cores sharing the same memory (with or without banking) and exchanging messages via FIFOs.

5. We need to make the scripts compatible with Windows Subsystem for Linux (WSL). Right now they either run under Linux or under Windows using Git for Windows.

6. We need to explore the Lattice commercial toolchain.

7. We need to validate the open-source YosysHQ toolchains for Gowin and Lattice. This support was put together by Ruslan Zalata, but I never tried it.

8. We have plenty of ideas to support new peripherals. The most needed is UART to connect to a computer using USB-to-UART. It is implemented in bits and pieces, but we need a solution that works with both Linux and Windows. It should include a console to interact with the example designs plus a file transfer capability.

9. Examples of work with SDRAM are urgently needed, as well as examples of memory-based FIFO with prefetch to hide latency. The challenge is: boards have different SDRAMs + there is at least one board with SRAM, Digilent Cmod S7.

10. Solder all unsoldered headers, review pin connectivity for ergonimics, and support all not yet supported Gowin, Altera, and Xilinx boards we have on hand.

11. Document everything.

12. Make all examples compatible with the open-source ASIC toolchain.

13. We need to create a proposal for a hackathon in Hacker Dojo using the devpost.com website.

Let’s finalize the meeting time and start working on those subjects.